JPS5819968A - Address designating system - Google Patents

Abstract

PURPOSE:To shorten the processing time, by giving the same absolute addresses as respective terminal registers to shared registers and giving the same relative addresses to lower areas of respective terminals and giving these addresses to areas to which shared registers do not correspond. CONSTITUTION:When a control interrupt is given to a CPU1, the CPU1 analyzes terminal machine numbers 40-4F to obtain an absolute address and stores it in an RAM2. The absolute address designates a terminal register and designates the storage area of a corresponding working register 4 with upper 2 digits, for example, 40-4F. The CPU1 calculates addresses of terminal registeres 40-4F or the address of the working register 4 to be accesses and gives relative addresses 00-FF to the working register 4 and gives relative addresses F8-FF to respective terminal registers 40-4F. The working register has address 4000- 4FFF, and terminal registers have addresses 40F8-4FFF. Thus, the time for address allocation is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an addressing system, and more particularly, to an addressing system in a central processing unit that includes a shared memory that is connected to a plurality of terminals and that is commonly used by each terminal. Regarding.

FIG. 1 is a schematic block diagram showing a conventional computer control system that is the background of this invention.

In the configuration, CPU1 has ILAM2 and 110M
3 is connected. The RAM 2 includes a storage area as shown in FIG. Further, the ROM 3 stores an operating program as shown in FIG. Furthermore, CI'Ul includes a single king register 4 and terminal registers 5G, 51 .
-5F is connected. Terminal registers 50 to 5F are C
I'Ul [A memory provided in a terminal whose operation is controlled, and includes a plurality of registers, but for convenience it is called a terminal register. Also, the working register 4 stores data from each terminal, It stores data files related to each terminal and is used as a shared memory commonly used by multiple terminals. The storage area of the Noriichi King Register 4 is divided and used for terminal identification.

That is, the CPU 1, the RAM 2, the ROM 3, and the working register 4 constitute a central processing unit for data processing, where ≠−S+4≠−1=4−.

Here, the working register 4 and the terminal register 50
Address designation of 5th to 5th floors will be explained. Working register 4 and terminal registers 50 to 5F are assigned, for example, four-digit hexadecimal addresses. For example, working register 4 is assigned addresses 400G to 4FFF. Further, addresses 5ooo to 59FF are assigned to the terminal register 50, addresses 5100 to 51FF are assigned to the terminal register 51, and addresses 5F00 to 5FFF are assigned to the terminal register 5F in the same manner.

Note that the terminal registers 5o to 5F as described above are used, for example, as buffer registers for temporarily storing data generated in the terminal and transmitting it to the CPUI, and their storage capacity is relatively small.

On the other hand, the working register 4 is the terminal register 50.
The storage capacity is relatively large because it cumulatively stores data transmitted from 5F' to 5F' and stores data files used in each terminal. For example, taking an electronic cash register (hereinafter referred to as FICCI) as an example, the terminal register included in the KCI as a terminal temporarily stores, for example, W, CR key inputs, etc. In contrast, the working register is
It stores CI registration data cumulatively and cumulatively, and stores tables in which the unit price of each product is set for each product code. By the way, in the system shown in FIG. 1, the number of addresses assigned to each terminal register is equal to the number of addresses assigned to the corresponding storage area of the working register. However, since the storage capacity of each terminal register is small as described above, storage areas do not exist for all assigned addresses. That is, most of the addresses assigned to each terminal register are empty addresses.

Now, in the four-digit hexadecimal address described above, the most significant digit specifies whether it is on the working register side or the terminal register side.

In addition, the second digit from the top specifies whether it is compatible with Izugo's terminal. Further, the lower two digits specify addresses within each storage area of the working register 4 and within each terminal register.

When looking at the four-digit address mentioned above based on the specification of each terminal, in the absolute specification method, the absolute address of the upper two digits is different on the working register side and the terminal register side, and this is different. The reverse number relative register corresponds to the working register side and the terminal register steel.

2 is a diagram showing a part of the storage area of the RAM 2.

As shown in FIG. 2, the RAM 2 includes a start address table that stores the start address of each terminal register and the start address of the corresponding storage area of the working register 4 for each terminal number.

When specifying the address of king register 4 or terminal register 50 to 5F in this address table,
Used to obtain absolute addresses.

FIG. 3 is a flowchart for explaining operations related to addressing in the computer control system of FIG. 1. First, when the CPU is given an interrupt to control a terminal, the CPU analyzes the terminal number to determine which terminal should be controlled, and stores the analyzed terminal number in the RAM 2. Next, the CPU reads out the start address of the storage area in the terminal register and working register corresponding to the terminal number stored in the RAM 2 from the address table shown in FIG. 2 and stores it in the RAM 2. In other words, we are looking for an absolute address here. Then, the address of the terminal register or working register to be accessed is calculated. This calculation is RA
This is done by adding a predetermined address, that is, a relative address, to the top address of the terminal register and working register stored in M2.

As mentioned above, in the conventional addressing system, the absolute address assigned to the working register 4 is different from the absolute address assigned to the terminal registers 50 to 5F. Therefore, after analyzing the terminal number, Cpul must obtain the absolute address of the working register 4 and the absolute address of the terminal registers 50 to 5F.

Therefore, a leading address table for each terminal number as shown in FIG. 2 is required, which has the drawback of increasing the storage capacity of the RAM 2. In addition, in order to read a desired address from this first address table, the terminal numbers are sequentially read from the first address table, compared with the analyzed terminal number, and when they match, the corresponding first address is read. I have to get it out. Therefore, the operation program becomes complicated and the processing time becomes long. In particular, in a program that requires many address specifications, the above-mentioned operation must be performed each time, which increases the processing time.

Therefore, the main object of the present invention is to provide an addressing system that eliminates the above-mentioned drawbacks and allows faster processing related to addressing.

In summary, the present invention provides the following advantages: when specifying an address in a storage area included in a terminal device and consisting of a relatively small number of addresses, and an address in a shared memory consisting of a relatively large number of addresses included in the central processing unit, It is specified by a combination of an absolute address and a relative address, and the same absolute address is assigned to the storage area of the terminal and the storage area of the shared memory corresponding to the terminal, and the storage area of the shared memory is assigned to each terminal. A plurality of different relative addresses are assigned within the same storage area corresponding to a machine, and a plurality of the same relative addresses are assigned between each storage area.

FIG. 4 is a schematic block diagram showing a computer control system using an embodiment of the present invention.

In the configuration, as in the $1 figure, CPU1 has iLAM2.
and mouse OM3 are connected. Note that RAM2 has a second
The address table shown in the figure is not stored,
Further, the ROM 3 stores an operation program as shown in FIG. 5, for example. Furthermore, cpul has working register 4 and terminal registers 40 to 4Y.
is connected. This terminal register 40 to 4F is the first
Similarly to the figure, this is a memory included in each terminal controlled by CI'U1.Furthermore, a prohibition circuit 5 is connected to CI'U1.This prohibition circuit 5 includes, for example, a decoder, etc. When outputting address designation data of terminal registers 40 to 4F, a continuous output prohibition signal is given to working register 4.

Here, working register 4 and terminal register 40
I will briefly explain the address designation of 4F.

First, the working register 4 is assigned four-digit addresses 4000 to 4FFF in hexadecimal notation as in FIG. Further, four-digit addresses 40FB to 49FF displayed in the terminal register X 401116m are assigned, addresses 41FB to 41FF are assigned to the terminal register 41, and addresses 4vvB to 4FFF are assigned to the terminal register 4F in the same manner.

Thus, in the addressing scheme according to this embodiment,
The most significant digits of the four-digit hexadecimal address are all the same, and the second most significant digit specifies which terminal the address corresponds to. That is, absolute addresses are commonly determined for the storage areas of the working register 4 corresponding to each terminal and the terminal registers 40 to 4F. Furthermore, the lower two digits of the four-digit hexadecimal address, that is, the relative address, is a plurality of starting addresses "00" to "j" for each storage area corresponding to each terminal in the working register 4.
FFJ is assigned. A plurality of different relative addresses "F8" to jFFJ are assigned to each terminal register. Therefore, the relative addresses overlap only on the terminal register side and on the king register side. That is,
In this overlapping area (shaded area in FIG. 4), the same address is assigned to the working register 4 and the terminal registers 40 to 4F.

As described above, the terminal registers 40 to 4F are used, for example, as buffer registers for data transmission between the terminal and the CPU, and their storage capacity is relatively small.

In contrast, the storage capacity of the working register 4 is much larger. That is, the storage capacity of the corresponding storage area in the belly king register 4 is extremely large compared to the storage capacity of each terminal register. Therefore, the number of addresses allocated to the terminal register may be smaller than the number of addresses allocated to the corresponding storage area in the counting register 4. That is, the number of addresses assigned to the terminal registers 40 to 4F shown in FIG. 4 is smaller than that of the terminal registers 50 to 5F shown in FIG. 1, but this does not mean that the storage capacity is smaller. In addition, in the working register 4, the part that overlaps with the address of each terminal register (the shaded part) is an empty area that is not used for data processing, but this empty area is not used for the entire storage of the king register 4. It is very small compared to its capacity. Normally, the storage capacity of the working register is set with a margin to prevent overflow, but it is possible to include the empty area in the margin.

Now, in the embodiment shown in FIG. 4, since the addresses of the beam register 4 and the terminal registers 40 to 4F are specified as described above, each storage area of the working register 4 contains the address of the corresponding terminal register. An overlapping portion occurs. Therefore, if an attempt is made to specify an address within the terminal register, an overlapping address in the corresponding storage area of the working register 4 will also be specified. Therefore, when reading data from a terminal register, especially when data continues to be output, the data contents of the working register 4 having an address that overlaps with the address of the terminal register will also be read. Therefore, in FIG. 4, a prohibition circuit 5 is provided, and when the address data from the cpul specifies the address of one of the terminal registers, a successive prohibition signal is derived to the working register 4, and reading is prohibited. . by this,
CPU 1 can read data only from desired terminal registers.

FIG. 5 is a flowchart for explaining operations related to addressing in the computer control system of FIG. 4. The operation related to address designation in FIG. 4 will be described below with reference to FIG. 5.

First, when a terminal control interrupt is given to the CPUI,
The CPUI analyzes the terminal number to determine which terminal should be controlled. Then, based on the analyzed terminal number, the corresponding absolute address is determined and stored in the RAM 2. As described above, the absolute address specifies which terminal register it is and also specifies the storage area of the working register 4 corresponding to that terminal register. Therefore, it is no longer necessary to provide an address table in the iLAM 2 as in the system shown in FIG. 1 and to obtain the start address of the terminal register and q working register corresponding to the analyzed terminal number based on the address table. Therefore, compared to the system shown in FIG. 1, the processing time for address specification can be reduced. Also, R
The storage capacity of AM2 can be reduced. jI again
5fl! Referring to J, cpul calculates the address of the terminal register or algorithm register to be accessed. That is, the relative address is determined by this calculation.

Furthermore, if the data indicating the terminal number given to CI'Ul at the time of a terminal control interrupt is given in the form of an absolute address from the beginning, there will be no need to analyze the terminal number, further improving processing speed. The person who will do it will come.

In addition, in the above-mentioned embodiment, the beam register 4 and the RAM
Although the working register 4 is provided separately from the RAM 2, the working register 4 may be included in the RAM 2.

Furthermore, in the above-described embodiment, the address is specified using a four-digit number expressed in 1G decimal, and the upper two digits are used as an absolute address and the lower two digits are used as a relative address, but the present invention is not limited to this. Not sure. For example, 1
You can specify the address using numbers in decimal notation (or you can change the number of digits for the absolute address and relative address depending on the capacity of the terminal register and the number of digits in the address). According to this invention, the same absolute address is assigned to the terminal identification corresponding to the storage area on the terminal side and the shared memory, and the storage area of the shared memory has a plurality of different addresses within the same storage area corresponding to each terminal. Since relative addresses are allocated and a plurality of the same relative addresses are allocated between each storage area, the processing time for address specification can be reduced compared to the conventional addressing method.

Further, there is no need to provide a head address table unlike the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing a conventional computer control system that is the background of this invention. FIG. 2 is a diagram showing the storage area of RAM2. FIG. 3 is a flowchart for explaining operations related to addressing in the system of FIG. 1. FIG. 4 is a schematic block diagram showing a computer control system in which the addressing scheme according to the present invention is used. FIG. 5 is a flowchart for explaining operations related to addressing in the system of FIG. 4. In the figure, 1 is the CPU, 4 is the working register, and 5 is the CPU.
indicates a prohibition circuit, and 4G or 4F indicates a terminal register. Math 2 diagram

Claims (1)

[Claims] (1) A plurality of terminals are connected, each containing a storage area consisting of a relatively small number of addresses, and a central processing unit (Kid) containing a shared memory commonly used by the plurality of terminals stores the memory of each terminal. The method includes specifying an address of an area or a storage area of a shared memory, wherein the shared memory includes a storage area consisting of a relatively large number of addresses corresponding to each terminal, and the shared memory includes a storage area consisting of a relatively large number of addresses,
[The address of the included storage area and the address of the storage area included in the shared memory are specified as multi-digit addresses, and in the multi-digit address, the upper digits specify an absolute address and the lower digits specify a relative address. The storage area corresponding to each terminal identification of the shared memory and the storage area included in each terminal are specified by an absolute address determined to correspond to each terminal identification. and each address included in the storage area corresponding to each terminal identification of the shared memory is different from the plurality of addresses included in the storage area corresponding to one terminal and corresponds to another terminal. The central processing unit is configured to specify a relative address that is the same as each of a plurality of addresses included in the storage area, and the central processing unit is configured to specify an absolute address corresponding to each terminal identification and a desired address among the plurality of addresses. 12) The central processing unit specifies the address of a storage area for each terminal identification or a storage area included in each terminal identification in the shared memory according to a combination of addresses. 12) The central processing unit The addressing system according to claim 1, further comprising means for inhibiting reading from said shared memory based on designating an address of a storage area.