JPS58196794A - Memory circuit for reproducing device of digital video signal - Google Patents

Abstract

PURPOSE:To make the control of a memory element easier by storing a unit of plural number of picture element data in the same address of the different memory elements to make an address signal generation circuit in common. CONSTITUTION:An address signal is supplied to RAMs M11, M12..., M21, M22..., M16 and M26... from a common address signal generation circuit 105 in a memory write controller. In the memory circuit, four RAMs Mi1-Mi4, which store picture elements of luminance signals for one frame, and two RAMs Mi5 and Mi6, which separately store each picture element of chrominance signals R-Y and B-Y for one frame are arranged in steps equivalent to the number of quantized bits (i), e.g. six steps, and also six picture elements in total, which are transmitted as the same unit by an address signal from the common circuit 105, are stored in the same address by upper 6 bits respectively.

Description

[Detailed description of the invention]

The present invention relates to a memory circuit in a digital video signal reproducing device, and the present invention relates to a memory circuit in a digital video signal reproducing device, and includes pixel data of four sample points of a digital luminance signal and pixel data of two or less sample points of a digital color difference signal. A digital video signal reproduced from a recording medium on which a component-encoded digital video signal is recorded is supplied in a signal format in which one pixel data is transmitted in a time-series manner in units of intermediate values. It is an object of the present invention to provide a memory circuit in which a common address signal generation circuit can be used and the memory elements can be easily controlled by storing 8 to 5 pixel data in different memory elements at the same address. . In recent years, video signals and A-dio signals have been converted into pulse codes mm (
)) CM) @ Digital video signals and digital audio signals obtained by digital pulse modulation are recorded on a disc-shaped recording medium (hereinafter referred to as "disc") as intermittent changes in bit strings, and the intensity or intensity of light from the disc is recorded. Systems are being actively developed to detect changes in capacitance, read and reproduce the recorded green signal. Among these, a recording method of a digital audio disc is known in which a digital video signal related to color still image information is added as additional information to a digital audio signal and recorded on the same track of the disc. Usually, a plurality of music programs are recorded on the same side of such a digital audio disc, and a digital video signal related to color still image information is recorded corresponding to each music program. When played back, the music program can be played back using a world-wide playback system.
1. On the other hand, since the 6 types of televisions are not universally available when it comes to playing back video signals, in order to make such discs playable in regions or countries where the television system is different from the television system in which the video signal was recorded, it is necessary to As for video signals, it is necessary to convert them into a signal format that complies with the television system of the region or country in which they are to be played back and displayed. In particular, since the above-mentioned digital video signal is about color still images that play a supporting role to help the listener's imagination to play the digital audio signal, the above-mentioned disc is compatible with the world's television system. It is desirable to adopt a universal system regardless of differences in television systems, and to reproduce the signal format in accordance with each television system. Among the world's television systems mentioned above, the current color signal transmission format is the NT'SC system. There are three systems, the PAL system and the SFCAM system, and each of these systems configures a color image signal from a luminance signal and two types of color difference signals, so the brightness signal and two types of color difference signals are separately processed. Adopting a component encoding method that transmits digital pulse modulation ensures compatibility between the three methods mentioned above, and also enables the use of the horn terminal with three primary color signals of RG [(), which may appear in the future. This component-encoded digital video signal is desirable because it has advantages such as good image quality when using a conventional display monitor, and the possibility of partial moving images, especially in the case of the above-mentioned digital audio disc. Regarding digital video signals applied to
CCIR) is proceeding with the standardization test, and according to it, the number of scanning lines/number of images per second is the least common multiple of the horizontal scanning frequency of 525 lines/30 frames, which are the main methods in the world, and 625 lines/25 frames. 13.5M flz, which is 6 times the frequency of 2.25MH7, is set as the sampling frequency of the brightness reduction signal, and two types of color difference signals (RY) and (B-Y) are each sampled at 6.75MHIc. A proposal has been made for component encoding, in which each component is naturalized with 8 bits/pel. In this case, the number of sampling points per scanning line (hereinafter also referred to as "line") of the luminance signal is 13.5M at the sampling frequency.
1 (obtained by subtracting Z by the horizontal scanning frequency of 15.625 kHz, resulting in 864 pieces. Also, the signal format is [171-171-It is obtained by subtracting Z by the horizontal scanning frequency of 15.625 kHz, and there is no signal deterioration due to processing or other image processing. In the case of transmitting consumer digital video signals, it is preferable to transmit according to the standards proposed in ``-'', but if the number of data is large, the image memory element will be large, and the image The problem is that the transmission time of
Assuming that the number of effective sampling points on one line is 720g for the luminance signal, 360 for the two types of color difference signals (R-Y) and (B-Y), and the number of transmission lines is 575, the number of transmission sampling points is (720+ 2x 360) x 575= 828
,000 (pieces). If the point 11a is composed of 8 bits, then 828.000x8=6,624,000 (bits). This is 2 (=65,536) bits of 64k RAM (Random Access Memory)
This is the age of information that can be accumulated using two pieces. This information is 44
．． If it is transmitted using a transmission line that can transmit 16 bits at 1kllz, it will be 6.624,000/(44,100x16) -9
, 39 (seconds) of transmission time is required. Furthermore, assuming that there are two types of memory circuits, one for reading and one for display, a total of 204 of the 64 kRAMs will be required. However, this makes the configuration of the memory circuit of the playback device complicated and expensive for consumer-use digital video signal transmission on the digital audio disc, and especially for consumer-use digital video signals that require lower prices. Undesirable for video signal reproducing devices. By the way, the frequency band of the luminance signal in the television broadcast signal is 4.2 MHz in the NTSC system, and 5 MHz or 6 MHz in the 1) Ai system and SECAM system.
However, the frequency band of the Hikari signal actually transmitted in a television receiver is 3 according to the NTS CZJ system.
Up to about MHz, and up to about 3M f-1z to 4M) IZ for PAL and SLCAM systems.
Only 1 is used. Therefore, the sampling frequency is 8M
Although it is possible to lower it to 1 liter, it is better to use h, which has a margin of 1 liter. Therefore, the sampling frequency of the luminance signal is 9, which has a 3:2 relationship with the 13.5 MHz mentioned above.
Select M fl z. Also, the color difference signal (RY), (
The sampling frequency of B-Y) is 1 of the above 9M II t
/4 frequencies, 2 and 25 MH2, respectively. Note that the number of bits in a memory circuit that stores digital video signals increases in proportion to the signal band frequency.
In addition to the standard mode digital video signals mentioned above,
Future number of scanning lines: 1125, luminance signal frequency band: 20
Considering the case where MHZ high-definition ring mode digital video signals are also recorded, a code is provided in a part of the header (described later) to identify whether it is standard mode or high-definition mode. The number of sampling points of the luminance signal per scanning line of the digital video signal in the standard mode shown below is the sampling frequency 9M)I
It is obtained by dividing z by the horizontal scanning frequency 15.625 kHz t', resulting in 516 pieces. However, in addition to the image information, this includes horizontal blanking periods such as the horizontal synchronization signal period and color burst signal period, and if we exclude the sample points during this period, there will be approximately 456 melons. can be reduced. On the other hand, the bit number of general commercially available 64k RAM is 2” (
= 65,536) hits, and if four of these are used, a number of bits of 6 4X2 = 2 per 262,144 (bits) is obtained. This number of bits is divided by the number of effective sample points of the luminance signal of underwater scanning lines (456) (which results in approximately 574.87. Therefore, among the 625 scanning lines in one frame,
The number of effective scanning lines to be transmitted as an image is - [574.8
By selecting 572 clams that are extremely close to and smaller than 7, each pixel data of the effective sample point of the luminance signal for one frame is 64k R of 4 pieces per bit.
This results in efficient accumulation in AM. In addition, the information on the two types of digital color difference signals obtained by digital pulse modulation of the two types of color difference signals (R-Y) and (B-Y) at a sampling frequency of 2.25MH7 for each person is as follows.
Since it is 1/4 of that of the digital luminance signal, the image collection data of the effective sample points of each digital color difference signal can be efficiently stored in one 64k RAM for each bit. Therefore, assuming that the pixel data of the sample point is 6 bits, the digital video signal obtained by chronologically combining the digital luminance signal and the two types of digital color difference signals is one frame of the pixel data. Minutes are 6X (4+1+1)=3
6, it can be stored in 36 64k RAMs. In addition, these 36 64k RAMs can store two 1-field digital videos Gj, which is much smaller than the 204 64k RAMs required for the memory circuit for the television studio mentioned above.
Lower prices can be achieved. In the case of component encoding, even if the pixel data of one sample point is quantized with 6 pits as described above, there is almost no problem in detecting quantization noise with standard consumer F11 equipment. confirmed experimentally. As described above, the present invention provides Ysr! for commercially available television receivers! Considering the transmission frequency band of one signal and the signal section that is actually displayed as both images in the video signal, - the number of sample points per scanning line (number of image collections) and one screen in the 41 quasi-television system. The number of effective scanning lines is reduced compared to the digital video signal applied to the television studio, and the signal format is set to 6 pixel data as one unit and transmitted in time series for each unit: 1 This invention relates to a memory circuit for storing a digital video signal reproduced from a recording medium on which an integrally encoded digital video signal is recorded.
The signal recording system for the digital video signal mentioned above will be explained. FIG. 1 shows a block diagram of an example of the essential parts of the F open signal recording system. In the figure, 1 is a video signal source such as a color television camera, Flying Sporatos, VTR, etc. 1'' from a TV synchronization signal generator 2 as necessary.
(2) A synchronizing signal is supplied, and the three primary color signals relating to the color image of -C11 recording size are taken out and supplied to the matrix circuit 3. The matrix circuit 3 generates a luminance signal Y with 625 scanning lines and a horizontal scanning frequency of 15.625K H2 and two types of color difference signals (B-Y) and (R-Y), respectively, and these AD converters 4.5 and 6 separately. On the other hand, T
The output TV synchronization signal of the V synchronization signal generator 2 is supplied to the clock generator 7.8. Memory write controllers 12 and 13 are supplied with the memory. The AD converter 4 receives the luminance signal Y from the output generator 7.
Due to the above-mentioned reason, 9 M) I
After sampling at the sampling frequency selected for Z, the signal is quantized using eight pits, converted into a digital luminance signal, and supplied to the memory 9. As mentioned above, this digital luminance signal has a sample point count (pixel count) of 456 per scanning line.
, and in the case of one frame, the number of effective scanning lines is 5.
There are 72 digital luminance signals. The memory 9 is controlled by the output write control signal of the memory write controller 12. For example, the digital brightness a4Δ is sampled for one frame, and the sampling frequency is set to 44.1kl-12 by the output readout control signal of the memory read controller 0-14.
(or 47.25kHz), read out as a quantized 8-bit digital luminance signal 1° or At) converters 5 and 6 convert color difference signals (B-Y) and (
R-Y) are supplied separately, and the human color difference signals are
After sampling at the sampling frequency selected as 2.25M112 as described above using the clock from the zero clock generator 8, quantization is performed using an 8-bit quantization number, so that the number of sample points per scanning line is 114 ( −456/4) digital color difference signals. The memories 10 and 11 write the digital color difference signals taken out from the AD converters 5 and 6 in response to a write control signal from the memory write controller 13, for example, for one lumen (effective scanning line number: 572).
The sampling frequency is 44.1k l(Z (or 4
7.25k)+2) and are read out as first and second digital color difference signals with a quantization number of 8 bits. On the other hand, a signal enters the input terminal 16 each time the color image information to be recorded changes, and is supplied to the header signal generator 17. The header signal generator 17 generates a 16-bit header signal, which is a set of signals and codes constituting a part of the header, and supplies this to the memory 1B. The memory 18 stores the header signal at a sampling frequency of 44.1 k H7 (or 47.2
5kHz2), read out with a quantization number of 16 bits. The switching circuit 15 switches the digital luminance signal from the memory 9, the first and second digital color difference signals from the memory 10.11, and the header signal from the memory 18 in a predetermined order, respectively. 3, a digital video signal having a signal format as shown in FIG. Note that a read υ control signal is output from the memory read controller 14 in synchronization with the clock signal from the gage digital recorder 19. Next, the signal format of the digital video signal □ signal 'E' will be explained in more detail. The digital video signal taken out from the switching circuit 15 is composed of a header portion of 12 words and an integrally encoded digital video signal portion of, for example, 684 words of 2) 1 minute (11 is a horizontal scanning period), which are alternately divided at different times. is synthesized sequentially, and
This is a signal in which a signal transmission end signal (hereinafter also referred to as rEOD signal j) is added to one word at the end, and when image information for one frame is transmitted, as shown in Fig. 3,
Part of the 286 headers of 111 to H286 (however, 113 to H286 are omitted) and ■1 to V286 (
However, v3 to v285 are not shown).28
6 video signal sections and 11 words of E O indicated by EOD
A total of 199,057 words of digital video signals including D signals are recorded. Therefore, the digital video signal for one frame is
In the case of 10, in which one word is recorded in one channel of 16-bit transmission in one block of the signal shown in Fig. 6, which will be described later, the signal period of this one block and the sampling frequency of the header signal are Since the reciprocal spears are selected equally, when the sampling frequency is 47.25 kHz, it is transmitted in about 4.51 seconds, and when the sampling frequency is 47.25 kHz, it is transmitted in about 4.21 seconds. That will happen. Each of the header parts 111 to N28G of the poem is the first 19 words (one word consists of 16 bits).
A fixed pattern synchronization signal is placed in , and the next word contains an image type identification code to identify whether the mode is the standard mode, all fineness mode, or a moving image using a run length code, and a scanning line number conversion code. A code for specifying whether the memory circuit into which data is to be written is a display side memory circuit or a non-display side memory circuit, and a T1 code indicating image information and other various image information are arranged.
An address signal is placed in the sixth word from the word drawer. Further, in the latter six words from the seventh word to the twelfth word, codes having the same contents as the first six words are arranged in the same arrangement. However, only the synchronization signal has a different value. In this way, sending part of the header information twice is as follows:
Since there is no data correlation between adjacent words in the header signal, it is difficult to correct it when the contents of the header signal are not transmitted. Therefore, the video signal part immediately after the header signal cannot be captured, and 2H worth of data is lost. WfA main data will be missing. (-) Part of the header information is sent twice, and even if the first half of the header signal part is not reproduced, the second half of the header signal part is used to capture pixel data. Of course, part of the header The information may be sent one time and be composed of 6 words.Next, to explain the A-mat of the video signal section V1 to V286 shown in Fig. 2, Fig. 3 shows the B1A signal. Accept an example of the signal format of part v1. In this figure, the vertical direction shows the bit arrangement, the lower side shows the MSB, the lower side shows the LSB, and the horizontal direction shows time, which is the same as in FIG. Here (・ is 286 video signal parts v1~
As mentioned above, V286 is composed of 684 words each, but in each video signal section, the pixel data of one scanning line is arranged in the upper 8 bits of the pixels of adjacent scanning lines. , the pixel data of the other scanning line are placed in the lower 8 bits and transmitted. Therefore, the signal format of the first video signal portion V1 is as shown in FIG.
The upper 8 bits of each word are the first bits located at the upper intermediate level on the screen.
The digital video signal sequence of each sample point of the scanning line (first F1 of the first field) is arranged (i.e., the first row of pixels of a plurality of pixels arranged in a matrix and forming one screen). The lower 8 bits of each word contain the digital video signal sequence (i.e., the second pixel data from a group of pixels in a row) are arranged. Also, in Figure 3, YO to Y455 (however, Y455
(not shown) is the first digital luminance signal of the first scanning line.
Indicates each arrangement position from the sample point to the 456th sample point, Y
456 to Y911 (however, Y911 is not shown) are the second
456th sample point from the first sampling point of the digital luminance signal of the scanning line
m, and each arrangement position up to Mokugyo is shown. Also (RY)0~
．． (RY) 113, (B-Y) 0 ~ (B-Y
) 113 (however, (R-Y) 113 is not shown) are the digital color difference signals (R-Y) and (B-Y) of the first scanning line.
Each arrangement position from the first sample point to the 114th sample point is marked. Furthermore, (RY) 114 to (RY) 227,
(B-Y) 114 to (F3-Y) 227 (R-Y) 227 is not shown) is the digital color difference signal (R-Y) of the second scanning line, the first sampling point of (B-Y) The arrangement positions from to the 114th sample point are shown. Therefore,
The video signal section v1 consists of a group of 2H pixel data of the first and second scanning lines, including pixel data of four sample points of the digital luminance signal and one sample point of each of the two types of digital color difference signals. A signal is transmitted repeatedly in each unit, with six WAf data consisting of data as one unit. Note that the other video signal sections v2 to v286 also correspond to the above video r'
No. 448■ It has the same signal format as 1. Rather than arranging the pixel data of the same scanning line in the same word as shown in Fig. 4, the pixel data of 62 adjacent scanning lines are arranged in the same word e as shown in Fig. 3. The reason for this is to facilitate conversion of the number of scanning lines in consideration of the case where the number of scanning lines is converted from 625 lines to 525 lines as will be described later. Also, pixels γ of two adjacent scanning lines in the same word
By simultaneously transmitting both signals and signals, it is possible to reduce the number of times of reading and writing into memory in the calculation for converting the number of scanning lines from 625 to 525. Note that the values of each word in the video signal portions V1 to V286 are as follows:
When the value of each signal in the header part 1''1 to H286 is equal to the value of the EE OD signal, it is changed to another value close to it. Next, a recording system for recording the digital video signal (1) on the digital A-A disc will be described. Here, the digital video signal is transmitted on one or two of the four transmission channels, and the digital audio signal is transmitted on the remaining channels.
- As an example, a case will be explained in which a digital video signal is transmitted through one channel. Further, for convenience of explanation, the digital audio disc will be explained by taking as an example a capacitance-change readable disc proposed earlier by the present applicant. FIG. 5 shows a block system diagram of an example of the above recording system. In the figure, the same component forces as in FIG. 1 are given the same reference numerals. 30, 31, and 32 are input terminals into which 3 channels of analog audio signals are input separately, and the 3 channels of analog audio signals include a central sound localization signal. Real image localization of the central ist and expansion of the listening range, which could not be achieved with 2-channel stereo, can be achieved. Further, 33 is a start signal input terminal;
34 is 8 of the 1st 3 channel analog audio signal
The Raku I program was the first music program that existed up until then.

[4] - This is the signal input terminal that occurs every time you switch from a music program to another music program. Here, assuming that a digital signal with a sampling frequency of 44 jk 82 and a quantization number of 16 bits is recorded in one track in time series for four channels as an information layer for one channel on the disk 40 to be described later. The above 3 channel Ana 11 Guo Dei A count has an AD converter 35
Therefore, each channel has a sampling frequency of 44.1kH.
The signal as shown in FIG. A digital video signal with a sampling frequency of 44.1 kHz and a sacrificial number of 16 bits is supplied to a signal processing circuit 37 using a signal number A-mat. Further, the control signal generating circuit 36 generates a control signal and supplies the start signal entering the input terminal 33 and the ↑co signal entering the input terminal 34 to the signal processing circuit 37, respectively. -The control signal controls the position of the pickup playback element (random access) as described later.
etc. used for such purposes. The signal processing circuit 37 receives these 16-bit input digital signals and control signals of a total of 4 channels, which are parallel data. ) are rearranged into serial data, the digital signals of each channel are divided into predetermined intervals, and they are interleaved for time-division processing. Then, a recording signal is generated by adding an error code correction signal, an error No. 6 detection signal, and a synchronization signal hit indicating the beginning of a block (frame) to the history. FIG. 6 is a diagram schematically showing an example of one block (one frame) in the recording signal generated as a result of signal processing by the signal processing circuit 37. One block is composed of 130 bits, and for example, The signals are synthesized block by block at 44.1k H2, which is the same as the conversion frequency. 5YNC is a 10-bit fixed pattern synchronization signal bit indicating the start of a block, Ch-1 to Ct+-53 are 16-bit digital audio signals of the open side 3 channels, and Ch-4 is the above-mentioned gauge digital audio signal. 1 shows each multi-Φ position of one word of a 16-bit digital video signal reproduced from the above. Furthermore, P and Q shown in FIG. 6 are signals for positive 16-bit error code, for example, P = W + ■W2■W3■W4 (
1) Q-T4 ・W1■■3 ・W2■■2 ・W2
This is a signal generated by the formula OIT-W4 (2). However, in formulas (1) and (2), W+, W2, Ws, and Ws are C11-1 to Ch
-4 16-bit digital signals (usually digital signals in different blocks), ``K'' is an auxiliary matrix of a predetermined polynomial, and ``2'' represents a 2-by-2 addition sieve for each corresponding bit. Furthermore, in FIG. 6, CRC is a 23-bit error code detection signal, and is a signal for ch-1 to Ch-, / arranged in the same block.
For example, each word of i, p, and Q is
23 obtained when dividing by the generator polynomial +x+i
This is the bit remainder, and during playback, the signal from the 11th bit to the 129th bit of the same block is removed by a 12-bit polynomial, and if the resulting remainder is zero, it is detected that there is no error. used for Furthermore, in FIG. 6, Adr is the control signal, each bit data of which is distributed, and one hit is transmitted in one block. For example, all bits of the υ control signal are transmitted by 196 blocks (that is, the control signal is It consists of 196 bits.) Therefore, when the number of rotations of the disk 40 is 900 rD-, 2940 blocks are recorded and reproduced per disk rotation, so the above 196-bit control signal is recorded and replayed 15 times during the disk rotation period. become. A digital signal of 130 bits per block shown in FIG. 6 is sequentially extracted block by block from the signal processing circuit 37 in series, and is supplied to the next stage modulation circuit 38 shown in FIG. After being modulated using a modulation method (MFM), a carrier wave of, for example, 7 MHz is frequency-modulated to produce a frequency-modulated wave signal. This frequency modulated wave signal is recorded on the disk 40 by recording using a laser beam or the like. When the disc recording method previously proposed by the present applicant is applied, the recording device 39 described above has a configuration as shown in FIG. 7. In the figure, a laser beam emitted from a laser light source 41 is transmitted to an optical modulator 42k. After the drift and noise of the laser beam are removed, the laser beam is reflected by a mirror 43 and divided into two optical paths by a mirror mirror 44. The divided laser beams are modulated in the optical modulator 45 by the output frequency modulated wave signal of the modulation circuit 38 from the input terminal -f46 and a third tracking control reference signal fp3 to be described later.
is considered to be a modulated light beam. The other divided laser beam enters the optical modulator 47 alternately from the input terminal 48 to the 1 rotation period button of the recording master 49 and generates a first or second tracking control reference signal f pl or f described later. p2
is modulated into a second modulated light beam. The first modulated light beam is reflected by reflection 1150 and its optical path is changed by cylindrical lenses 51 and 52. By passing through an information recording optical system consisting of a slit 53 and a convex lens 54, the light is shaped into a rectangular recording master disk 49-. On the other hand, the second modulated light beam is transmitted through a convex lens 55. A tracking recording optical system consisting of a slit 56 and a convex lens 57 shapes the light into a circular shape on the recording master 49, and the optical path is changed by a trailing copper mirror 58. The first and second modulated light beams, which have been shaped into a desired shape, are combined onto substantially the same optical axis 1- by a polarizing prism 59, pass through a half mirror 60, and have their optical paths changed by a prism 61. Furthermore, the first modulated light beam passes through the sleeve i-62 and the recording lens 63 onto the recording master 49 on which the photosensitive agent 1165 is formed on the glass substrate 64.
The second modulated light beam is focused in a rectangular shape as indicated by 67 and a circular shape as indicated by 67. The recording master disk 49 is disk-shaped and rotates synchronously at a constant speed, and the light reflected from the half mirror 60 is applied to a signal monitoring system 68, and the light reflected by the prism 61 is applied to a monitoring optical system 69. Added. The gap between the two modulated light beams on the recording source 1149 is measured overnight by the optical system 69, and the gap is monitored by the signal monitoring system 68, and the cylindrical lens 51 is moved in the vertical direction in the figure. The deviation is corrected by 1
Kiroku Ryo 1149 underwent a known development process and 1f-1 process to create a standby disc. The disk 40 copied by this standby disc contains the three-channel digital audio signal described above and the one-channel digital video signal in the signal format shown in FIG. 2 or 3 as shown in FIG. A spiral main track in which frequency modulated waves of signals synthesized in time series in block units on the NoA mat are recorded as intermittent bit strings, and each track center line of adjacent main tracks. Approximately in the middle between them, first and second tracking υ control reference signals f pl are arranged in a bunist-like manner and have a frequency that is within a band lower than the band of the frequency modulated wave alternately for each disk rotation period. A sub-track recorded by a bit string in which f p2 and f p2 are intermittent is formed, and further f pl,
The troughing control reference signal fp3 of logic 3- is recorded on the main track of the switching connection portion of fp2. Further, this disk 40 does not have a guide groove for tracking the reproducing needle, and has an electrode function. In this way, six pixel data consisting of pixel data of four sampling points of the digital luminance signal and pixel data of one sampling point of each of the two types of digital color difference signals are transmitted in a time-series manner as one unit. The component-encoded digital video A signal is chronologically combined with the digital audio signal and recorded on the disc 40. Furthermore, the sampling frequency of the digital luminance signal in the above-mentioned integrally encoded digital video signal is selected to be four times that of each of the two types of digital color difference signals, and the sampling frequency of each scanning line of the above-mentioned digital video signal is selected to be four times that of the two types of digital color difference signals. Inner thread 5--
The address signals indicating the memory address for each data M are synthesized in time series and are recorded on the disk 40. Next, a device for reproducing digital video signals recorded on the disc 40 will be explained. FIG. 8 shows a block system diagram of an example of a digital signal reproducing device. In the figure, a disk 40 is placed on a turntable (not shown) and rotated synchronously at 900 rpm. On the disk 40 there is a flat surface 70 and a bit 71 as shown in FIG.
A main track with a track width TW and a track pitch Tp in which C is repeated, a tracking control reference signal f in which a flat surface 70 and a bit 72 are repeated, a pH recording sub-track, a flat surface 70 and a bit 73, As mentioned above, the tracking 11 reference signal f p2 recording sub-track is formed repeatedly on the surface of the disc 40 on the bottom surface 74 of the playback button 74.
b is made to slide. As shown in FIG. 8, the reproduction button 74 is fixed to one end of a cantilever 75, and a permanent magnet 76 is fixed to the base side of the other end of the cantilever 75. cantilever 75
The part to which the permanent magnet 76 is fixed is a tracking coil 77 and a jitter correction coil 78 fixed to the playback device.
is surrounded by. The tracking coil 77 generates a magnetic field in a direction perpendicular to the magnetic field direction of the permanent magnet 76, and depending on the polarity of the tracking error signal from the tracking servo circuit 79, the cantilever 75) is moved in one direction to increase the track width. And, Displace it with a displacement fist according to its size. The resonant frequency changes in response to the change in the capacitance age formed between the disk 40 and the electrode 74a shown in FIG. 16 circuits that apply a constant frequency to this resonant circuit; a circuit that amplitude-detects a high-frequency signal whose amplitude changes according to changes in electrostatic capacity from the resonant circuit; A high-frequency reproduction signal extracted from a pickup circuit 80 consisting of a circuit for pre-amplifying a high-frequency signal (reproduction signal) is supplied to an M demodulation circuit 81, where the main information signal of one track (in this case, a digital After the audio signal and the digital video signal synthesized in time series are demodulated, a portion is branched and supplied to a tracking servo circuit 79. The tracking servo circuit 79 detects the first signal from the reproduced signal.
to third tracking control reference signals fp1 to fp
3 by selecting the frequency and extracting both reference signals t pi,
The envelope detection output of r p2 is differentially amplified to obtain IJ1-
A rattling error signal is output to the tracking coil 77. However, f pl, f for the main track
Since the recording positional relationship of p2 is switched every rotation period of the disk 40, the tracking polarity is switched every one rotation period of the disk 40 by the switching pulse generated based on the detection output of the tracking control reference signal f p3. . Note that when a kick instruction signal is received at the input terminal 82, the tracking servo circuit 79 drives the tracking coil 77 so as to forcibly move the playback button 74 in the track width direction by one track pitch or more. do. On the other hand, the 1ml digital signal taken out from the FM1M tone circuit 81 is applied to the digital
After being decoded into a time-series composite signal with the signal format shown in Figure 6, the beginning of the signal block is detected based on the synchronization signal bit 5YNC, and the i-column signal is converted into a parallel signal. Detection is performed. Only when an error is detected, the error signal is corrected and restored using the error rI month correction code 1] and Q. In this way, three of the 16-bit four-channel digital signals are restored as needed (restored to be error-free and the signal arrangement is restored to its original order before interleaving). The 16-bit digital audio signal for each channel is converted into an analog audio signal by the DA converter in the decoder 83, and then sent to the output terminal 8.
4.85 and 86, respectively. In addition, the pickup control signal is sent to a predetermined circuit (
(not shown). On the other hand, the digital video signal having the signal format shown in FIG. 2 (and further shown in FIG. 3) that is reproduced in chronological order in the fourth channel is supplied to the scanning line number conversion circuit 87 shown in FIG. The number of scanning lines is converted from 625 lines to 525 lines. FIG. 10 is a diagram schematically showing how the number of scanning lines is converted. In the figure, YO is the first digital luminance signal of the first scanning line of the 625 scanning line system as shown in Fig. 3.
In the pixel data of the sampling point, Y456 similarly indicates the pixel data of the W41 sampling point of the digital luminance signal of the second scanning line. As can be seen from FIG. 3, the above-mentioned pixels f-Y YO and Y456 are transmitted at the beginning of the video signal section V1, but the data obtained by multiplying this pixel data YO by 3/4 (this is the data obtained by multiplying YO by 3/4). The pixel data Y456 is created by adding the data shifted by 1 bit LSB in the direction, the data shifted YO by 2 bits LSB in the h direction, and the pixel data Y456.
The pixel data YO' of the 141st point of the first scanning line of the digital luminance signal of the 525 scanning line system is generated by mixing the 1/4 times the data shifted by 2 bits in the S and B directions. Data 1/2 times the pixel data Y456 is stored in the auxiliary memory (1 line memory) 103. Hereafter, in the same manner as above, the first
The data obtained by multiplying the pixel data of each sample point of the scanning line by 3/4 and the data obtained by multiplying the pixel data of each sample point of the second scanning line by 1/4 are in the same word. Certain sample points are mixed together and converted into pixel data of the first scanning line of the 525 scanning line system. Subsequently, the pixel data of each sample point of the third scanning line of the 625 scanning line system of the video signal part V2 is multiplied by 1/2 (
(obtained by shifting one bit in the LSB direction) and then mixed with the pixel data read from the auxiliary memory -03 of the same sample point to become the pixel data of the second scanning line of the 525 scanning line system. converted. Y912 is the pixel data of the first sampling point of the digital luminance signal of the third scanning line in the 625 scanning line system, and Y456' is the first sampling point of the digital luminance signal of the second scanning line in the 525 scanning line system.
The art collection data for each sample point is shown. Also Y1388. Y
1824. Y2280 is the pixel data of the digital luminance signal of 625 scanning lines, and Y1368 is the pixel data of the 4th
The first sample point of the scan line, Y 1824 is the first sample point of the fifth scan line.
Sample point Y2280 indicates pixel data of the first sample point of the sixth scanning line. Historically Y 912', Y1368'
, Y1824' is the pixel data of the digital luminance signal of 525 scanning lines, Y912' is the first sample point of the third scanning line, and Y1368' is the first sample point of the fourth scanning line.
sample point, and Y1824' indicates pixel data of the first sample point of the fifth scanning line. As shown in Figure 10, the number of scanning lines such as Y912 is 62.
The pixel data of each sample point on the third scanning line of the 5-line method is halved.
The multiplied data is mixed with the data obtained by multiplying the pixel data of each sample point of the fourth scanning line such as YI368 by 1/2, respectively.
While the pixel data of each sample point of the third scanning line of the 525 scanning line system such as 912' is obtained, the data on the rear right is stored in the auxiliary memory (one line memory) 104. Similarly, the pixel data of each sample point of the fifth scanning line such as Y1824 is multiplied by 3/4, and then mixed with data obtained by multiplying the pixel data of the same sample point read from the auxiliary memory 104 by 1/2. Then, pixel data of the fourth scanning line of 525 scanning lines such as Y 1368' is obtained, and further pixel data of Y 228' is obtained.
The pixel data of the 6th scanning line such as 0 is the same as the number of scanning lines 52
This is the pixel data of the fifth scanning line of the five-line system. Thereafter, the same operation as above is repeated, and the pixel data of the 6 scanning lines of the 625 scanning line system is mixed at a predetermined mixing ratio, and the pixel data of the 5 scanning lines of the 525 scanning line system is mixed. will be converted into. Here, as is clear from the explanation in E, the auxiliary memory 103° 104 used for 8 and sieving in the scanning line number conversion is as follows.
A common one-line memory is used in turn. On the other hand, as mentioned above, the number of sample points (l
ii number of raw data) is - number of sample points per horizontal scanning line 45
6 and the number of effective scanning lines is 572.
832 bits, whereas the number of bits of four 64k RAMs is 262,144 (= 2" x 4) bits, so there is a margin of 1312 bits. In other words, four 64k RAMs have a margin of 1312 bits. , 2] (Since there is an extra memory capacity capable of storing 1 bit for each pixel i of the sample point of the digital luminance signal on the distribution, this can be used as the above-mentioned auxiliary memories 103 and 104. Note that reading and writing to the auxiliary memories 103 and 104 are performed within the horizontal blanking period of the standard television system (NTSC system here) color video signal taken out from the output terminal 102. Then, the scanning line number conversion circuit 87 converts the number of scanning lines to 6.
This circuit converts pixel data of the 25-line system into pixel data of the 525-scanning line system, and since the pixel data is transmitted in the format shown in FIG. 3, the conversion operation is easy. This scanning line number conversion circuit 87 is a circuit necessary only for a playback device that reproduces and outputs an all-log color video signal conforming to the NTSC system as shown in FIG. This circuit is unnecessary for a playback device that plays back and outputs an analog color video signal conforming to the SECAM or SECAM systems. However, depending on the playback device, a changeover switch is provided to change the input/output of the scanning line number conversion circuit 87, and the circuit 87 is switched to be activated or deactivated depending on the number of scanning lines of the television system to be reproduced. Good too. The output pixel data of the scanning line number conversion circuit 87 is transferred to a memory 94 or 95, which is a main part of the circuit of the present invention, by a switch circuit 88.
supplied to Further, the digital video signals sequentially and time-sequentially extracted from the decoder 83 in the signal format shown in FIG.
The signal is also supplied to a synchronization signal detection circuit 89, a header signal detection circuit 91, and a memory write controller 92, respectively. The synchronization signal detection circuit 89 detects the synchronization signal in the header signal and supplies the detection signal to the 111 circuit 90. Further, the header signal detection circuit 91 selectively reproduces each "-" code and address signal except for the synchronization signal in the header signal and supplies it to the control circuit 90. The control circuit 90 is supplied with the synchronization signal detection signal and each code detection signal of the header signal, and also detects the video type intended by the playback device user (this can be determined in advance by recording a plurality of chips on the disc 40) by operating an external switch or the like. - can be arbitrarily selected when different images are recorded) are supplied from the input terminal 93, these input signals are discriminated and decoded, and the scanning line number conversion circuit 87 and the switch circuit 8
8. Controls the memory write controller 92, switching circuit 97, etc. The memory write controller 92 (memory 94 or 9
The pixel data in the digital video signal supplied to 5 is polished to a specified address, but the header signal and EOD
The signal is controlled so that it is not written. The switch circuit 88 is switched to terminal a or b by a control signal from the control circuit 90 based on the memory write designation code in the header signal, and the digital video is switched to the terminal a or b designated by the memory write designation code. supply the signal. The memories 94 and 95 contain reproduced pixel data for one frame written based on read control signals from the memory read controller and synchronization signal generation circuit 96, or two fields in total written for each field. The reproduced pixel data is read out simultaneously, and jitter associated with reproduction is also corrected. Here, the digital color difference signals read out from the memories 94 and 95 are read out at a sampling frequency of 9 MHz and a quantization number of 8 bits, and the first and second digital color difference signals are respectively read out at a sampling frequency of 2.25 MH2 and a quantization number of 8 bits. 8 bit'
C is read out and supplied to the switching circuit 97, respectively. Next, the configuration and operation of the memories 94 and 95 will be explained in more detail. FIG. 11 shows a memory 94, 95 and a memory write controller [l-ra 9] which are an embodiment of the circuit of the present invention.
2 shows a partial block system diagram. A part (auxiliary circuit) of the scanning line number conversion circuit 87 can also be included in this. In the same figure, Mll. M2S,...,M63. ..., M16.・・・
-2M66 is a RAM of about 64 bits, and these 36 RAMs in total are supplied with 7 address signals from a common address signal generation circuit 105 in the memory write controller 92. When the memories 94 and 95 are frame memories, 12 sets of 36 RAMM11 to M66 are required, but when they are field memories, 111 are sufficient. Although not shown in the drawings, there is a first memory which stores a group of pixel data transmitted in the upper 8 bits of each word of the video signal portion of the signal format as shown in FIG. A buffer memory and a second buffer memory are provided for storing a group of pixel data transmitted in the lower 8 bits in 6 words of pixel data each. Also S1. S2. S 3. . . . , 86 is a 6-contact changeover switch (actually an electrically operated analog switch) to which pixel data from the first and second buffer memories is supplied and which selectively outputs the pixel data. 1
is RAM Mll, M12. . . . The MSB of pixel data is supplied to one of the RAMs at the back of 1M16. Similarly, among the changeover switches S2 to S6, Si (where i = 2 to 6) is set to RAM Mij (where j = 1 to 6).
) The high-order i-th bit of pixel data is supplied to one of the RAMs at the back of ). Therefore, in the metering circuit shown in FIG. ), two RAMMi5. Mi6 is arranged in i stages equal to the number of crystallized bits to be reproduced (1) (in this case, i = 6), and a total of six Uniform data is such that the first 6 bits of each pixel data are stored at the same address (therefore, the pixel data of the luminance signal per field is stored from two 64K RAMs). The pixel data of the two types of color difference signals per field are arranged in six stages of memory elements each consisting of one 64 kRAM.) Therefore, the lower two hits of the 8-bit pixel data are discarded, but the effect on the reproduced image is not a problem. Of course, all 8 bits of pixel data may be stored by adding 12 64k RAMs to the memory, but as a consumer digital video signal reproducing device, the configuration shown in Figure 11 is sufficient. Using a circuit is more advantageous in terms of cost. Next, to explain the operation of the memory circuit mentioned in item 1, first,
Address signal generation circuit 105 that generates an address signal with an address number matching the address information in the header signal.
A 16-bit 7 address signal whose value in hexadecimal notation is [0OO0,1 is outputted to RAMM11-M66, respectively. On the other hand, selector switches 31.1 to 31.1 to S6 are used to select RAM Mll, M21. M31. Mn2, M
51 and MB2 are supplied with the I-order 6 bits of the pixel data Y0 shown in FIG. As a result, the data of MSF3 of YO is transferred to address [0OOOJ of RAM Mll.
The data of the second most significant bit of YO is stored at address 1-0000J. M31. Mn2゜M51
and MB2's 7 dress [YO in the same way for 0OOOJ
The data of the 1st, 3rd, 4th, 5th, and 6th bits are stored, respectively. Next, leave the address signal as it is and switch 81~
S6 is switched, and the upper 6 bits of pixel data Y1 are R.
AMM12. M22. M32. M42. M52
and M62, one bit at a time, and stored at the address [0OOOJ. Thereafter, the values of the address signals are left as they are in the same manner as above, and the changeover switches 81 to 81 . S6 is switched sequentially, and RAMM1
6. M26. M36. M2S, MSB and M6
When the data of the F-6 pit of pixel data (B-Y) 0 is stored bit by bit at the address l[0OOOJ in hexadecimal notation of 6, the next address signal generator 1-circuit 105
4 address signals indicating the address of hexadecimal value [0001J are output from RAMM11 to RAMM11 in the same way as above.
At address [0OO1,l of M66, art book data Y 4
．． Y5. Y6. Y7. (RY)
1° and (B-Y)1 are stored one bit at a time. From then on, the same operation as above is repeated, the address increases by 1, and the pixel data group of the first scanning line becomes RAMMI.
When the data is stored in I to M66, an address signal of 00721 in hexadecimal format is generated from the address @ month generation circuit 105, and the second temperature signal shown in FIG. 3 is generated through the changeover switches 81 to S6. The upper 6 bits of pixel data Y456 of the first sampling point of the scanning line are stored in RAM Mll, M21.
M31. Mn2. One bit is applied to M51 and MB2 and stored. After that, the switching switches fs 1 to S6 are switched while leaving the value of the address signal as it is.
The first 6 bits of pixel data Y451 are stored in RAMM12. M
22. ...2M62 is applied. This allows R.A.
Pixel data Y45 is at address 10072J of MM12.
7 MSF3 data is written into RAMM22. M
32. ...1M62 address [0072J contains the 2nd bit, 3rd bit, . . . , 6th bit of Y457, respectively.
The bit-th data is written. 1. Similarly to the above, the address is incremented by -If4j1f, and writing of the pixel data group of the second scanning line is completed. The pixel data of the first 6 words of the third scanning line is the hexadecimal value "00E
6 from the beginning of the fourth scanning line.
The pixel data of the word is written into an address with the value "0156" in hexadecimal notation. In this way, one frame or one field's worth of pixel data is written into the memories M11 to M66 for two fields, but of the pixel data transmitted in six continuous pixels, the pixel data of the same scanning line is Six pixel data (consisting of four pixel data of digital luminance signal and one pixel data of two types of digital color difference signals) are stored in 36 RAMMs.
11 to M66 at the same address. Here, since the memory circuit shown in FIG. 11 is driven by the same address signal, it is necessary to perform one writing and one reading in a time-division manner. Specifically, as shown in FIG. 8, the readout control signal from the sized memory read controller and synchronization signal generation circuit 96 determines the video period (approximately 51 use
c) IfrRAMMll ~ 1y166 is read, and horizontal blanking period (approximately 13 μsec)
One write is performed within the memory, and the reading and writing of the auxiliary memory for converting the number of scanning lines is performed. Also RAM
By reading M11 to M66, the aforementioned six pixel data at the same address are read out simultaneously. Referring back to FIG. 8, pixel data to be read from memory 1-h of the memories 94 and 95 configured as shown in FIG. Selected output based on the code,
The pixel data of the digital luminance signal is supplied to the DA converter 98, and the pixel data of the two types of digital color difference signals are supplied to the DA converter 98.
transducers 99 and 100, respectively. Here, the switching circuit 97 selects the switching Ij supplied when the EOD signal is detected.
By the lJIIl signal, the memories 94 and 95 are switched from the memory that was selectively outputting the readout output to selectively outputting the readout output of the other memory.1') The analog 0g brightness signal, the color difference signals (B-Y) and (R-Y) extracted from the DA converters 99 and 100, and the memory read control [l
- horizontal taken out from the horizontal and synchronizing signal generation circuit 96;
Each vertical synchronization signal and h color burst signal are respectively supplied to an encoder 101 and generated into a color video signal compliant with the NTSC system, and then outputted from a playback output terminal 102 to a color television receiver for monitoring (not shown). Here, the audio signal is output from the output terminals 84, 85, 86 and reproduced as light and used for music listening by the listener F.
The image is displayed as a color still image or partial moving image as supplementary information. As can be seen from the explanation in FIG. 11, if each pixel data is composed of n pits, 64k RAM
Itememory for the number of (4-+-1+1)xn is 94.9
5, but if it is acceptable to further reduce the resolution of the color signal, the color difference signal (R-Y) and ([3-Y) can be taken into the memory 94°95 as line-sequential.
4-)-1) Xrl, that is, 3 when n is 6 bits
94.95 can be configured with 0 pieces of 64k RAM. On the other hand, if the resolution of color signals is important, 64kRA
The memory is configured using M in the number of (4+2+2)xn. Also, 256kRAM is 262,144 (= 2
) bit, it is preferable because one RAM can store one bit of signal per frame. In this case, R.A.
It depends on the reading speed of M, but if the reading speed is slow, it is configured as a 2-frame memory circuit, and two F<
There is also a method of using AM in time division. Furthermore, since the digital color difference signal is read out from the memory 94.95 at a readout speed 1/4 of the digital luminance signal, one RA
M can be used time-divisionally for two types of digital color difference signals. Note that in the case described in -, the case where a digital video signal with 625 scanning lines is stored on the disk 40 and played back has been explained; Even when recording, -
Is the product of the number of sample points per scanning line and the number of right-moving scanning lines 27? Select a value slightly smaller than that and record it. In addition, in the explanation below-1, image transmission in the standard mode was explained, but in the case of high-definition, high-quality image transmission, or when transmitting a moving image using a run-length code, the header signal provided in the header signal The values of both image type identification codes are discriminated and reproduced, and the scanning line number conversion circuit 87 and the memory write controller 92 are activated as necessary according to the output signal of the control circuit 90.
The format for importing into the memory 94 and 95 is selected by controlling. Note that the unit of division of the digital video signal recorded on the disc 40 is not limited to the above embodiments.
The point is that when the display screen is displaying a negative image and gradually switching to another image, it is sufficient that the human eye does not perceive that the color and brightness are being switched separately (for example, the scanning line (It is also possible to transmit the data by adding a part of the header to it in groups of up to 10 pieces of inner element data.) Furthermore, in the above embodiment, the pixel data of the divided signal was explained as pixel data of two adjacent scanning lines (that is, pixel data of a group of pixels in two horizontal rows), but in the vertical direction There may be pixel data C of adjacent pixel groups arranged in 2 to 10 columns. Furthermore, the digital video signal may be transmitted for one frame or one field through a total of two channels, Ch-3 and Ch-4 shown in Fig. 6, and in this case, the reproduced The digital BJA@ signals are reproduced in chronological order and transmitted over a single transmission line. Furthermore, in the above explanation, the case where the application is applied to the disk recording method and playback device proposed earlier by the present applicant was explained, but the invention is not limited to this, and the present invention is not limited to this, and the present invention is not limited to this, and the present invention is not limited to this. The present invention can also be applied to disks in which the green signal is read by a light beam.Furthermore, if the television receiver has three primary color signal input terminals of R, G, and B, A matrix circuit is used in place of the encoder 101, and this converts the Kiyoyu No. Y and color difference signals (R-Y) and (B-Y) into the three primary colors No. 18 R, G, and B and sends them to the above input terminals. By supplying each separately, it is possible to display extremely high quality still images on the television receiver.Furthermore, the color difference signals recorded on the disk 40 are (G
It goes without saying that a combination of -Y) and (RY) or (B-Y) may be used, and furthermore, an I signal, a Q signal, or three primary color signals may be used. [As described above, the memory circuit in the digital video signal reproducing apparatus according to the present invention has N stages (
However, N is a natural number), and N or smaller stages of color code met elements having a capacity of about 2r bits per field (K is 16.15 or 14) are arranged. 1. The luminance signal memory element and the chrominance signal memory element are connected to a common address signal generation circuit, and the pixel data of the four pixel data of the luminance signal reproduced from the recording medium and the two types of color difference signals (color signal ) A component encoded digital video signal transmitted in units of 8 to 5 pieces of data consisting of 2 or less sample points each is passed through the input selector switch to the above-mentioned brightness. The voltage is selectively applied to the boundary signal memory element and the color signal memory element, respectively, and each 1st N pit of the image collection data of four sample points in the same unit of the luminance signal is applied to the memory element for the II degree signal of N stages. In addition to storing data in addresses with the same number, each of the 1st N bits or more of the pixel data of 4 to 1 sample points of the color difference signal (color signal) in the same unit as above is stored in the N stage section 1. Since the memory element for the color difference signal is configured to store data in the seven addresses having the same number as above, it is possible to use a general commercially available 64K memory element as the memory element.
By using a RAM, it is possible to efficiently store the digital encoded digital video code, and since the address signal generation circuit can be shared, the memory elements can be easily controlled and the circuit configuration can be simplified. It can be constructed at a low cost, and furthermore, the above component-encoded digital video signal has address information indicating a memory address for each pixel data group of each scanning line synthesized in chronological order, and the previous two addresses The signal generation circuit generates an address signal that increases the address for each unit of 8 to 5 prefixed pixel data based on the address information mentioned above, so it has features such as easy control of address t11. It is something.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram showing an example of the main part of a recording system for digital video signals to be stored in the circuit of the present invention;
The figure shows an example of the signal format of a digital video signal, FIG. 3 shows an example of the signal format of the video signal section in FIG. 2, and FIG. 4 shows another example of the signal format of the video signal section. Figure 5 shows an example of a recording system for recording a digital video signal together with one digital A-dio signal.

[-]Tsuk system diagram, Fig. 6 is a diagram showing an example of the 1-block signal format proposed earlier by the present applicant, and Fig. 7 is a diagram showing an example of the 1-block signal format proposed earlier by the present applicant. FIG. 8 is a system diagram showing an example of a recording device in the figure, FIG. 8 is a block system diagram showing an example of a digital signal reproducing device, and FIG. FIG. 10 is a diagram for explaining an example of the conversion operation of the scanning line number conversion circuit; FIG. 11 is a block diagram showing an embodiment of the circuit of the present invention; FIG. It is. 1... Video signal source, 2... TV synchronization signal generator,
3... Matrix circuit, 4.5.6.35... AD
Converter, 9-11.18...Memory, 15.97...
・Switching circuit, 17...Header signal generator, 19...
・Digital Reni]-da, 30 to 32... Analog O/GOD A signal input terminal, 36... Control signal generation circuit,
37... Im month processing four paths, 39... Recording device, 40
...Disc-shaped recording medium (disc), 41...Laser light source, 42.45.47...Light modulator, 74...
Regeneration needle, 74a... Electrode, 76... Permanent magnet, 79
...Tracking servo circuit, 80...Pickup circuit, 83...・1? -1-da, 84~
86...Analog audio signal output end, 87.
...Scanning line number conversion circuit, 88...Switch circuit, 90
...υrm circuit, 91...header signal detection circuit,
92...me[rewrite controller, 94.95...
・Memo for digital video signal storage■c96...Metric read. Controller and synchronization signal generation '1 time M, 98
to 100... OA converter, converter, 101... encoder, 102... analog video signal output terminal, 103
゜104...Auxiliary memory, 105...Address signal generation circuit, MU-M66...64k RAM forming the main part of the circuit of the present invention, 81-S6...Selector switch. 59 Figure 4 16 Figure 6 jYzzao Y+'824 Continuation of Figure S, page 1 0 Inventor Yoshiaki Amano Inside Victor Company of Japan, 3-12 Moriyamachi, Kanayō-ku, Yokohama 0 Inventor Koji Tanaka City of Yokohama Inventor: Fujio Suzuki, 3-12 Moriyamachi, Kanayo-ku, Japan Victor Co., Ltd., 3-12 Moriyamachi, Kanayo-ku, Yokohama Inventor: Mitsuo Kubo, 3-12 Moriyamachi, Kanayo-ku, Yokohama Chome 12, Japan Victor Co., Ltd. 0 Inventor: Kikuchi Hikaru, 3-12 Moriyamachi, Kanayō-ku, Yokohama City, Japan Victor Co., Ltd., 1st floor? ttS 1E rate 1.1il'l table Kosho lit ri71IIjlmu Htl No. 112353 No. 2
Buyamei's 'r' 1st name r'(shitarubij" A Buddha name reproduction

[) Rume Seven Circuit: 1. ? Fortune-telling for lLI 1 “I Engineering’1 Applicant +1 1”f+ 〒221 3 Moriyacho, Kanayō Ward, Yokohama City, Kanagawa Prefecture] 121 Land? 1st name (432) E1
Hon Victor Co., Ltd. 1 CEO Ishi Odori -
Department/1st generation Zhou 1 person 11 Ogi 〒102 Tokyo F 11th 51st Kojimachi 7j1;] 11i J 6 of 11th Kojimachi, Tokyo 102, Detailed explanation of the invention in the specification to be amended. 7. Contents of the amendment (1) In the specification, "of frequency" on page 6, line 13 will be deleted. ■ In the same text, page 42, line 8, ``Ireru'' is supplemented with ``Sareru''. ■ Similarly, in the 42nd page, from line 14 to line 1711, [pixel data group...memory] is changed to [first buffer memory that stores one pixel data group, and the lower 8 bits are transmitted. 111 minutes of pixel data group is stored.'' (4) In the same text, No. 44, line 13, 1, ``To explain,'' is amended as follows. 1.Explain. However, for convenience of explanation, the digital video signal A for direct reproduction is supplied to the memory 94.95 without passing through the scanning line number conversion circuit 87.
Anode compliant with S E CAM method
A case of a playback device that re-outputs a color video signal will be explained below. 1 (h) till, page 44, line 18,
'' and ``Switch...1 Insert 1 from the 1st batsuno〆memory between [1].
6 rows of [Mn+, Ma+, -, and M66 J
f F M +3”・M 65゜tvl To +4・M
M15~M and M16~M66 [and correction 64
'65 →ru. (7) Same, page 45, No. 16 (jno〒 line 18, “Pixel J
−・Evening... When the memorization is completed, ] is corrected as follows. 1 pixel data Y2, Y3, <RY)o, (B-Y)
The data of the 1st 6 bits of o is memorized bit by bit [,
The first divided self-system data group of the first scanning line ((゛kode=i
, 14 luminance pixel data and two chrominance pixel data (1′-ta) are now outdated. ” d Same, No. 46, line 6, “When it is finished being remembered” (!I
AL! It ends being remembered. ] Corrected. (!J) till, 46th member, line 10 to line 11, between “...6jit・ga1 and r RAM...” Insert 1 1° (10) Same as page 46, line 14, [pixel f-1] is corrected to [pixel data from the second square mark, 1]. (11) "Third scanning line... is occupied." on page 47, lines 3 to 7 is corrected as follows. [Video signal sections V3, VJ, V5, etc. are read in the same way, and the last pixel data group of the 571st and 572nd scanning lines (1285th and 286th scanning lines in the case of field feed) is RAM address r F
The data is stored in E45J and rFEB7J (r7EE9J and r7F513J in the case of field feed), and the loading of one frame (or one field) is completed. ” (12) Same, 48th Tei, 4th line to 8th line [is done, ... is read out. ' shall be corrected as follows. 1- It is done. Also, when reading RAM M1 to M66, six pixel data marked with 1 at the same address are read out at the same 0.1, and the address is foooo
It increases by 1 from l. In order to output the ab0gjit'Afa number based on the NlSC method from the meat signal, the fintervi 1o signal from the reader 83 is sent to the scanning line by the circuit 87. 1 when writing to mailbox 94 or 95 after converting the number
The write operation to the memory circuit is based on the number of data 5), 6
Since the explanation is the same as above except that it is doubled, the explanation will be omitted here. (13) Same, page 49, line 16 [pixel data...
(14) Similarly, correct [memory] on page 50, line 19 to 1 record 1.

Claims (1)

[Claims] (1) A recording medium on which a component-encoded digital video signal obtained by separately digital pulse modulating a luminance signal and two types of color difference signals (chrominance signals) of image information to be recorded is recorded in time series. In the memory circuit of a digital video signal reproducing device that plays back the digital video signal and stores and reads out the reproduced digital video signal for one screen, N stages (however, , N is a natural number) and 23 bits per field (K is 16.1
Color signal memory elements having a capacity of about 5 or 14) are arranged in N stages or smaller stages, and the luminance signal memory elements and the color signal memory elements are connected to a common address signal generation circuit, respectively. , a total of 8 to 5 art book data consisting of pixel data of four sample points of the luminance signal reproduced from the recording medium and pixel data of two or less sample points of each of two types of color difference signals (color signals). The component-encoded digital video signal transmitted in each unit is selectively applied to the upper luminance signal memory element and the color signal memory element through the input switch, and the same medium level of the luminance signal is applied. The upper N bits of the pixel data of the four sampling points are stored in the addresses of the same number of the luminance signal memory elements of the N stages, and each of the color difference signals (chrominance signals) in the same middle range as above is stored. Each of the upper N bits or more bits of the pixel data of two or less sampling points is N
1. A memory circuit in a digital video signal reproducing apparatus, characterized in that the memory circuit is configured to store information at addresses having the same number as the above in memory elements for color difference signals below the stage. ■ The component-encoded digital video signal is
Address information indicating a memory address is synthesized in time series for each pixel data group of each scanning line, and the address signal generation circuit generates an address for each unit of six pixel data based on the address information. 2. A main circuit in a digital video signal reproducing apparatus according to claim 1, wherein the main circuit generates an address signal that increases the address signal.