JPS58195385A - Digital video signal recording system - Google Patents

Abstract

PURPOSE:To reduce the deterioration in the vertical resolution, by mixing the digital video signals of the 1st and the 2nd fields obtained from analog video signals for one frame's share through digital pulse modulation, producing the digital video signal of the 3rd field and recording the signals on a recording medium. CONSTITUTION:To suppress the deterioration in the vertical resolution of a field picture taking the reproduction of a digital signal reproducer having a field memory only and the field picture reproduction with the fast feed reproduction into consideration, the digital video signal of one field is attenuated and mixed to the digital video signal of the other field as shown in Equations, and the result is recorded as the digital video signal of the other field, where L2n (n is a natural number) in Equations is the picture element data of the 2n-th scanning line from the upper part of the screen, the scanning lines of an odd number order represent the scanning lines of the 1st field and the scanning lines of an even number order represent the scanning lines of the 2nd field. The mixing processing as shown in Equation is done in memories 9, 10 and 11, the picture element data from the main memory of the scanning lines to be mixed in an auxiliary memory is stored, read out and operated sequentially, and stored again in the main memory, allowing to attain the mixing processing.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital video signal recording method, in which a digital video signal obtained by digital pulse modulation of an analog video signal for one frame is converted into a digital video signal of one field and a digital video signal of the other field. A third field digital video signal is generated by mixing the digital video signals of the above at a predetermined mixing ratio, and this is recorded on a recording medium as the digital video signal of the one field together with the digital video signal of the other field, This recording medium is a digital video signal that enables high-quality image reproduction in both inexpensive playback devices that have only field memory as a memory circuit for storing playback digital video signals in the playback device, and high-end playback devices that have frame memory. The purpose is to provide a recording method.

In recent years, pulse code modulation (
Digital video signals and digital audio signals obtained by digital pulse modulation such as PCM) are recorded as changes in intermittent bit strings on a disc-shaped recording medium (hereinafter referred to as "disk"), and the changes in the intensity of light from the disc or static Systems are being actively developed to read and reproduce recorded signals by detecting changes in capacitance. Among these, a recording method for a digital audio disc is known in which a digital video signal related to color still image information is added as additional information to a digital audio signal and recorded on the same track on the disc. Usually, a plurality of music programs are recorded on the same side of such a digital audio disc, and a digital video signal related to color still image information is recorded corresponding to each music program, but when this disc is played back, Music programs can be played using a playback system that is common throughout the financial world.

On the other hand, since the television system for playing back video signals is not universally accepted worldwide, in order to be able to play back in regions or countries where the television system differs from the television system for the video signal recorded on such a disc, it is necessary to As for the signal, it is necessary to convert it into a signal format that complies with the television system of the region or country in which it is to be reproduced and displayed. In particular, since the above-mentioned digital video signal concerns color still images that play an auxiliary role to aid the imagination of the listener who listens to the playback of the digital audio signal, the above-mentioned disc is compatible with the differences in television systems around the world. It is desirable to use a universal system regardless of the TV system and reproduce the signal format in accordance with each television system.

Among the world's television systems mentioned above, the current color signal transmission formats are NTSC, PAL, and S
There are three ECAM systems, and in all of these systems, the color image signal is composed of a luminance signal and two types of color difference signals. Adopting a component encoding method that modulates and transmits the data allows for easy compatibility between the three methods mentioned above, and also allows the use of a display monitor with RGB three primary color signal input terminals that may appear in the future. It is desirable because it has advantages such as good image quality when used with digital audio discs, and especially the possibility of partial moving images in the case of digital audio discs.

Among such component-encoded digital video signals, digital video signals particularly applicable to television studios are currently being referred to by the International Wireless Telecommunications Advisory Committee (
CCIR) is currently considering unifying standards, and according to the standardization, the number of scanning lines/number of images per second is 22, which is the least common multiple of the horizontal scanning frequency of 525 lines/30 frames, which are the world's main methods, and 625 lines/25 frames. 1, which is 6 times the frequency of .5MHz
The sampling frequency of the luminance signal is 3.5 MHz, and the two types of color difference signals (R-Y) and (B-Y) are each 6.75 MHz,
A proposal has been made for component coding in which each component is sampled at 8 bits/pel and quantized at 8 bits/pel. In this case, the number of sampling points per scanning line (hereinafter also referred to as "line") of the luminance signal is obtained by dividing the sampling frequency of 13.5 MHz by the horizontal scanning frequency of 15.825 KHz, which is 86
There will be 4 pieces. Further, as a signal format, a format has been proposed that does not cause signal deterioration even when subjected to chroma key processing or other high-quality processing.

In the case of transmitting digital video signals for consumer use, it is preferable to transmit according to the standards proposed above, but when there is a large amount of data, the problem is that the image memory element becomes large and the image transmission time becomes long. Become. For example, 1
The number of effective sample points on the line is 720 for the luminance signal and 360 for each of the two types of color difference signals (RY) and (B-Y).
If the number of transmission lines is 575, the number of transmission sample points is (720+2×360)×575=828,000. If one sample point is composed of 8 bits, then 828,000×8=6,624,0OO (bits). This is 216 (=55,536) bit S4k
This is the amount of information that can be stored using 102 RAMs (random access memories). This amount of information is 44.1kHz
If the transmission is performed using a transmission path that can transmit 16 bits at z, the transmission time will be required. Furthermore, assuming that the memory circuit has two types, one for writing and one for display, the 64kRA
A total of 204 M is required. However, this makes the configuration of the memory circuit of the playback device complicated and expensive for consumer-use digital video signal transmission on the digital audio disc, and especially for consumer-use digital video signals that require lower prices. Undesirable for signal regenerators.

Therefore, the present invention can perform high-quality image reproduction even in a consumer-use gage digital signal reproducing device having only a field memory that satisfies the above-mentioned demand for cost reduction, and can also perform high-quality image reproduction even in a high-end digital signal reproducing device having a frame memory. A digital video signal that has been converted in advance into a signal format that can be reproduced with high quality in the same manner as described above is recorded on a recording medium such as the digital audio disk, and an embodiment thereof will be described below with reference to the drawings. I will explain it together.

The frequency band of the brightness signal in the television broadcast signal is 4.2MHg in the NTSC system, and 4.2MHg in the PAL system and S
In the ECAM system, the frequency band is 5MHz or ■MHz, but in the NTSC system, the frequency band of the brightness signal actually transmitted is up to about 3MHz, and in the PA
The L method and the SECOAM method only utilize frequencies up to about 3 MHz to 4 MHz. Therefore, the sampling frequency is 8
Although it is possible to lower it to about MHz.

It is better to have some leeway. Therefore, the sampling frequency of the luminance signal is selected to be 9 MHz, which has a 3:2 relationship with respect to the above-mentioned 13.5 MHz. Also, the color difference signal (RY), (
The sampling frequency of B-Y) is selected to be 2.25 MHz, which is 1/4 of the frequency of 9 MHz.

Note that the number of bits in a memory circuit that stores digital video signals increases in proportion to the signal band frequency.
In addition to the standard mode digital video signals mentioned above,
Future number of scanning lines: 1125, luminance signal frequency band: 20
Considering the case where a digital video signal in MHz high-definition mode is also recorded, a code for identifying whether the mode is standard mode or high-definition mode is provided in a part of the header, which will be described later, for recording.

The number of luminance signal sampling points per scanning line of the standard mode digital video signal is 576, which is obtained by dividing the sampling frequency of 9 MHz by the horizontal scanning frequency of 15.625 kHz. However, in addition to lkigI information, this includes horizontal blanking periods such as the horizontal synchronization signal period and color burst signal period, and if we exclude sample points during this period, it is possible to reduce the number to about 456. can.

On the other hand, the number of bits of a general commercially available 64kRAM is 216 (=
65,536) bits, and if you use 4 of these, 4×
A number of bits of 216=218=262,144 (bits) is obtained. Dividing this number of bits by the number of luminance signal effective sample points of one horizontal optical scanning line, 456, yields approximately 574.87. Therefore, out of the 625 scanning lines in one frame, the effective number of scanning lines to be transmitted as an image is selected to be 572, which is extremely close to and smaller than the above 574.87. This means that each pixel data of the effective sample points of the luminance signal can be efficiently stored in four 64k RAMs per bit.

Furthermore, the amount of information of the two types of digital color difference signals obtained by digital pulse modulation of the two types of color difference signals (R-Y) and (B-Y) separately at a sampling frequency of 2.25 MH is as follows.
Since it is 1/4 of that of the digital luminance signal, the pixel data of the effective sample points of each digital color difference signal can be efficiently stored in one 64k RAM per bit. Therefore, assuming that the pixel data of one sampling point is 6 bits, the digital video signal obtained by chronologically synthesizing the above digital luminance signal and two digital color difference signals will consist of one frame. As shown by 6X(4+1+1)=36 (items), it can be stored in 36 64k RAMs. Two 1-field digital video signals can be stored using 64kRAM, which is equivalent to the number of 64kRAMs required for the aforementioned television studio memory circuit (20).
It is much less than 4, and can be realized at a low price.

In addition, in the case of component encoding, even if the pixel data of one sample point is quantized to 6 bits as described above, there is almost no problem in detecting quantization noise with standard consumer playback equipment. This was confirmed experimentally. Furthermore, according to this embodiment, since the number of chips per bit can be an integer, the address signal generation circuit for actually controlling the storage of digital video signals in the memory circuit can be shared, and memory control can be easily performed. This also eliminates the need for an extra buffer memory element added to facilitate memory control.

Next, the signal recording system of the present invention will be explained.

FIG. 1 shows a block system diagram of an embodiment of the main part of the system of the present invention. In the figure, reference numeral 1 denotes a video signal source such as a color television camera, flying spot scanner, VTR, etc., to which a TV synchronization signal from a TV synchronization signal generator 2 is supplied as necessary, and three signals related to the color image to be recorded are supplied.
The primary color signals are extracted and supplied to the matrix circuit 3.

Matrix circuit 3 has 625 scanning lines and horizontal scanning frequency 1
5,625kHz luminance signal Y and two types of color difference signals (B-
Y) and (-Y) respectively, and send these to the AD converter 4.
, 5 and 6 separately. On the other hand, the output TV synchronization signal of the TV synchronization signal generator 2 is output from the clock generators 7, 8, 12.
and 13, respectively.

The AD converter 4 converts the luminance signal Y into the clock generator 7.
The luminance signal is sampled at a sampling frequency selected to be 9 MHz for the reason described above using the same clock, and then quantized using an 8-bit quantization number, converted into a digital luminance signal, and supplied to the memory 9. As described above, this digital luminance signal has 456 sample points (pixels) per scanning line, and has 572 effective scanning lines for one frame. The memory 9 writes one frame or one field of the digital luminance signal according to the output write control signal of the memory write controller 12, and writes the digital luminance signal for one frame or one field at a sampling frequency of 44.1 kHz (or 47.5 kHz) according to the output read control signal of the memory read controller 14. 25kHz) and is read out as a digital luminance signal with 8 bits of quantization.

Further, the AD converters 5 and 6 output color difference signals (B-Y) and (R
-Y) are supplied to each side, and their input color difference signals are clocked by the clock generator 8 as described above.
．． After sampling at a sampling frequency selected to be 25 MHz, the signal is quantized using an 8-bit quantization number and converted into a digital color difference signal having 114 (=456/4) sampling points per scanning line. The memories 10 and 11 write and read the digital color difference signals taken out from the AD converters 5 and 6 for one frame (572 effective scanning lines) or one field in response to a write control signal from the memory write controller 13. The sampling frequency is set to 44.1kHz (or 47kHz) by the output readout control signal of the controller 14.
25 kHz) and read out as first and second digital color difference signals with a quantization number of 8 bits.

Here, the luminance signal, color difference signal (B-Y) and (R-
Y) is transmitted for one frame or one field, but
When playing back with a low-cost consumer digital signal playback device that only has field memory, or when performing fast-forward playback on a digital signal playback device that has frame memory, the first field (odd field) and the second field (even field) Since only the signal component of one of the fields is stored in the memory and reproduced, the vertical resolution is naturally lower than that of the reproduced image (frame image) when one frame is transmitted. Therefore, in the frame image, the oblique edges displayed as shown in Figure 2 (A) are the reproduced image when the same field described above is transmitted twice (this is referred to as one field image).
), the diagonal lines become step-like, as shown in FIG. In addition, the thickness of the horizontal line of the image becomes non-uniform in the field image, for example, when the frame image has horizontal lines with different thicknesses and positions as shown in FIG. 3(A),
As shown in Figure (B), the field image tends to be displayed as a horizontal line with emphasized differences in thickness and position, so this is a problem especially when displaying kanji on the screen. becomes.

Therefore, in the present invention, in order to suppress the decrease in the vertical resolution of the field image, taking into account playback by a digital signal playback device having only the above-mentioned field memory and field image playback by fast-forward playback, the following formula is used to suppress the decline in the vertical resolution of the field image. The digital video signal of one field is attenuated and mixed with the digital video signal of the other field, and this is recorded as a digital video signal of one field.

L2n+1'=L2n/4+L2n+1/2+L2n+
2/4(1) or L2n'=L2n-1/4+L2n/2+L2n+1/
4(2) However, in formulas (1) and (2), s L2n
(where n is a natural number) is a total of 684 pixel data at the 2nth scanning edge from the top on the screen, where the odd-numbered scanning line is the scanning line of the first field, and the even-numbered scanning edge is the scanning line of the second field. Assuming that it indicates a scanning line, L2n indicates pixel data of the scanning line of the second field. Also L2n+1
shows a total of 684 pixel data of the scanning line of the first field displayed next to the pixel data L2n of the scanning line of the second field on the screen. Therefore, when recording pixel data L2n+1' shown by equation (1) as pixel data of one digital video signal in the third field, (
1) As is clear from the formula, the pixel data obtained by multiplying each of the 684 pixel data L2n+1 of the first field of the 2n+1st scanning edge by 1/2, and the 2nth and 2n+2nd pixel data displayed above and below it on the screen The pixel data obtained by multiplying the 684th pixel data L2n and L2n+2 of the second field of each scanning line by 1/4 are respectively added, and the two pixel data on the screen are added.
It is recorded as 684 pixel data to be displayed on the n+1th scanning line. On the other hand, when recording the pixel data L2n' shown by equation (2) as pixel data of the digital video signal of the third field, as is clear from equation (2), 6
Pixel data of 1/2 times each of 84 pixel data L2n, and 2n-1st and 2m displayed above and below on the screen
The 684 pixel data L2n-1 and L2n+1 of the first field of the +1st scanning line are respectively added to the pixel data obtained by multiplying by 1/4, and the 684 pixels to be displayed on the 2nth scanning line on the screen are added. This is recorded as individual pixel data.

Here, 1/2 of the reduction ratio (mixing ratio) in equations (1) and (2) can be obtained by shifting the pixel data by 1 bit in the LSB direction, and the reduction ratio 1/4 is obtained by shifting the pixel data by 2 bits in the LSB direction (therefore, for example, L2n/4 is the pixel data L2n
It is obtained by shifting 2 bits toward the LSB. ).

In this way, the pixel data of the third field generated according to equation (1) or (2) is transferred to the first field or the second field.
When displayed on the screen instead of field pixel data, the contour of the boundary portion is replaced with an intermediate value, so jagged edges (so-called "jaggies") can be reduced. Furthermore, the field image of the third field is viewed with an impression similar to that of an actual frame image, and the effect is extremely large.

By the way, it is essentially up to you whether to perform matrix processing as shown in equation (1) or equation (2), that is, high-frequency component removal by image filtering in the vertical direction, on the playback device side or on the recording system. When the recording system is used as in the present invention, it is convenient for a low-cost digital signal reproducing apparatus having only a field memory.

However, in a high-grade digital signal reproducing device having a frame memory, the digital video signal of the third field has vertical high frequency components removed compared to the digital video signal of the first field or the second field. Since there is a lack of information, it is not recommended to play this as is. Furthermore, when the digital video signal of the third field and the digital video signal of the second field (or the first field) are respectively stored in the frame memory and played back and displayed, the images between the two fields are different and flicker occurs. This is not desirable because it is displayed on the screen as

However, the digital video signal of the third field can be reproduced as the original field digital video signal on the playback device side. For example, when the digital video signal of the third field shown in equation (1) is restored and reproduced, The pixel data L2n in the digital video signal of the second field that is reproduced as the other field signal is multiplied by 1/4 (shifted by 2 bits in the LSB direction), and this is subtracted from the pixel data L2n+1' shown in equation (1). When the pixel data L2n+2 is reproduced from the first subtraction signal obtained by By doubling it, the original pixel data L2n+1 of the first field can be restored. In this case, when the pixel data L2n+1' is transmitted in 8 bits, the restored and reproduced pixel data L2n+1 becomes a 1-bit signal in which the LSB information is lost;
The image quality of the bits is good enough and does not pose any practical problems.

In view of the above, the present invention records the digital video signal of the third field in the case of field forwarding, and records the digital video signal of the third field and the second field shown in equation (1) in the case of frame forwarding. The digital video signal of the first field (or the digital video signal of the fourth field and the digital video signal of the first field shown in equation (2)) are respectively recorded on a recording medium.

The mixing process shown in equation (1) or equation (2) above is performed in memories 9, 10, and 11 shown in FIG.

Memories 9, 10, and 11 each consist of a main memory, an auxiliary memory, and an arithmetic circuit, and store pixel data from the main memory of scanning lines to be mixed in the auxiliary memory, read out the data sequentially, and perform arithmetic operations on the arithmetic circuit. The above mixing process is performed by storing the data in the main memory again.

On the other hand, a signal enters the input terminal 16 every time the color image information to be recorded changes, and is supplied to the header signal generator 17. The header signal generator 17 generates a 16-bit header signal, which is a set of signals and codes constituting the header section, and supplies this to the memory 18. memory 1
8 transmits the header signal at a sampling frequency of 44.1 kHz (or 47.25 kHz), for example, with a 684-word transmission period period.
g) Read with a quantization number of 16 bits.

The switching circuit 15 switches the digital luminance signal from the memory 9, the first and second digital color difference signals from the memories 10 and 11, and the header signal from the memory 18 in a predetermined order, respectively. A digital video signal having a signal format as shown in FIG. 5 is generated and supplied to the digital recorder 18 where it is recorded. Note that a read control signal is output from the memory read controller 14 in synchronization with a clock signal from the digital recorder 19.

Next, the signal format of the above digital video signal will be explained in more detail. The digital video signal taken out from the switching circuit 15 is composed of a 12-word header portion and a 684-word component encoded video signal portion of 2H (H is a horizontal scanning period), which are synthesized alternately in time series. This is a signal in which a signal transmission end signal (hereinafter also referred to as "EOD signal") is added to the last word, and when one frame's worth of image information is transmitted, as shown in Figure 4. , H1 to H286 (however, H
A part of 286 headers (1 to H286 are not shown),
V1 to V286 (however, V5 to V285 are not shown)
A total of 199,057 words of digital video signals are recorded, consisting of 286 video signal parts indicated by , and one word of EOD signal indicated by EOD.

Therefore, the digital video signal for one frame is
The above-mentioned digital audio disc includes the 8th part described below.
If it is assumed that one word is recorded in one channel of 16-bit transmission line in one block of the signal shown in the figure, the signal period of this one block and the reciprocal value of the sampling frequency of the header signal are as follows. If they are selected equally, when the sampling frequency is 44.1 kHz, it will be transmitted in about 4.51 seconds, and when it is 47.25 kHz, it will be transmitted in about 4.21 seconds.

In each of the above headers H1 to H286, a fixed pattern synchronization signal is placed in the first word (one word consists of 16 bits), and the next word is either the standard mode or high definition mode as described above. An image type identification load to identify whether the video is based on a run length code from the display mode, a code for converting the number of scanning lines, and a code to specify whether the memory circuit in which data is written is a display side memory circuit or a non-display side memory circuit. Further, codes indicating the amount of image information and other various image information are arranged, and address signals are arranged in the next third to sixth words. And then the next 6th word from the 7th word to the 12th word.
In each word, codes having the same content as the first six words are arranged in the same arrangement.

However, only the synchronization signal has a different value.

In this way, information 1 in the header section is sent twice because there is no data correlation between adjacent words in the header signal, so it is difficult to correct it if the contents of the header signal are not transmitted. Therefore, the video signal portion immediately after that cannot be captured, and 2H worth of pixel data will be missing. Therefore, the information in the header section is sent twice, and even if the first half header signal section is not reproduced, the second half header signal section is used to capture pixel data. Of course, part of the information in the header may be sent once and may be composed of 6 words.

Next, the signal formats of the video signal sections V1 to V286 shown in FIG. 4 will be explained. FIG. 5 shows an embodiment of the signal format of the video signal section V1. In the figure, the vertical direction shows the bit array, the upper side is the MSB, the lower side 1 is the LSB, and the horizontal direction shows the time.
It is similar to the figure. As mentioned above, in this embodiment, each of the 286 video signal sections V1 to V284 is composed of 684 words. ) Among the pixel data of the two scanning lines of a field, the pixel data of the scanning line of one field is placed in the upper 8 bits, and the pixel data of the scanning line of the other field is placed in the lower 8 bits and transmitted. Ru. Therefore, the signal format of the first video signal portion V1 is as shown in FIG. A digital video signal sequence of The lower 8 bits of the second scanning line (second (
The digital video signal sequence of each sample point (that is, the pixel data from the pixel group in the second row) of the first Hth field) is arranged.

In addition, in Fig. 5, Y0 to Y455 (however, Y10 to
Y455 (not shown) indicates each arrangement position from the first sample point to the 456th sample point of the digital luminance signal of the first scanning line, and Y456 to Y911 (however, Y466 to Y911
(not shown) is the first digital luminance signal of the second scanning line.
Each arrangement position from the sample point to the 458th sample point is shown. Also (R-X)0~, (RY)113, (B-Y)0~
(B-Y) 113 (However, (RY) 2 ~ (RY) 1
13 and (B-Y) 2 to (B-Y) 112 (not shown) are the digital color difference signals (R-Y) and (B-Y
) from the first sample point to the 114th sample point are shown. Furthermore, (RY)114 to (RY)227, (B
-Y) 114 ~ (B-Y) 227 (However, (R-Y) 1
16~(RY)227 and (B-Y)116~(B-Y
) 226 (not shown) indicate the respective arrangement positions of the digital color difference signals (R-Y) and (B-Y) of the second scanning line from the first sample point to the 114th sample point. Therefore, the video signal section V
1 consists of a group of 2H worth of pixel data of the first and second scanning lines, consisting of pixel data of four sample points of the digital luminance signal and pixel data of one sample point of each of the two types of digital color difference signals. The signal format is such that six pixel data are set as one unit, and each unit is repeatedly transmitted. Note that the other video signal sections V2 to V286 are also
They each have the same signal format as V1.

Rather than arranging the pixel data of the same scanning line in the same word as shown in Fig. 6, the pixel data of two adjacent scanning lines are divided and arranged in the same word as shown in Fig. 5. This is to facilitate conversion of the number of scanning lines in consideration of the case where the number of scanning lines is converted from 625 lines to 525 lines as will be described later. Furthermore, by transmitting the same pixel data of two adjacent scanning lines in the same word, the number of times of memory writing and reading can be reduced in the calculation for converting the number of scanning lines from 625 to 525.

Note that when the value of each word in the video signal sections V1 to V286 becomes equal to the value of each signal in the header sections H1 to H286 and the value of the EOD signal, it is changed to another value close to the value of each signal in the header sections H1 to H286.

Further, in the above embodiment, the signal format for transmitting one frame has been explained, but when transmitting one field, the signal of one of the third and fourth fields is The signal is transmitted in a signal format as shown in FIG. In this case, the pixel data of the n-th scanning line of the same field is arranged in the upper 8 bits of the same word, and the pixel data of the n+1-th scanning line is arranged in the lower 8 bits.

Next, a recording system for recording the above-mentioned digital video signal onto the above-mentioned digital audio disc will be explained.

Here, the digital video signal is transmitted on one or two channels out of a total of four transmission channels, and the digital audio signal is transmitted on the remaining channels, but as an example, the digital video signal is transmitted on one channel. Let me explain using an example. Further, for convenience of explanation, the digital audio disc will be explained by taking as an example a capacitance change reading type disc previously proposed by the present applicant.

FIG. 1 shows a block system diagram of one embodiment of the above recording system. In the figure, the same components as in FIG. 1 are designated by the same reference numerals. Reference numerals 30, 31, and 32 are input terminals into which three channels of analog audio signals are input separately, and the three channels of analog audio signals include a signal for central sound localization, so that in conventional two-channel stereo, Real image localization of the central sound source and expansion of the listening range, which could not be achieved previously, can be achieved. 33 is a start signal input terminal;
Reference numeral 34 is an input terminal for a cue signal generated each time the music program of the analog audio signals of the three channels is switched from the previous music program to another music program.

Here, assuming that the amount of information for one channel is recorded on a disk 40 to be described later, for example, four channels of digital signals with a sampling frequency of 47.25 kHz and a quantization number of 16 bits are recorded in one track in time series. 3 above
The analog audio signal of the channel is sent to the AD converter 35.
Therefore, each channel has a sampling frequency of 47.75kHz.
2 and converted into a digital audio signal (PCM audio signal) with a quantization number of 16 bits, which is supplied to the signal processing circuit 37, and simultaneously reproduced by the digital recorder 18 as shown in FIG. A digital video signal with a sampling frequency of 47.25 kHz and a quantization number of 16 bits is processed by the signal processing circuit 37 in the signal format.
supplied to Further, a control signal generation circuit 38 to which a start signal input to the input terminal 33 and a cue signal input to the input terminal 34 are respectively supplied generates a control signal having a configuration shown in FIG. 37. The control signal controls the position of the pickup reproducing element (as described later).
random access), etc.

The signal processing circuit 37 rearranges these 16-bit input digital signals and control signals of a total of four channels from parallel data to serial data, and
The digital signals of each channel are divided into predetermined intervals, and the signals are interleaved and time-division multiplexed. Then, a recording signal is generated by adding an error code detection signal, an error code detection signal, and a synchronization signal bit indicating the start of a block (frame).

FIG. 8 is a diagram schematically showing an example of one block (one frame) in the recording signal generated as a result of signal processing by the signal processing circuit 37. One block is composed of 130 bits, and its repetition. The frequency is the same as the sampling frequency 47.
It is 25kHz. SYNC is 1 indicating the beginning of the block
0-bit fixed pattern synchronization signal bits, Ch-1~
Ch-3 indicates the 16-bit digital audio signal of the three channels, and Ch-4 indicates the multiplexing position of one word of the 18-bit digital video signal reproduced from the digital recorder 9. Furthermore, P and Q shown in FIG. 6 are 16-bit error code correction signals, for example, P=W1■W2■W3■W4(3) Q=T4・W1■T5・W2■T2・W5■T・W4(
4) is a signal generated by the following equation. However, (3
), (4) where w1, w2, w3, w4 are Ch-1 to C
h-4 16-bit digital signals (usually digital signals in different blocks), T is an auxiliary matrix of a predetermined polynomial, and ■ indicates modulo-2 addition for each corresponding bit.

Furthermore, in FIG. 8, CRC is a 23-bit error code detection signal, and Ch-1 to Ch-4, which are arranged in the same block,
For example, each word of P and Q is X23+X5+X4+x+1
This is the 23-bit remainder obtained when dividing by the generator polynomial, and when the signal from the 11th bit to the 129th bit of the same block is divided by the generator polynomial during reproduction,
When the resulting remainder is zero, it is used to detect that there is no error. Furthermore, in Figure 8, Adr
is the control signal, and each bit data is distributed and transmitted one bit in one block. For example, all bits of the control signal are transmitted by 126 blocks (that is, the control signal is composed of 128 bits). . Therefore, when the rotational speed of the disk 40 is 800 rpm, 3150 blocks are recorded and reproduced per one rotation of the disk, so the above 126-bit control signal is divided into two blocks during one rotation of the disk.
It will be recorded and played back five times.

FIG. 9 schematically shows an example of the structure of the above control signal.

The total 126-bit control signal is composed of a 42-bit first chapter code CP-1, a 42-bit second chapter code CP-2, and a 42-bit time code TC. The first chapter code CP-1 is 1
It is obtained by adding the 7-bit synchronization signal, the 4-bit mode signal, the 8-bit chapter signal, the 12-bit chapter local address, and the signal bits from the mode signal to the chapter local address modulo 2. It consists of a 1-bit parity code and a 1-bit parity code.
The second chapter code CP-2 also has the same configuration and the same values as the first chapter code CP-1 except for the value of the synchronization signal. The above mode signal is a signal indicating the division of 4 channels of digital signals recorded on the disk 40. For example, when it is "1100", 3 channels of digital audio signals and 1 channel of digital video signals are recorded. , “11
01", a 4-channel digital audio signal is recorded, "1110", 2 types of 2-channel digital audio signals are recorded, and "1111", a 2-channel digital audio signal and Indicates that the digital video signal is being recorded in two channels. The chapter signal is a signal indicating the number of the recorded music program from the signal recording start position on the disc 40.

Further, the time code TC shown in FIG. 9 includes, for example, a 17-bit synchronization signal and first and second chapter codes CP-
1. Similar to the mode signal in CP-2, the type of 4-channel digital signal recorded on the disk 40 is 4.
A bit mode signal, a 16-bit time identification code that indicates the position of the recorded music program on the disk 40 in terms of the total time from the signal recording start position, and a time identification code that increases by 1 for each revolution of the disk 40 and is set to "0". It consists of a 4-bit track number code indicating a value of ~14 in binary code, and a 1-bit parity code. The above time identification code is expressed in minutes or seconds, and its minimum unit is 1 second. However, if the disk 40 rotates at 900 rpm, it will rotate 155 times per second, so the time identification code Even if the codes have the same value, the music program recording position can be identified each time the disk 40 rotates by the track number.

A digital signal of 130 bits per block shown in FIG. 8 is sequentially extracted block by block from the signal processing circuit 37 in series and supplied to the modulation circuit 38 shown in FIG. ), for example, 7M
A Hz carrier wave is frequency modulated to produce a frequency modulated wave signal. This frequency modulated wave signal is recorded on the disk 40 by a recording device 39 using a laser beam or the like.

When the disc recording method previously proposed by the present applicant is applied, the recording device 39 described above has a configuration as shown in FIG. 10. In the figure, a laser beam emitted from a laser light source 41 is removed by an optical modulator 42 to remove drift and noise of the laser beam, and then reflected by a reflecting mirror 43 and divided into two optical paths by a half mirror 44. . The split loser light is sent to the input terminal 4 in the optical modulator 45.
The light beam is modulated by the output frequency modulated wave signal of the modulation circuit 38 from 6 and a third tracking control reference signal fp3 to be described later, and is made into a first modulated light beam. The other divided laser beam is inputted to the optical modulator 47 from the input terminal 48 by a first or second tracking control reference signal f, which will be described later, which alternately enters every rotation period of the recording master 49.
It is modulated by p1 or fp2 to form a second modulated light beam.

The first modulated light beam is reflected by a reflecting mirror 50, has its optical path changed, and passes through an information recording optical system consisting of cylindrical lenses 51 and 52, a slit 53, and a convex lens 54, thereby forming a rectangular shape on the recording master 49. It is shaped into a light. On the other hand, the second modulated light beam is transmitted through the convex lens 5
5, a tracking recording optical system consisting of a slit 56 and a convex lens 57 shapes the light into a circular shape on the recording master 49, and then the optical path is changed by a reflecting mirror 58.

The first and second modulated light beams, each shaped into a desired shape, are combined on substantially the same optical axis by a polarizing prism 53, pass through a half mirror 60, and have their optical paths changed by a prism 61. Furthermore, a slit 62 and a recording lens 63
The first modulated light beam is formed in a rectangular shape as shown by 66, and the second modulated light beam is in a circular shape as shown in 67, on the recording master disk 49 on which a photosensitive agent layer 65 is formed on a glass substrate 64. irradiation is performed in a focused manner.

The recording master disk 49 is disk-shaped and is rotated synchronously at a constant speed.The light reflected from the half mirror 60 is applied to a signal monitoring system 68, and the light reflected from a prism 61 is applied to a monitoring optical system 69. Added. The distance between the two modulated light beams on the recording master 4s is measured by the monitoring optical system 68, and the deviation is monitored by the signal monitoring system 68, and the deviation is corrected by moving the cylindrical lens 51 in the vertical direction in the figure. Let's do it.

The recording master disc 49 is subjected to a known development process and a disc making process to create a stamper disc. On the disk 40 copied by this standby disc, the three channels of digital audio signals described above and the one channel digital video signal in the signal format shown in FIG. 4 or 5 are sequentially stored in the signal format shown in FIG. 8. A spiral main track in which the frequency modulated wave of the signal synthesized in block units in time series is recorded as an intermittent bit string;
Approximately in the middle between the track center lines of adjacent main tracks, first and second burst-shaped bursts of a single frequency are alternately arranged in a band lower than the band of the frequency modulated wave for each rotation period of the disk. 2 tracking control reference signals fp1 and f
A sub-track recorded by a bit string in which p2 is intermittent is formed, and a third tracking control reference signal f is formed on the main track at the switching connection portion of fp1 and fp2.
p3 is recorded. Further, this disk does not have a guide groove for tracking the reproduction needle, and has an electrode function.

As described above, according to the present embodiment, each of the 684 pixel data of one scanning line is combined with the digital video signal of the third field generated according to the above equation (1) or (2).
The digital video signal of the field or the first field is recorded on the disk 40 in time series along with the digital audio signal at a lower sampling frequency.

Next, an explanation will be given of an apparatus for reproducing digital signals recorded on the disc 40 according to the method of the present invention.

FIG. 11 shows a block diagram of an example of a digital signal reproducing device. In the figure, the disk 40 is a turntable (
(not shown) and rotated synchronously at 900 rpm. As shown in FIG. 12, on the disk 40 there is a main track with a track width TW and a track pitch TP, in which a flat surface 70 and bits 71 are repeated, and a tracking control system, in which a flat surface 70 and pits 12 are repeated. As described above, the reference signal fp1 recording sub-track for tracking control and the tracking control reference signal fp2 recording sub-track formed by repeating the flat surface 70 and pits 13 are formed, respectively. The bottom surface 14b of the regeneration needle 14 is made to slide on the surface.

As shown in FIG. 11, the regeneration needle 74 is fixed to one end of a cantilever 75, and a permanent magnet 76 is fixed to the base side of the other end of the cantilever 75. cantilever 7
The part to which the permanent magnet 76 of No. 5 is fixed is a tracking coil 77 and a jitter correction coil 7 fixed to the playback device.
It is surrounded by 8. The tracking coil 77 generates a magnetic field in a direction perpendicular to the magnetic field direction of the permanent magnet 76, and moves the cantilever 75 in one direction in the track width direction according to the polarity of the tracking error signal from the tracking servo circuit 79. , and displace it by a displacement amount corresponding to its size.

The capacitance formed between the disk 40 and the electrode 74a shown in FIG. A resonant circuit, a circuit that applies a constant frequency to this resonant circuit, a circuit that amplitude-detects a high-frequency signal whose amplitude changes according to the change in the capacitance from the resonant circuit, and a circuit that detects the amplitude of a high-frequency signal whose amplitude changes according to a change in the capacitance. A high frequency reproduction signal extracted from a pickup circuit 80 comprising a circuit for pre-amplifying a reproduction signal (reproduction signal) is supplied to an FM demodulation circuit 81, where the main information signal of the main track (in this case, a digital audio signal and a time series The digital video signals (combined digital video signals) are each demodulated, while a portion is branched and supplied to a tracking servo circuit 79.

The tracking servo circuit 79 detects the first signal from the reproduced signal.
to third tracking control reference signals fp1 to fp3
are frequency-selected and taken out, and both reference signals fp1 and fp2 are extracted.
A tracking error signal obtained by differentially amplifying the envelope detection output is output to the tracking coil 77. However, since the recording positional relationship of fp1 and fp2 with respect to the main track is switched every cycle of the rotation axis of the disk 40, the tracking polarity of the disk 40 is changed by the switching pulse generated based on the detection output of the tracking control reference signal fp3. It is switched every rotation period. Note that when a kick instruction signal is received at the input terminal 82, the tracking servo circuit 73 drives the tracking coil 77 so as to forcibly move the playback needle 74 in the track width direction by one track pitch or more. do.

On the other hand, the demodulated digital signal taken out from the FM demodulation circuit 81 is applied to the decoder 13, where it is MFM decoded and converted into a time-series composite signal in the signal format shown in FIG. The beginning of a signal block is detected and converted into a serial signal into a parallel signal, and further error detection is performed. Only when an error is detected, the error code correction signals P and Q are used to correct and restore the error signal. In this way, each of the three channels of the 16-bit 4-channel digital signal is corrected and restored as necessary to be error-free and returned to the original order before the signal arrangement was interleaved. The 16-bit digital audio signal is
After being converted into an analog audio signal by the DA converter in the Tecoder 83, it is outputted to output terminals 84, 85 and 86, respectively. Further, the pickup control signal is output to a predetermined circuit (not shown) for high-speed position search and the like.

On the other hand, the digital video signal in the signal format shown in FIGS. 4 and 5, which is reproduced in time series on the fourth channel, is supplied to the scanning line number conversion circuit 87 shown in FIG. The number is converted from the 625-line system to the 525-line system.

FIG. 13 is a diagram schematically showing how the number of scanning lines is converted. In the figure, Y0 is the first digital luminance signal of the first scanning line of the 625 scanning line system as shown in FIG.
In the pixel data of the sampling point, Y456 similarly indicates the pixel data of the first sampling point of the digital luminance signal of the second scanning line.

As can be seen from FIG. 5, the above pixel data Y0 and Y4S6 are transmitted at the beginning of the video signal section V1, but the data obtained by multiplying this pixel data Y0 by 3/4 (this is Y
(created by adding data in which 0 is shifted in the direction of 1 bit LSB and data in which Y0 is shifted in the direction in 2 bits LSB), and 1/4 data in which pixel data Y4S6 is shifted 2 bits in the direction of LSB. Pixel data Y0' of the first sampling point of the first scanning line of the 525-scanning-line digital luminance signal is generated by mixing them, and
Data 1/2 times the pixel data Y456 is stored in the auxiliary memory (
1 line memory) 103. Hereinafter, in the same way as above, the pixel data of each sample point of the first scanning line of the 625 scanning line method is multiplied by 3/4, and the pixel data of each sample point of the second scanning line is multiplied by 1 The data obtained by multiplying /4 are mixed at sample points in the same word, and the number of scanning lines is 5.
The pixel data is converted into pixel data of the first scanning line of the 25-line system.

Next, the pixel data of each sample point of the first scanning line of the 625 scanning line system of the video signal V2 to be reproduced is multiplied by 1/2 (
(obtained by shifting one bit in the LSB direction), and then mixed with pixel data read from the auxiliary memory 103 of the same sample point and converted into pixel data of the second scanning line of the 525 scanning line system. . Y912 is the pixel data of the first sampling point of the digital luminance signal of the third scanning line of the 625 scanning line system, and Y456' is the pixel data of the first sampling point of the digital luminance signal of the second scanning line of the 525 scanning line system. Each pixel data is shown. Also Y1368, Y1824,
Y2280 is the pixel data of the digital luminance signal of 625 scanning lines, and Y1368 is the pixel data of the 1st of the 4th scanning line.
Sample point Y1824 is the first sample point of the fifth scanning line, Y22
8O indicates pixel data of the first sample point of the sixth scanning line. Furthermore, Y912', Y1368, and 1824' are pixel data of digital luminance signals of 525 scanning lines, respectively.
912' indicates the first sampling point of the third scanning line, Y1368' indicates the first sampling point of the fourth scanning line, and Y1824' indicates the pixel data of the first sampling point of the fifth scanning line.

As shown in Figure 13, the number of scanning lines such as Y912 is 62.
The pixel data of each sample point on the third scanning line of the 5-line method is halved.
The multiplied data is mixed with the data obtained by multiplying the pixel data of each sample point of the fourth scanning line such as Y1368 by 1/2, respectively.
While the pixel data of each sample point of the third scanning line of the 525 scanning line system such as 912' is obtained, the latter data is stored in the auxiliary memory (one line memory) 104. Similarly, the pixel data of each sample point of the fifth scanning line such as Y1324 is multiplied by 3/4, and then mixed with the pixel data of the same sample point read out from the auxiliary memory 104 and multiplied by 1/2. The fourth type of 525 scanning line system such as Y1368'
The pixel data of the scanning line is obtained, and the sixth pixel data such as Y2280 is obtained.
The pixel data of the scanning line is directly used as the pixel data of the @S scanning line of the 525 scanning line system. Thereafter, the same operation as above is repeated, and the pixel data of the 6 scanning lines of the 625 scanning line system are mixed at a predetermined mixing ratio, so that the number of scanning lines is 5.
The pixel data is converted into pixel data of five scanning lines using the 25-line system.

Here, as is clear from the above description, the auxiliary memories 103 and 104 used in the calculation of scanning line number conversion are a common 1-line memory that is used in turn. on the other hand,
As mentioned above, the number of sample points (number of pixel data) of the digital luminance signal is 260,832, which is expressed as the product of 456 sample points per horizontal scanning line and 572 effective scanning lines. , the number of bits of four 64kRAMs is 26
Since it is 2,144 (=216X4) bits, 131
This means that there is a margin of 2 bits. That is, four 6
The 4kRAM has an extra memory capacity that can store each 1 bit of pixel data of sampling points of digital luminance signals for 2H or more, so this is stored in the auxiliary memory 103 described above.
and 104. Note that the reading and writing of the auxiliary memories 103 and 104 are performed within the horizontal blanking period of the standard television system (NTSC system here) color video signal taken out from the output terminal 102.

Further, the above-mentioned scanning line number conversion circuit 87 is connected to a memory 84 which will be described later.
, 85 are field memories, the above-mentioned scanning line number conversion is performed on the reproduced third field digital video signal itself, and on the other hand, the memory 94
. After restoring and reproducing the data, the above scanning line number conversion is performed. Note that the pixel data that can actually obtain good image quality is 6 bits, but on the other hand, as mentioned above, the LSB 1 bit information is lost due to the inverse calculation process, so in order to reproduce with good image quality, at least 7 (= 6+1) bits or more must be subjected to inverse arithmetic processing. When performing the above-mentioned inverse arithmetic processing within a playback device, it is better to transmit adjacent scan-like pixel data in the same word as described above, since the memory writing and
The number of reads can be reduced, and the number of auxiliary memories required for calculations can also be reduced.

In this way, the scanning layer number conversion circuit 87 converts the number of scanning lines to 6.
This circuit converts 25-line pixel data into 525-scanning line pixel data, and since the pixel data is transmitted in the format shown in FIG. 5, the conversion operation is easy. This scanning line number conversion circuit 87 is a circuit necessary only for a playback device that reproduces and outputs an analog color video signal compliant with the NTSC system as shown in FIG.
This circuit is unnecessary for a playback device that plays back and outputs an analog color video signal that conforms to the standard. However, depending on the playback device, a changeover switch is provided to change the input/output of the scanning line number conversion circuit 87, and the circuit 87 is switched to be activated or deactivated depending on the number of scanning lines of the television system to be reproduced. Good too. The output pixel data of the scanning line number conversion circuit 87 is transferred to the memory 94 or 9 by the switch circuit 88.
5.

Further, the digital video signals sequentially and time-sequentially extracted from the decoder 83 in the signal format shown in FIG.
The signal is also supplied to a synchronizing signal detection circuit 89, a header signal detection circuit 91, and a memory write controller 92, respectively. The synchronization signal detection circuit 89 detects the synchronization signal in the header signal and supplies the detection signal to the control circuit 90 . Further, the header signal detection circuit 91 discriminately reproduces each code and address signal except for the synchronization signal in the header signal, and the control circuit 91
supply to

The control circuit 90 is supplied with the synchronization signal detection signal and each code detection signal of the header signal, and furthermore, the control circuit 90 is supplied with the above-mentioned synchronization signal detection signal and each code detection signal of the header signal. When an image is recorded, a signal specifying the image (which can be arbitrarily selected) is supplied from the input terminal 93, and these input signals are discriminated and decoded and sent to the scanning line number conversion circuit 87 and the switch circuit 8.
8. Controls the memory write controller 92, switching circuit 97, etc. The memory write controller 92 causes pixel data in the digital video signal supplied to the memory 94 or 95 to be written to a predetermined address based on the address signal in the header signal, but not to write the header signal and the EOD signal. Control. switch circuit 88
is switched to terminal a or b by a control signal from the control circuit 90 based on the memory write designation code in the header signal, and supplies the digital video signal to the memory 94 or 95 designated by the memory write designation code.

Memories 94 and 95 store reproduction pixel data for one frame written based on a read control signal from a memory read controller and synchronization signal generation circuit 96, or reproduction pixel data written for one field each for a total of two fields. In addition to reading out pixel data simultaneously, it also corrects jitter associated with reproduction.

Here, the digital luminance signals read out from the memories 94 and 95 are read out at a sampling frequency of 9 MHz and a quantization number of 8 bits, and the first and second digital color difference signals are read out at a sampling frequency of 2.25 MHz and a quantization number of 8 bits, respectively. The data is read out in 8 bits and supplied to the switching circuit 97, respectively.

Next, the configuration and operation of the memories 94 and 95 will be explained in more detail. FIG. 14 shows a block system diagram of an example of the memories 94, 95 and a part of the memory write controller 92. A part of the scanning line number conversion circuit 87 (auxiliary memory) can also be included in this. In the same figure, M11, M2
1,...,M61,M12,M22,...,M62,M
13, M23,..., M65,..., M66 are each 64
These 36 RAMs in total are supplied with an address signal from a common address signal generation circuit 105 in the memory write controller 92. When the memories 94 and 95 are frame memories, there are 36 RAs.
A total of two sets of MM11 to M66 are required, but if it is a field memory, one set is sufficient. Also, although not shown,
A first buffer memory stores a group of pixel data transmitted in the upper 8 bits of each word of the video signal portion having the signal format shown in FIG. A second buffer memory is provided for storing a group of pixel data transmitted in six words of pixel data each.

In addition, B1, B2, B3, ..., B6 are the first and second
S1 is an S contact changeover switch (actually an electrically operated analog switch) which is supplied with pixel data from the buffer memory and selects and outputs it.
Any one of M12,...,M16
Supply the MSB of pixel data to AM.

Similarly, among the changeover switches B2 to B6, Si (however,
i=2 to 6) supplies the first most significant bit of the pixel data to any one of the RAMMij (where j=1 to 6). Therefore, in the memory circuit shown in FIG. 14, the lower two bits of the 8-bit pixel data are discarded, but their influence on the reproduced image does not pose much of a problem. Of course, all 8 bits of pixel data may be stored by adding 12 more 64kRAMs, but as a consumer digital video signal reproducing device, the 14th
It is more advantageous in terms of cost to use a memory circuit with the configuration shown.

Next, to explain the operation of the above memory circuit, first,
The hexadecimal value from the address signal generation circuit 105 is “0”.
The 16-bit address signal “000” is RAMM1.
1 to M66, respectively. On the other hand, selector switch S1
~ RAMM11, M21, M31, M through S6 respectively
41, M51 and M61 contain pixel data Y0 shown in FIG.
The upper 6 bits of the data are supplied. As a result, RAMM1
The MSB data of Y0 is in the address “0OOO” of 1.
The data of the second most significant bit of Y0 is stored at the address "0000" of M21. M31, M41, M51
and Y0 in the same way to the address “0000” of M61.
The data of the third, fourth, fifth, and sixth most significant bits are stored, respectively.

Next, leave the value of the address signal as it is and switch S1~
S6 is switched, and the upper 6 bits of pixel data Y1 are R.
AMM12, M22, M32, M42, M52 and M6
2, one bit is supplied to each address, and the address “000
0". Thereafter, in the same manner as above, the value of the address signal is left as is, and the changeover switches S1 to S
86 are switched sequentially, RAMM16, M2
6, Pixel data (B-Y) 0 is placed at the address of M36, M46, M56, and M66 with the value "0000" in hexadecimal notation.
When the upper 8 bits of data have been stored one bit at a time, an address signal indicating an address with the value "0001" in hexadecimal notation is output from the address signal generating circuit SO5, and in the same manner as above, RAMM11 to M66 address “
0001'', pixel data Y4, Y5, Y6, Y7, (
R-Y)1 and (B-Y)1 are stored one bit at a time. After that, the same operation as above is repeated and the address becomes 1.
The pixel data group of one scanning line increases step by step and is stored in RAMM.
11 to M66, an address signal with a hexadecimal value of "0072" is generated from the address signal generation circuit 105, and is passed through the changeover switches S1 to S6 to the second scanning line shown in FIG. The upper 6 bits of pixel data Y456 of the first sampling point are RAMM11, M21, M3.
1, M41, M51 and M61 one bit at a time and stored. After that, the changeover switches S1 to S6 are changed while the value of the address signal remains unchanged, and the upper 6 bits of the pixel data Y467 are changed to RAMM12, M22, . . .
..., is applied to M62. This allows RAMM
Pixel data Y457 is at address “0O72” of 12R.
MSB data is involved, RAMM22, M32
,..., address "0072" of M62 has M45 respectively.
The data of the second bit, third bit, . . . , and sixth bit of 7 is written. Thereafter, the address is incremented by 1 in the same manner as described above, and writing of the pixel data group of the second scanning line is completed. The pixel data of the first six words of the third scanning line are stored in the address with the hexadecimal value "00E4", and the pixel data of the first six words of the fourth scanning line are written with the hexadecimal value "00E4". 0156" address.

In this way, one frame or one field's worth of pixel data is written into the memories M11 to M66 for two fields, but among the pixel data transmitted in six consecutive words, six pixel data (digital 36 RAMMs (consisting of 4 pixel data of luminance signal and 1 pixel data of 2 types of digital color difference signals)
It is written to the same address from 11 to M66. Here, since the memory circuit shown in FIG. 14 is driven by the same address signal, writing and reading must be performed in a time-division manner. Specifically, the read control signal from the memory read controller and synchronization signal generation circuit 96 shown in FIG.
), reading from RAMM11 to RAMM66 is performed, writing is performed within a horizontal blanking period (approximately 13 μsec), and reading and writing from the auxiliary memory for scanning line number conversion are performed.

Further, by reading out RAMM11 to M66, the above-mentioned six pixel data at the same address are read out simultaneously.

Returning to FIG. 11 again, the read pixel data of one of the memories 94 and 95 configured as shown in FIG. The selected output is
The pixel data of the digital luminance signal is supplied to the DA converter 98, and the pixel data of the two types of digital color difference signals are supplied to the DA converter 98.
The signals are supplied to converters 99 and 100, respectively. Here, the switching circuit 97 selects and outputs the readout output of one of the memories 94 and 95 from the memory that had been selectively outputting the readout output of the other memory in accordance with the switching control signal supplied when the EOD signal is detected. can be switched to

The analog luminance signal taken out from the DA converter 98 and the D
Color difference signals extracted from A converters 99 and 100 (B
-Y) and (R-Y), horizontal and vertical synchronization signals and color burst signals taken out from the memory read controller and synchronization signal generation circuit 96 are respectively supplied to the encoder 101, and the color burst signals conform to the NTSC system. After being generated as a video signal, it is outputted from the playback output terminal 102 to a color television receiver for monitoring (not shown), where you can listen to the audio signal that is outputted from the output terminals 84, 85, and 86 to be sounded. The images are displayed as color still images or partial moving images as supplementary information for people's music appreciation.

As can be seen from the explanation in FIG. 14, if each pixel data is composed of n bits, the memories 94 and 95 can be constructed using (4+1+1)Xn number of 64kRkM. If it is acceptable to lower the resolution of the (4+1)
Xn, that is, when n is 6 bits, 30 64kR
With AM, memories 94 and 95 can be configured.

Furthermore, since 256kRiM is 282,144 (=218) bits, it is preferable that one frame of one bit signal can be written in one RAM. In this case, although it depends on the read speed of the RAM, if the read speed is slow, there is also a method of configuring it as a 2-frame memory circuit and using the two RAMs in a time-sharing manner. Furthermore, the digital color difference signal is read out from the memory 94 at 1/4 of the readout speed of the digital luminance signal.
, 95, one RAM can be used for two types of digital color difference signals in a time-sharing manner.

Note that the above explanation has been about image transmission in standard mode, but when transmitting high-definition, high-quality images, or when transmitting moving images using run-length codes, the image type provided in the header signal The value of the identification code is discriminated and reproduced, and the output signal of the control circuit 90 controls the scanning line number conversion circuit 87 and the memory write controller 92 as necessary to select the format for loading into the memories 94 and 95.

Furthermore, when the memories 94 and 95 are respectively field memories, it goes without saying that the reproduced digital video signal of the first field is written into the memories 94 and 95. In this case, only the upper 8 bits or lower 8 bits of pixel data of each word in the signal format shown in FIG. 5 will be written into the memories 94, 95.

In addition, in the above explanation, the case where it is applied to the disk recording method and playback device proposed earlier by the present applicant has been explained, but it is not limited to this, and the capacitance change reading type disk having a tracking guide groove is explained. The present invention can also be applied to disks in which previously recorded signals are read by a light beam. In addition, the television receiver has R, G,
If it has three primary color signal input terminals of B, encoder 1
A matrix circuit is used instead of 01 to convert the luminance signal Y and color difference signals (RY), (B-Y) into three primary color signals R, G, B and supply them to the above input terminals separately. This allows the television receiver to display extremely high quality still images. Furthermore, the color difference values recorded on the disk 40 are (G-Y) and (R
-Y) or (B-Y); furthermore, the I signal, the Q signal 1, or the three primary color signals may of course be used.

As described above, the digital video signal recording method according to the present invention is based on the digital video signal of the first field and the digital video signal of the second field obtained by digital pulse modulation of one frame worth of analog video signal. The pixel data of the digital video signal of the second field (or the first field) is attenuated at a relatively large attenuation ratio and mixed with the pixel data of the digital video signal of the first field (or the second field), and the pixel data of the digital video signal of the first field (or the second field) is mixed. This third field digital video signal is recorded as a first field (or second field) digital video signal together with the second field (or first field) digital video signal on a recording medium. This makes it possible for this recording medium to be played back on a playback device that has a field memory as a memory circuit for storing digital video signals in the playback device, or even when played back in fast forward mode even on a playback device that has a frame memory. It is possible to play back a field image that is displayed as a field image in which the decrease in vertical resolution is reduced and jaggies are prevented, and a playback device that only has field memory can play back the digital video signal of the third field as is. By doing so, it is possible to eliminate the need for a circuit for vertical filtering, and in high-end playback devices with frame memory, the digital video signal of the played third field is transferred to the digital video signal of the played second field. (or the first field) can be used to restore and reproduce the original one-field (or second field) digital video signal, so in that case, the first and second field digital video signals It is possible to reproduce a high-quality reproduced image with no loss of high-frequency component information equivalent to when reproducing a video signal, and also
The field digital video signal is generated by multiplying the pixel data of the first and second fields to be displayed by three adjacent scanning lines by 1/2 or 1/4 and mixing them. The calculation is simple because it can be performed only by bit shifting, and furthermore, the pixel data of each scanning line of the third and second (or first) fields are recorded at approximately the same time at the same sampling point. , it has a number of features that make it easy to convert the number of scanning lines when it is reproduced.

[Brief explanation of drawings]

FIG. 1 is a block system diagram showing an embodiment of the main part of the method of the present invention, FIGS. 3(A) and 3(B) are diagrams showing other examples of frame images and field images, respectively. 5 is a diagram showing a signal format of one embodiment of the video signal section in FIG. 4, FIG. 6 is a diagram showing another example of the signal format of the video signal section, and FIG. 7 is a diagram showing another example of the signal format of the video signal section. FIG. 8 is a block diagram showing an embodiment of the main part; FIG. 8 is a diagram showing an example of the one-block signal format previously proposed by the applicant to which the method of the present invention can be applied; FIG. Figure 1 showing an example of the signal format of the control signal of
0 is a system diagram showing an example of the recording device in FIG. 7 proposed earlier by the present applicant, FIG. 11 is a block system diagram showing an example of the digital signal reproducing device, and FIG. 12 is a system diagram showing an example of the recording device in FIG. FIG. 13 is a partially enlarged perspective view showing an example of the sliding situation between the playback needle and the disc-shaped recording medium. FIG. 13 is a diagram for explaining an example of the conversion operation of the scanning line number conversion circuit. FIG. FIG. 2 is a block system diagram showing an example of the configuration of a memory and the like. 1... Video signal source, 2... TV synchronization signal generator,
3... Matrix circuit, 4, 5, 6, 35... AD
Converter, 9-11, 18... Memory, 15, 97...
・Switching circuit, 17...Header signal generator, 19...
・Digital recorder, 30-32...Analog audio signal input terminal, 36...Control signal generation circuit, 3
7... Signal processing circuit, 39... Recording device, 40...
- Disc-shaped recording medium (disc), 41... Laser light source, 42, 45, 47... Optical modulator, 74... Playback needle, 74a... Electrode, 76... Permanent magnet, 79...・
- Tracking servo circuit, 80...Pickup circuit, 83...Decoder, 84-86...Analog audio signal output terminal, 87...Scanning line number conversion circuit,
88... Switch circuit, 90... Control circuit, 91.
...Header signal detection circuit, 92...Memory write controller, 94, 95...Memory, 96...Memory read controller and synchronization signal generation circuit, 98-1
00...DA converter, 101...Encoder, 10
2... Analog video signal output terminal, 103, 104
...Auxiliary memory, 105...Address signal generation circuit, M11-M66...64kRAM, B1-B6...
・Choice switch.・ 2nd [21 Figure 3 (8) +Al ■Day-■ ■1-■ Figure 6 Figure 13 Figure 4121,, ``51 Figure 7 Be 8 Figure S Figure 9 Figure 10 Figure 1 page Continuing 0 shots Author: Mitsuo Kubo, 3-12 Moriyamachi, Kanayō-ku, Yokohama City, Japan Victor Co., Ltd. 0 authors: Yoshiaki Amano, 3-12 Moriyamachi, Kanayō-ku, Yokohama City, Japan Victor Co., Ltd. 0 authors: Kikuchi Inside Victor Co., Ltd., 3-12 Moriyamachi, Kanayō-ku, Hikari Yokohama City. Procedural Amendment May 16, 1980 Commissioner of the Japan Patent Office Kazuo Wakasugi 1.1 What number 1988 Patent Application No. 77875 No. 2, Name of the invention γ digital video signal recording method 3, Patent applicant address of the person making the amendment 3 Moriya-cho, Kanayō-ku, Yokohama-shi, Kanagawa Prefecture 221
12-chome Name (432) Victor Japan Co., Ltd. Representative Director and President Michi Shiji - Department 4, Agent 1゜Address 1.1 6, 5-7 Kojimachi, Chiyoda-ku, Tokyo 102, Supplementary 1-chome Detailed description of the invention in the subject specification. 7. Contents of correction (1) In the detailed calculation, page 52, lines 7 to 10 (j, "Storing pixel data group..." and the bottom 8 pi]-
111 minutes of pixel data group transmitted by IF is stored.'' (2) ``To explain,'' on page 53, line 10 of the same, has been amended as follows. However, for convenience of explanation, the playback digital video signal is directly supplied to the memory 94.95 without passing through the scanning line number conversion circuit 87, and thereby the PAI method or SE
A case of a playback device that plays back and outputs an analog color video signal conforming to the CAM system will be described. (3) Same, page 53, line 13, ``on the other hand'' and ``switch...''
Insert "from the first buffer" between ".". (4) Same, page 54, lines 9fj to 10 r M 1
6. M2G,..., and M44" to "M13~M41.M
14~M44, M+s~Mm and M16~
Correct it as M 44 J. (5) "Pixel data . . . after storage" in the 11th and 12th lines of page 54 is corrected as follows. [Pixel data Y2, Y3, (RY)o, (RY)@
The upper 6 bits of data are stored bit by bit and -C1
Writing of the first divided pixel data group (here, four luminance pixel data and two chrominance pixel data) of the first scanning line is completed. ” 6) On page 54, line 20 of the same page, [When the storage is finished, [1] is finished being stored. ” he corrected. ■ Insert "J from the second buffer candy" between "...6 bits" and rRAM..." in lines 4 and 5 of page 55. ■ Same, page 55 The "pixel data" on the 8th line of the page is corrected to "pixel data from the second buffer memory." (2) "Third scanning line...involved" on page 55, lines 16 to 20 is corrected as follows. Fortune-telling of 1° video signal section V3, Vs, -! The loading is performed in the same way, and the last pixel j-ta group of the 571st and 572nd scanning lines (285th and 286th scanning lines in the case of field feed) is stored in RAM addresses rFE45j and rFEB7J ()r. - r7EE for field feed
9J and r 7 F 5 [3,1'), and the interleaving of one frame (or one field) is completed. (10) Same as above, one line from page 56, line 17 to page 57, line 1 is read out.] is corrected as follows. , the above six pixel data of the same address are read out at the same time, and the address is incremented by 1 from r00001.In order to reproduce and output an analog video signal conforming to the NTSC system from the reproduced signal, a decoder is used. 831□::'・
When writing the digital video signal □ from the camera to the memory 94 or 95 after converting the number of scanning lines in the circuit 87, the writing operation to the memory circuit described in 1.
Since this is the same as the above explanation, the explanation will be omitted here. ” :1 111

Claims (3)

[Claims] (1) Of the digital video signal of the first field and the digital video signal of the second field obtained by digital pulse modulation of one frame worth of analog video signal, the digital video of the first field (or the second field) Attenuating and mixing the pixel data of the digital video signal of the second field (or the first field) with the pixel data of the signal at a relatively large attenuation ratio to generate the digital video signal of the third field; The digital video signal of the three fields is converted into the digital video signal of the first field (or the second field) and the digital video signal of the second field is
A digital video signal recording method characterized in that a digital video signal of a field (or a first field) is recorded on a compatible recording medium. (2) The digital video signal of the third field is the pixel data of the first field to be displayed on the 2n-1st (n is a natural number) scanning line from the top of the screen.
n-1, and the pixel data of the second field to be displayed on the 2nth scanning edge below it is L2n, then it will be displayed on the 2n+1st (or 2nth) scanning line from the top of one screen. The pixel data of the digital video signal of the third field is L2n/4+L2n+1/2+L2
n+2/4 (or L2n-1/4+L2n/2+L2n
2. The digital video signal recording method according to claim 1, wherein the digital video signal recording method is generated based on the formula: +1/4). (3) The pixel data of each scanning line of the third field and the pixel data of each scanning line of the second field (or first field) are pixel data at the same sampling point recorded at approximately the same time. A digital video signal recording system according to claim 1 or 2, characterized in that: