JPS58196721A - Field effect transistor circuit - Google Patents

Abstract

PURPOSE:To obtain a master-slave D flip-flop without any inverter, by using an R-S flip-flop which has R-S input terminals of a differential input type and a clock input and a reference voltage terminal of a differential input type. CONSTITUTION:The R-S input terminals 26 and 27 and the clock input terminal 24 and reference voltage input terminal 25 are of the differential input types, respectively, and one of differential inputs is connected to a fixed power source to allow operation by only one of S and R signals. Further, while a clock signal is inputted to the reference voltage terminal, a reference voltage is applied to the clock input signal terminal to perform the same operation without generating the inverted signal of the clock signal. For the constitution of the master-slave D flip-flop, this R-S flip-flop is connected in series and input signals to the clock input terminal and reference voltage input terminal of the front stage are supplied reversely to the rear stage.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect transistor circuit composed of field effect transistors (hereinafter referred to as MESFETs) with a Schottky junction as a gate, and in particular reduces the number of required inverters and An object of the present invention is to provide a synchronous master-slave D flip-flop that can realize high-speed and stable operation with a clock of

First, the conventional technology will be described. Figure 1 shows two R-
This figure shows a synchronous master/slave D/flip 70 block consisting of a 5-flip 70-tub. Referring to the drawing, the two R-S flip-flops 11 and 12 are master-slave flip-flops, and the inverter 13 is connected to the reset R terminal of the master flip-flop 11. do. Inba~
14 is the clock C of the slave flip-flop 12.
Connect to the terminal. Terminal 16 is the delay input terminal terminal 16
is a clock input terminal. Terminals 17 and 18 are respectively i
There are phase output terminals for l and +E phases.

In this circuit, the clock input terminal 16 is turned to "H" level, the input gates S and R of the master clip flop 11 are opened, and the signal level 7+n applied to the terminal 15 is output to the output terminal Q of the mask frisogage frog 11. appears at the output terminal Q, and at the same time its opposite phase level appears at the output terminal Q.

Next, when the clock input terminal 16 is set to the rLJ level, the input gates S and R of the mask flip-flop 11 are cut off, and the input gates S and R of the slave flip-flop 12 are opened. The signals at the output terminals Q and Q of the slave flip-flop 11 are read in. Due to this combination, the signal level of the terminal 15 previously applied appears at the output terminal 17 of the slave flip-flop 12, and the signal level is output from the output terminal 18.
, the reverse phase output of the output terminal 17 appears.

In this way, the signal at input terminal 16 is transmitted to input terminal 1.
6 is “H”, then the clock input terminal 1
When 6 becomes rLJ, it is output to output terminals 17 and 18. Therefore, this circuit is a synchronous master/slave/Da
Operates the Furinog clock.

However, in the circuit shown in FIG. 1, the inverter 13
This mask slave D flip-flop consumes less than the R-8 clip-flop.
Mind power and chip area increase.

Furthermore, the inverter 14 causes the clock input terminal 16 to
A signal with the opposite phase of the signal added to the inverter 14 is supplied to the slave flip 12, but the operation of the slave flip flip flop 12 is delayed from that of the master slave flip flop 11 by the signal propagation delay time of this inverter 14. Therefore, it is difficult to maintain normal operation in the high-speed operation of Uf (F). Therefore, the frequency divider composed of 9-knob flops cannot perform stable high-speed operation. .

Conventionally, in order to eliminate this clock delay, a method has been used in which the mask and slave flip are synchronized separately using a two-phase clock. However, in this method, the clock for driving the flip-flop is of two phases, and a special lock generation circuit is required, which results in a significant increase in power consumption and chip area.

SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks of the prior art, and aims to reduce the number of required inverters, thereby reducing power consumption and chip area;
The present invention provides a field effect transistor circuit capable of high-speed stable operation over a phase clock, especially a synchronous master-slave D flip-frog circuit.

Embodiments of the field effect transistor circuit according to the present invention will be described below with reference to the drawings. FIGS. 2 and 3 are field effect transistor circuits according to embodiments of the present invention. In FIG. 3, the R-8 flip-frog shown in FIG.
It is used as Fukufu 32. In FIG. 2, the terminal 21C1 is the ground terminal 21, and the terminal 22 is the power supply terminal. MESFETQ21. Q22 has its lease terminal commonly connected to the current source 23, and each gate terminal is connected to the terminal 24. It is assumed to be terminal 25. The terminal 24 is a one-clock input terminal, and the terminal 26 is a low voltage input terminal. M.E.
SFETQ23 has a drain terminal in common with MESFETQ24, and a source terminal is an MES whose drain terminal is commonly connected to the drain terminal of MESFETQ26.
Connect in common with the source terminal of FETQ26. terminal 26
．． 27 are respectively ft ME SF ET'i3. Q2
Reset with gate terminal 6.

This is a set input terminal. Resistor R21 is MESFET-
Q23. Q24 common load, resistor R22 is M
E S F E T Q 25 * Q2 is the common load of e.

The drain terminals of MESEFTQ2□ and Q28 are connected to the ground terminal 21, and the drains are grounded. MESFET-Q
Between the source terminal of 2□ and the power supply terminal 22, a diode D21. Current sources 28 are connected in series.

A diode D and a current source 29 are connected in series between the source terminal of the MESFET Q28 and the power supply terminal 22. MESFETQ24. The gate terminals of Q26 are each connected to a diode D22. Connect in common with the cathode terminal of D21. The terminals 210 and 211 are respectively IF phase and
This is a negative phase output terminal.

Next, the operation of this circuit will be explained. Now, in this circuit, when the clock input terminal 24 becomes a higher potential than the reference voltage input terminal 25, the MESFET Q21. Q22 are turned on (conducting) and off (blocking), respectively, and the reset input terminals 26. The set input terminal 27 is connected to MESFETQ23. It is possible to turn on either Q26. Next, when the clock input terminal 24 becomes a lower potential than the reference voltage terminal 25,
MESFETQ21. Q22 is off and on, respectively, ME SF E TQ24 to 25 *02□
, Q28 constitute a bistable element, and the aforementioned reset input terminal 26. The state specified by the set input terminal 27 is maintained as it is. This state is output from the output terminals 210 and 211VC.

MESFETQ2□, Q28 acts as an output buffer, and diodes D24. D22 is for adjusting the output level. In this way, the circuit in Fig. 2 is a synchronous type R-
8. Works as a flip-flop.

The circuit of FIG. 3 shows an embodiment of a single phase lock synchronous type mask slave D 7 lip-flop using the R-S flip-flop of FIG. Here R-8 Flip
Flops 31 and 32 are the flip-flops shown in FIG.
Diagnostic pressure (REF).

The terminals of 1E phase output Q and negative phase output Q are terminal 27, respectively.
．． 26. Corresponds to 24, 25, 210, 211. Terminal 33 is a clock input terminal, which is connected to the master 7 linop.
The C terminal of the flop 31 is further connected to the REF terminal of the slave flip-flop 32. The terminal 34 is a first reference voltage input terminal, which is connected to the REF terminal of the 1iff master Φ flimp float sensor 31 and further to the C terminal of the slave flip 70 tube 32. Terminal 36.
36 are a signal input terminal and a second reference voltage input terminal, respectively, and 2LF'ii are connected to the S and R terminals of the master 7 linop frog 31, respectively. Terminals 3A and 38 are positive phase and negative phase outputs, respectively.

Now, in this circuit, when the potential of the terminal 33 becomes higher than that of the terminal 34, the input gate S of the mask flip-flop 31,
R is opened and the signal at terminal 36 is compared with the voltage at terminal 36 and input. Next, when the terminal 33 becomes a lower potential than the terminal 34, the master flip clock frog 31
The input gate of Slave Flip Flora 132 is opened in its place, and the output terminal 37.3 is opened.
A signal appears at 8;/'.

C of flip number flops 31 and 32 used in this circuit,
The REF terminal and S and R terminals are both in a differential input relationship, and the input logic is determined by constantly comparing them.
If the other is fixed in a direct current manner as described above, operation is possible with only one phase signal. In this case, the clock need only be one phase, and there is no need to add an inverter to the input 'l'-43°R terminal of the master flip-flop 31, just connect the human input signal to the terminal 36. good. Therefore, in this circuit, a synchronous master slave D-flip 70 switch can be constructed using only two R-3° flip-flops without using an inverter, and the chip area and power consumption can be reduced. Furthermore, with a single-phase clock, the mask and slave flip-flops can be synchronized without delay, and accurate operation can be achieved even during high-speed operation.

It should be noted that the present invention is not limited to the above-mentioned embodiment, and the level shift diode D21. By connecting a plurality of D22 in series, even MESFETs with a large pinch-off voltage vP can be operated with +1T capability.

As shown in F above, the field effect transistor circuit of the present invention can reduce the number of inverters, thereby reducing the chip area and power consumption of the integrated circuit. High-speed operation of the circuit can be achieved.

[Brief explanation of drawings]

Figure 1 r1 is a circuit diagram of a conventional synchronous mask slave D flip-flop circuit, and Figure 2 is a circuit diagram of a conventional synchronous mask slave D flip flop circuit.
-A circuit diagram showing the S flip-flop circuit, FIG.
FIG. 2 is a circuit diagram showing a synchronous mask slave D 7 lip-70 circuit according to the present invention. 11.12, 31.32...R-3 Frisofu 70 tube, 13.14.0...Inverter, 15.3
5...Signal input terminal, 16, 24.33...
...Clock input terminal, 17, 18, 210° 211
．． 37.38... Output terminal, 21... Ground terminal, 22... Power terminal, 23.28.29
... ・Current source, 25, 34.36... Reference type press-fit J terminal, 26.27... Control input terminal,
Q21. Q22. Q23. Q24. Q2. , Q26...
......MESFET, R, R...Load resistance, D2. . . 21 22 D... Diode. 11 Name of agent Patent attorney Toshio Nakao and 1 other person 1st
51! Figure 2 I Figure 3

Claims (1)

[Claims] The first and second R-S are connected using a current switching type logic circuit in which the source terminals of two field effect transistors are connected in common and a current source is connected to the common source terminal.・Composes a flip 70 tube, and the first R-3 clip ・
The output of the first R-S slip-flop is connected to the cent input terminal of the second R-8 clip-flop, with the 70-ring as the first stage and the second R-S flip-flop as the second stage. Then, connect the inverted output of the first R-3 flip 70 tube to the reset input terminal of the second R-8 clip 70 tube, and connect the black 72111 to the first R-S a clock input terminal of the flip-flop and a reference voltage input terminal of the second R-S flip-flop;
3. Connect to the reference voltage input terminal of the flip fist 70 knob and the clock input terminal of the second R-8° flip frog. The second # lighting voltage was connected to the first R-8/slip/70 ring set terminal, and the input signal was connected to the set terminal r of the first R-8/flip 70 ring described in 11J. It is characterized by a military effect transistor circuit.