JPS58195335A - Data separating circuit - Google Patents

Abstract

PURPOSE:To attain a data separating circuit in which the margin of a setup time of data in latch input is large and no phase adjustment is required. CONSTITUTION:An enable pulse phi1 and a clock pulse CA are inputted to a latch circuit 25 and an output as shown in a figure 6 is obtained, a pulse phi2 and the clock pulse CA are inputted to a latch circuit 28 and an output (b) is obtained. A latch circuit 26 latches the output of the latch circuit 25 with the pulse phi2 and the CA. The timing of the output is shown in a figure 7. Latch circuits 27, 29 are operated with a clock pulse CB and the pulse phi2. When the pulse CB is inputted to an input terminal 23, the timing of the latch circuits 27, 29 is as shown in figures 10, 11. As mentioned above, it is used that the period of the change in the output data is double that of the pulse CB, and the setup time of data at the input of the latch circuits 27, 29 is increased more than that of conventional circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a data separation circuit Kll for separating encoded and time-division mixed data.

Seira's data *Circuit block diagram #! Figure 1 eζ, operation timing as a time chart [shown in Figure 2, 1
The purpose of the circuit in Figure 81 is to input data Al, Bl, A1,
Bl, A3, B' mammas, 112 figure (2)
It is to separate and output as shown in . First ts1
The signals input to the circuit shown in the figure will be described. Terminal IO is a data input terminal. As shown in Figure I82 CL, each element of A and 82 type-0 data is inputted to this ζ by being alternately mixed in time and minutes by sending gA@. A clock CA is inputted to the terminal 6, which indicates the timing at which the human input data is doubled. This is shown in Figure 182 (2) and is synchronized with the input data. Terminal 7 in FIG. 1 is the input terminal of the reset circuit 1tPj of the D#Ii7 rib flop circuit (hereinafter referred to as FF1 circuit), and terminal 8 is the input terminal of the clock CC for synchronizing the output data.

The operation of the circuit shown in Figure 1 will be explained with reference to Figures 11 and 182. The data shown in Figure I2 (1) is input to the terminal 10, and the reset (IIitPj) shown in Figure 2 (3) is input to the terminal 7. The outputs Q and Q of the FF circuit ill in Figure 81 are
I agree with 4) and (5). Output Q is launch route 3
1 output 4 is input to the latch circuit 2, respectively.

These outputs Q and Q are negative logic logic outputs, and are input by hand to these launch circuits 2 and 3 alternately. The outputs are shown in (7) of Fig. 2.These are generated by the one-shot multiplier circuit 13 of the output Q from the edge X- of the output Q shown in Fig. 2 (4). clock 11
゜From (al)) K in Fig. 2 of the CDC; Fl latch circuit, when latched at 4', the output shown in Fig. 2 (9) (revenge escape to the ring) is obtained. UU. 1o~yo
, 2 clock CC manually, 1 g of clock CC
By applying the output of 1w14.4' (Fig. 2 (9J14) to the latch circuit 5.5I by 7 nJ-, the output shown in Fig. 2) is obtained from terminal 11112 ((4 larel).

However, the conventional circuit described above has the following drawbacks.

(1), Since the data set-up time of the part skipped in 211ii2(6) (output of @1 ill's latte circuit 2) was shorter than the clock period, there was no margin for launch.

(2) Since the phase of the clock CD depends on the phase difference between the clocks C and CD, an all adjustment circuit is required, and the fireflies were also strange.

The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the conventional technology.The purpose of the present invention is to solve the following problems: The purpose of the present invention is to provide a sophisticated data separation circuit that does not require any data separation.

□.

The above object of the present invention is to output and output the #Il clock manual and reset manual gate latches 1ISilIl signals.
□■ The first latch control in @ki multiple launch - fairy tale 1 human power and control 41 clock λλ power and human power data launch lth latch 1g1M and second latch The output of the first launch circuit having a control signal and a first clock is input to the output of the first launch circuit.
A latch circuit with a latch circuit of 2, a latch control of IIN 2 and a clock of 12, and a launch of m article 2 (2)
The latch circuit of Tsumugi 3 which latches the output data of the circuit and outputs it to the output terminal of lI11, and the latch 1g1wI of 1114 which has the latch control signal human power of front +7@2 and the human power of the lth clock and latches the human power data. , AtIki lh2
A data separation device characterized in that it has a latch control signal of I5 and a launch circuit of I5 which has a latch control signal of III circuit #I2 and a latch circuit of I5 which launches the output of the latch circuit of 11tI log 4 and outputs it to the output terminal of Raku2. It consists of a circuit.

Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 113 is a block diagram showing an embodiment of the present invention, and FIG. 4 is an operation time chart of the circuit according to the present invention.

In FIG. 43, reference numbers 21, 22, 23, and 24 are input terminals, and 11 and 12 are output terminals. Also 25.26
．． 27, 28, 29 is Latte (ro) road, 30 is TF
A flip-flop circuit (hereinafter referred to as 11i''FIgl circuit) constituted by a D-type flip-flop is inserted.

First, the operation of the FF circuit of the 311!13 will be explained. A reset pulse h is input to the terminal 24, and the 4
Figure ta) As shown in ItC, it is accepted that the capital B of the human power data shown in Figure (1) is -4. Input the reset pulse P1 in the first step W11. The output of the FF-path 10 is shown as pHρ2 in the figure, and the output timings of these are shown in Figure 4 (4) for the output 1 and 41m (4) for the output p2.
These outputs χ1 and lB2, which are respectively received at the same time, are both applied to the latch 1 of @3- as negative logic enable pulses.
25, 26, 27.2g and 29, respectively.

Next, the overall operation will be explained. Terminal 21 of Sta diagram
is a data input terminal, and data A"%B"s A"%B"s A, B1, AL B3- as shown in the 4th btJ (1) is input here.
e-*e is input. In Figure 3, it is the latch circuits 25 and 28 that launch the input data. The latch circuit 25 has an enable pulse 01 shown in Figure 4 (4)K.
Then, by inputting the water clock pulse Ci to (2), (6
), and the output is 1111411 for footpath@ro28.
Enable pulse #2 (, a) shown in (6) of 111
Input the clock pulse CA shown in C111) to obtain the output shown in C111). The launch circuit 26v in FIG. 3 latches the output of the launch circuit 25 shown in (6) by the clock pulse C in FIG. The output of is 8
The timing is as shown in FIG. 4 (7). The launch circuit 27 in FIG. 3 outputs data to the output terminal 11, and the latch circuit w129 outputs data to the output terminal 12. The launch circuit n and 29 receive the clock pulse C input to the input terminal 23.
1 and the enable pulse action 2 shown in FIG. 4 (5). When the clock pulse Cj shown in Fig. 114 (9) is input to the input terminal path of Fig. 93, the output of the latch circuits w127 and 29 in the same figure is 41111!
The timing is shown in .

As above, the ring 4 diagram (Llj, OJ is 1g according to the present invention)
Although the timing of the output data of the l path is shown, the present invention
1, the output 1 - period 1 of the change in the evening - is shown in the same figure (-J), and the period 24'S a... is shown in the figure (-J). Figure latch circuit 27.290 input -
The data set-up time in the circuit is much longer than that of conventional circuits. In other words, as shown in Fig. 84 (2), clocks (Rus υ) synchronized with human data and clocks (Rus CB (!84
When the phase difference in Figure (9)) is d, the data set amplifier time S at the input of the aforementioned ratte is 5=2, where T is the jlI1 period of the clock pulse Cj shown in (9).
T- (given as i.-4 According to enable pulse play 2 shown in Figure (6)), S > T, and compared to 8 < T in the conventional circuit, the data set amplifier time is The leeway is increasing.

In the circuit of the present invention, for the clock pulse Ca shown in Fig. d, 11K4, the period T is equal to the clock pulse CA shown in (2), and the effective edge of the clock pulse is the enable I shown in (5) 4C. (Lus 12
However, in this range tC, depending on the phase of clock pulse Cj shown in Fig. 1 (9), Fig. 4114 (97% (41)% a
111c, synchronized with this, ε1. Riki Kiyama is obtained. This is the enable node (&) shown in Ia41.
Validity period of Ruth ρ2 In 1 Seki circle, 11K (7
), (1) is fixed. This is the effect of the circuit of the present invention.

An example of the present invention is a separation circuit for time/minute III mixed parallel data of three or more tanks. Now, if the time-division mixed data is on an electric bridge, the circuit output in Figure 30 of I3 is extended to bookbinding, and the manual terminal 21 and latch circuit 2
7 and between the λ capacitor 21 and the latch circuit 29, the number of latch circuits can be easily put into practice by adjusting the number of latch circuits required.

As explained above, in the present invention, when dividing data, the margin of the data cent-up time at the input of the latch is 4 larger than that of the conventional circuit, and the phase yI! This has the effect of eliminating the need for one circuit.

Although the present invention has been described above with respect to its favorable #Al1Il, it is merely an example, and it goes without saying that the present invention is not limited only by the *examples described here. .

[Brief explanation of the drawing]

Figure 182 is a block diagram of the circuit, Figure 182 is a time chart of the operation of the conventional circuit, Figure 182 is a block diagram of the circuit according to the present invention, and Figure 4 is a time chart of the operation of the present invention. . 1, 30. ,, 7 lips 70 tubes (glv1112.
3.4.4', 5.5', 25.26.27.28.2
9. ,,Latch path,13,,,z7 shiIRIJGQ
One-shot multi-biflator circuit patent applicant Representative of NEC Corporation Patent attorney Yutabe Kumagai (1) Jin Kaigo 4F31 82 B2 83
B3('2) 'C5 (1) Hekai 11zu A1 31 1
42 82 A3 B3 4 drawings

Claims (1)

[Claims] A circuit that has a 1111 pock input and reset input and outputs a plurality of site control II signals, a latch control signal input of @l among a plurality of launch control 141 signals of sII, and a clock input of #11 of itI. A launch circuit of m1ll that latches the input data, a latch circuit of Yuki 2 that has the latch control signal input of 182 and the clock power of @l and latches the output of the launch circuit of the 111I era, and +! IJ #I2 latch control signal input and 11!
A third latch circuit has a clock input of #2 and latches the output data of the latch circuit #182 and outputs it to the first output terminal, a latch control signal input of #J distribution 2, and a latch control signal input of #J distribution 1. t11 that has a clock input and latches manual data
i40yyf1gIWk and l! The runner control 9I11 of l1llkj 栴2 has the clock input of human power and the clock input of 2, and the output of the latch circuit of lll1kijuku 4 is latched to the second
A data separation circuit characterized by a lunch circuit of a cram school 5 that outputs to an output terminal of the circuit, and a circuit that commands the output terminal of the cram school 5.