JPS58193596A - Voice synthesizer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speech synthesis device, in which several parameters are extracted from the original f voice to make it standby,
HFII that synthesizes audio from those parameters is PA
ROOR-・----Partial Auto O
ar-r・14tlOn) type speech synthesis device 11
one target.

In the above-mentioned speech synthesis device, according to the bit allocation of each parameter at regular intervals (frames), data is requested from the ROM (read-only memory) K by the required number of bits, and the minute parameter is inserted into the next kKflll. emitted at iF'
go to

In this case, in order to smooth out the discrete changes in the image parameters when read one after another for each frame, the above-mentioned part is performed.

In the conventional inter-part method, the following 81&
Do the inter-departmental acts of l1. h 7t oHere, G is eyell111k and 69, P is lfl noodles, and R-na-
This is a girl whose form Ht has been changed by interpolation.

Ht − (G P) / g + F H * = (G He ) / 8 + li +
Ha = (GHs)/8+HsHa = (
GHs)/4 +HIHs = (G-H4)
/4+H4 ”m = (G Hi)/4 +H@Hy
=(G Ha )/2+H・Ha =(G
Hs)/1+H@=GUpper interpolation data, in order to form Hmaro, Hs, H4, H., the divisor is 7.6.5. And it must be 3 h or 8.4 KIF exchanged pseudo l [-] as mentioned above, so there was a drawback that it was quite distorted and large.

An object of the present invention is to provide a speech synthesis device 1* equipped with an interpolation circuit that has a relatively high degree of linearity.

Other objects of the invention will become apparent from the following description and figures.

Hereinafter, this invention will be explained in detail along with the ritual treatment.

Figure i@1 shows a block diagram of an overused RAROOR sound synthesizer according to the present invention.
Ru.

Each circuit block in the figure is formed on a single semiconductor board using known semiconductor integrated circuit technology.

This real-life speech synthesis device consists of a sound source section consisting of a noise source 1, a pulse train generator 1 and 2, and a digital filter 3.
D/MU converter4. It consists of a parameter interpolation circuit 5 and an interface 6.

The miscellaneous f source 1 is used to form unvoiced quantities such as (1, [θ]). The pulse train generation (b) path 2 generates a The pulse is formed according to the PI signal during the period.

When the micro combinator (not shown) is supplied with the starting address of the audio to be output from the K/V or the audio data ROM (not shown), the data (parameters) for each frame is sent from the ROM to the interface 6. In the parameter restoration (b) path of this interface 6, the bit data of each parameter is restored. and,#
(2) [5-1] Smoothing is performed for discrete changes in the above parameters. This interpolation circuit 5'
The pitch information passed through the LT is controlled by the sound source section, and the pitch and PAROOR coefficients are controlled by the digital filter 3. With this, the original voice is restored and synthesized, and the D/MU converter 4. Sound is generated via an external speaker.

FIG. 2 shows a block diagram of one embodiment of the above-mentioned intervening circuit 5. In FIG.

In the figure, what is indicated by the symbol F+ is the boundary [(
P or H) and the target salivary meeting, the difference of 7 [required reduction Jl[
This is an arithmetic circuit consisting of a 6+ path and a shift register that divides the above difference by 1/2n. In this example, shout Km! I
The difference depends on whether the shift register shifts the difference data te by 8 bits and performs division by 1/2'=1/256.

No. 66, the hydrogen bomb was inserted using a variable delay circuit.
In response to the above state-(P or H)t-, fl'! (This is to delay the time required for the removal by the shift register. This variable operation Ig circuit DI
Isn't it 11M?As shown in the implementation example in Figure 3, it is a D-type flip-flop D with 717t and 4 crotches in a tandem configuration. - LDIP4, and multiplexers MPX and K that receive the output signals and input signal M of each stage and selectively output them.

The shift tying in the arithmetic circuit F and the clock tying of the acid slip 70 DF or Dh are synchronized.

Once upon a time, this variable: IIa-1 road D- had a maximum of 4
(bit shift) (division by 1716).

The symbol Fl indicates the first calculation data of IllglMFt and the above town t.
]! l - J road Dt k passed tax value (P or H) and r
Add irises. The output data of this adder path IP is transmitted to two variable operation paths 11 of the upper device with a gradual configuration.
Through 1. It will be delayed. 7t or two variable j!
嬬19JIMrDa, D. can be modified to form a slow IJ#, time with a shift of up to 8 bits (17256@N)'*.

The symbol F, denoted by n, is an adder circuit that passes the second operation data of 8FH to the operation circuit 1 and the variable delay circuit DI, DI. Add t to the output data of (2).

And this addition circuit? The output data of glance is variable j! Through the extension circuit, time correction is performed, and the Okoseki data H
It is output by force. This interpolated data HFi is also used as a dust inventory for the next interpolation.

An explanation will be given according to the characteristic diagram of the erg4 diagram for obtaining interpolated data of this embodiment circuit.

The data of the previous frame P, the data 'kG' of the next 7 frames of L1, and the 16 interpolated data H1 to H+6(G) between them are determined as follows.

@Is the 11th interpolated data H. an arithmetic circuit? ,#/cte,
(G-P)/16 is formed, and P is added by the adder circuit PI. From this ttK, it can be obtained as H,=(GP)/16+P. At this time, the arithmetic circuit F- performs division by 1718, so the variable delay circuit requires 4 clocks to adjust the timeffjj! Currently 11P11 is late.

The first (second) interpolation data H1 is the blindness of interpolation or 1
/16 is accurate, so the addition is not performed in the nnXIp+ path FI and the addition circuit ? The output data of , or 7 is output as is. Specifically, it should be set as the 2i-th calculation data t-0 of the calculation circuit F1.

2 times − interpolated data Hm ri, (GH,)/15+
However, as mentioned above, with a shift register, it is not possible to form 1/2"L.

In this real IIrAN, the tributary circuit Fz11I-21Ql is used to simply perform division by 1/15.

In other words, in the tbth broom, division by 1/16 is performed in the same way as above, and the addition circuit? , at (G Ht)/16+H1t
- form. Then, in the second time, (G H+
)7256, line 1131 and add both Jl 1
9! % IF @ Te addition, Te, Hs = (G H
t)・(1/16+l/2 B B ) +H+. As a variable delay circuit, a delay operation of 8 clocks is performed in order to adjust the timing of the 8-bit shift required for the second (2) division (1/256).

+1/64.1/12#1/16+1/64.1/11
! ;1/l 8+1/32.1/1 o#tZ16+1
/32.

1/32.115ζl/6+1/1 ft, 1/3#
It is approximated as t/4+1/18.

In the above W7N calculation using the shift register, the electric power between the wheels is 1/2nK, and the time spent on division is different, so the variable delay circuits D1, DI, and DIKL are addition circuits? , , Fl's input-data is synchronized t.

In addition, the time correction t is applied to the Kaken delay a@ro D4 so that the Useki data H is outputted every foot cycle.

72: Previously, in this implementation fR circuit, it was possible to form interpolated data more approximated by [#l] using a relatively simple (b) path. In other words, by doing the interpolation weighting r as described above, li[-
Sex [Can be satisfied.

[Compared to the one used in conventional interpolation, the interspecies accuracy (directness) or the number 1
It is possible to achieve the same as above 1 of 0% or more, and it is possible to significantly improve the sound quality.

This invention is not added to the above embodiment f11.

In the real IIFA circuit shown in Fig. 2, the circuits D1 to D.

By using the adder circuit Fs, the IF/interrogation circuit, and sharing it in a time-sharing manner, the number of interpolations can be reduced to 0. is not limited to 2n, but can be any number.

Therefore, it can be made convenient for interpolation with variable frame length. That is, for a frame length n times the base time, ' / n , 1/n 1 r t/
This is because it is possible to interpolate n 2 , "-.

INDUSTRIAL APPLICATION This invention can be widely used for the speech synthesis apparatus 1 which handles the data 1 of the 1st spectral encoding system.

[Brief explanation of the drawing]

111 is a block diagram of a speech synthesis device commonly used in this invention, 2nd-1 is a block diagram showing one embodiment of the seventh Uranji, and 3rd is an embodiment of the variable delay circuit. 1 (2) indicating
FIG. 4 is a characteristic diagram for explaining the operation of the interpolation circuit. l...Noise source, 2...Pulse train generation circuit, 3...
Digital filter, 4...D/mu converter, 5...
Interpolation circuit, 6...interface. Figure 1 Figure 2 Figure 4, -! -4iyu, Jヱ, 5 years old//2//lif'〆j2

Claims (1)

[Claims] After receiving the ali&T and the old elutriation 0, the difference 'kl/ between the two is calculated.
The first arithmetic circuit that divides by 2n and the above first operation 1! A first variable delay rC1l path that delays the first operation of the circuit by a clock period of 11, and a first performance output of the first calculation circuit and the first variable delay (b) path. and a second arithmetic circuit which receives the output of the above-mentioned arithmetic circuit II2 and adds the two together; 2
The second operation is delayed by the clock period written in the second operation.
a variable delay circuit, a third arithmetic circuit that performs tmx on both the 1s2 (b)th arithmetic output of the first arithmetic-1 path and the output of the second variable Igl path; , an inter-part circuitry for forming inter-part data based on the third calculation output;