JPS5819167B2 - DC charge compensation method of charge transfer type transversal filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input weighted charge transfer type transversal filter, and includes DC charge compensation of the charge transfer type transversal filter in order to always keep the DC charge of each input stage of a charge transfer element constant. As is well known, charge transfer devices (hereinafter referred to as CTD) such as charge-coupled devices (hereinafter referred to as CCD) and bucket brigade devices (hereinafter referred to as BBD)
) can be applied to transversal filters using its delay function.

Recently, input signals that have been branched into multiple parts are weighted using predetermined coefficients, and then added using a CTD.
Transversal filters with high integration and excellent frequency characteristics have been developed by sequentially repeating delays.

This is called an input weighted charge transfer type transversal filter, and since the input signal is delayed and added at each stage, the DC component of the input signal is also added, and as it approaches the output stage, the added DC component This method has the drawback of increasing the area of the transfer electrode to accommodate the signal, and further has the drawback that the relative signal detection sensitivity at the output stage of the CTD decreases because the DC component relative to the signal increases.

The present invention has been made in view of the above points, and provides an input weighting type charge transfer type transversal filter including: 1. By injecting a predetermined DC charge from the front stage of the charge transfer section, and injecting a predetermined DC charge and signal charge from each stage other than the front stage, and letting the predetermined DC charge flow out, the degree of integration and signal detection sensitivity can be improved. An object of the present invention is to provide a DC charge compensation method for a charge transfer type transversal filter that can improve the performance of the charge transfer type transversal filter.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the DC charge compensation method of a charge transfer type transversal filter according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the present invention.

In the figure, reference numeral 1 denotes a charge transfer means, and at the forefront of the charge transfer means 1 there is provided a DC charge injection means 2 for injecting and covering DC charges.

Further, each stage of the charge transfer means 1 other than the first stage is provided with a pair of signal charge injection means 3a, 3a'.

3b, 3b', . . . 3d, 3d' are provided.

These signal charge injection means 3a, 3a', 3b,
3b/.

-3d, 3d' are terminals 4a, 4a', 4b,
4b'.

...The signal charges input through each of 4d and 4d' are
Terminal 5a J 5a/, sb t 5b', 5a
The charge is injected into the charge transfer means 1 after being weighted according to the control voltage input via j5d'.

First, each stage of the charge transfer means 1 other than the first stage includes the signal charge injection means 3a, 3a', 3b, 3b'.
, . . -3d, 3d', a set of charge draining means 5a, 5a' for draining charges corresponding to the DC component of the signal charges injected by each of them.

6bt6b', . . . 6d, 6d' are provided, and one set of charges in each stage is connected to terminals 7a, 7a/, 7b.
l 7b/.

. . 7dj7d', respectively, to the outside.

Further, the output stage of the charge transfer means 1 is provided with an output means 8 for detecting signals delayed, added or subtracted at each stage, and the signals detected here are outputted to the outside via a terminal 9. It is now possible to do so.

FIG. 2 is a schematic diagram for explaining the operating principle of the DC charge compensation method of the charge transfer type transversal filter configured as described above.

The operation will be explained below using FIG. 2.

As shown in the figure, DC charge Q■ is supplied from the DC charge injection means 2 to the signal charge injection means 3a t 3a', 3b t 3
Signal charge q from b', -3d, and 3a'.

(4) + i8 (4) t qO (4 - q8 (4') qO
(3) +”rs(3)tsu qO(3 pieces −qS(3 pieces) °” qO(t) Soil layer (1) FuqO(1')
QS(□'l are respectively injected into the charge transfer means 1, and the charge outflow means 6a, 6a't 6b t 6b/
,,・From 6d and 6d', DC charges q'o(4), q
o(4, qo(3).

q□(3/) ,...qO(1) j q'o(i'
) each has been leaked.

At this time, the following equation holds true.

Zheng-Q1+Σ((q□(k)+Q8(-Q'0(k))
−1 +Σ[(qo(k/l+q8(k/)=q′o(k/)
・・・・・・(1) k=1 Here, Q.

is the charge detected by the output means 8, and Q is the charge detected by the charge transfer means 1.
DC charges, QO(k) and q input at the front stage of.

(k/) is the DC component of the input charge of k and k'th stage, respectively, qS (k) and q8 (4 are the AC component of the input charge of k and k'th stage, respectively, q'0(k) and q′o(
k/) represent the DC charges drained at the k and k'th stages, respectively, and qs(h) and i.

Only (k/) has both positive and negative polarity. In equation (1) above, QO
(k) = q'0()c, qo(k = q'6(k/
), that is, when the DC component of the input charge and the outflow DC charge at the 'th stage are equal, 4 Q□ = QH+, 41 q3(k),! ,
``8tk re °°---(2) Therefore, the output charge Q.

is the result of sequential weighting of alternating current charges that swing positive and negative around the direct current charge Q injected from the front stage.

Therefore, as it approaches the output stage of the charge transfer means 1,
The phenomenon of increase in DC charge does not occur, and the capacitance under the transfer electrode of the charge transfer means 1 can be made the same in each stage.

Also, the DC charge Q input from the front stage of the charge transfer means 1
If the current is set to approximately 1/2 of the maximum amount of charge that can be accommodated under the transfer electrode, the input signal will also be (k), i, /l.
The widest dynamic range of the output charge Q for each can be achieved.

In the above equation (1), QO(k)\q'o(ic) j qO
(k＼q′o(When there are k, Q□ = QI X, E □ q′8(k) k′
Ibi□? i”stk+ε+εshi・(3),
Here, ε and ε′ are each ε=Σ[qo(k)−q′o(k)]...(4
a) k=1 ””'1/4 CqO1k') Q'O(k'))
(4b) where ε and ε' are the DC component q of the input charge.

(k). qo(k/) and the drained DC charge q'0(k
) j represents the cumulative deviation from Q'0(k').

Therefore, in this case, q. (k)” q'0(k)
t (101s=q'oac'), the dynamic range is narrower.

FIG. 3 is a plan view specifically showing the block diagram shown in FIG. 1, in which a potential balance method is used as the charge injection means, a single-phase drive type CCD is used as the charge transfer means, and a floating diffusion amplifier is used as the output mode. A case in which it is used will be explained.

In Fig. 3, 10 is a single-phase drive type CCD, and 11 is a CCD.
DC charge injection means provided at the forefront of 10, 12a,
12a't12b.

12b', . . . 12d, 12d' are each CCDI O
Signal charge injection means 13a provided in pairs in each stage of
.

13a', 13b, 13b', -13d, 13
ct' is a DC charge draining means provided in pairs in each stage of the CCDIO, and 14 is an output means provided at the output stage of the CCDIO.

The DC charge injection means 11 includes a source region 15, a first gate electrode 16 provided successively adjacent to the source region 15,
It is composed of a second gate electrode 17 and a third electrode 18, and predetermined DC via sum pressures (1) and (2) are applied to the first gate electrode 16 and the second gate electrode 17, respectively.

And the above bias voltage for both streams V ■ Each G-
The setting is such that approximately 1/2 of the maximum amount of charge that can be accommodated under the transfer electrode of the 1st G-2 CCD 10, which will be described later, is injected into the CCD 10.

Further, the source region 15 and the third gate electrode 18 are supplied with a pulse φ
8. φ.

-3 each are given.

Signal charge injection means 12a t 12a'> 12b y 12b', - provided in pairs at each stage of the CCD 10.
. . 12d, 12d' are source regions 19'a, 19a'j 19, similar to the charge injection means 11, respectively.
bt19b't...19d, 19d', a first gate electrode 20a provided adjacent to the source region,
20a'.

20bj20b'j...20dj20d', and second gate electrodes 21a, 21a'+21b, 2ib', .2 provided adjacent to the first gate electrode.
1d.

21d', and a third gate electrode 22a, 22a', 22bt22 provided adjacent to the second gate electrode.
b′,...22d? 22d/each.

and the source regions 19a, 19a'. 19b, 19
b',...19 (L19d' are each given a pulse φ8 in parallel, and one first gate electrode 20a, 20b
j...20d, a signal in which the input signal ν is biased with a DC voltage ■ is applied to the other first gate electrodes 20a', 20b',...20d.
A signal obtained by biasing the inverted input signal ν and the DC voltage ①8 is applied to ``.

One second gate electrode 21a+21b>・"21d has control voltages h4 (g), Vh3 (1), Vh2 (g),
vh law is given respectively, and the other second gate electrode 21a'
.

2 l b', -21d' is the control voltage Vh4 (-)
, Vh3(-).

Vh2H and Vhl(-) are each given.

Further, the third gate electrodes 22a, 22a'j 22b
222b'? ...22dj22d' each receives a pulse φ in parallel.

-3 is given.

DC charge draining means 13a, 13a', 13b, 13b', provided in pairs at each stage of the CCD 10.
. . 13d, 13d' are each a fourth gate electrode 23a.

23a', 23b, 23b', 23ct, 23
a' and the fifth gate electrode 24a >24a', 2
4b.

24b', . . . 24d, 24d' respectively, and sixth gate electrodes 25a, 25a', 25b, 25b', . . . 25
d.

25d' and drain regions 26a, 26a', respectively.

26b, 26b', . . . 26d, 26d'.

- and fourth gate electrodes 23a, 23a'. 23b
, 23b', .
524bt...24d has control voltage ■h4 (1), V
h3 (g), Vh2 (a), and vh□(1) are respectively connected to the other set of fifth gate electrodes 24a'j 24b'j and 24d.
'j has control voltages Vh, Vh, Vh2
H, Vh□(-) 4(-) 3(-) are given to the sixth gate electrodes 25a, 25a'.

A pulse φ is applied in parallel to 25b, 25b', . . . 25d, 25d'.

−3 is given, and further drain regions 26a, 26a
A DC voltage VDD is applied in parallel to 't26bt26b't'''26d and 26d'.

The CCDI O has transfer electrodes (transfer electrodes) provided successively adjacent to each other for transferring the charges injected by the DC charge injection means 11 and the signal charge injection means 12a, 12a'.
phase electrodes) 273 to 30a, and the transfer electrodes 272 to 30
transfer electrodes 27b to 30b provided successively adjacent to each other for transferring charges transferred from the transfer electrode 30a on the side closer to the output stage and charges injected by the signal charge injection means 12b and 12b'; , the transfer electrode 27b~
Charge and signal charge injection means 12c are transferred from the transfer electrode 30b on the side closer to the output stage among the transfer electrodes 30b.

The transfer electrodes 27C to 30c provided adjacent to each other in order to transfer the charges injected by the transfer electrodes 120', and the charges transferred from the transfer electrode 30c which is closer to the output stage among the transfer electrodes 27c to 30c. Signal charge injection means 12
d, for transferring the charge injected by 12d',
It is composed of transfer electrodes 27d to 30d that are successively provided adjacent to each other.

The transfer electrodes 27a to 30a, 27b to 30b. 27c
~30c, 2'7d~30d, transfer electrode 28a~
The substrate corresponding to each of the transfer electrodes 28d and 30a to 30d (the narrower transfer electrode in FIG. 3) is preliminarily implanted with other transfer electrodes 27a to 27. by ion implantation or the like. d, 29a~
A potential lower than the potential formed below 29d is formed.

Further, transfer electrodes 272 to 27d. A clock pulse φ1 is applied to transfer electrodes 28a to 28d in parallel to 30a to 30c.
A DC voltage V2 is applied in parallel to 29a to 29d, and a pulse φ is applied to the transfer electrode 30d.

are given respectively. The output means 14 is the transfer electrode 30d.
a floating diffusion region 31 provided adjacent to;
MO8F connected to this floating diffusion region 31
Source follower amplifier 3 consisting of ET32 and resistor 33
4, a reset gate electrode 35 provided adjacent to the floating diffusion region 31, and a drain region 36 provided adjacent to the reset gate electrode 35.

A pulse φ□ is applied to the reset gate electrode 35, and a DC voltage ■DD is applied to the drain region 36.

In the above configuration, the DC charge injection means 11:
The third gate electrode 18 is closed during the period when charge is injected from the source region 15, and the third gate electrode 18 is opened during the period when charge injection from the source region 1 is stopped, and the second gate electrode 17 is closed. CC the charge accumulated below
The data is transferred to the transfer electrode 27a at the front stage of the DIO.

Further, signal charge injection means 12a, 12a', 12b
, 12b', "・12d, 12c+' CC from each
The operation when transferring signal charges to each of the transfer electrodes 27a to 27d of D10 is similar to that of the DC charge injection means 11 described above.

Also, DC charge draining means 13a, 13a'. 13b
, 13b', . . . 13d, 13d', the fourth gate electrodes 23a, 2
3a', 23b, 23b',...23d.

Fifth gate electrodes 24a, 248' pass under 23d'.

The charges temporarily accumulated under 24b, 24b', . . . 24d124d'
respective second gate electrodes 21a, 21a';

2ib', . . . 21dj is equal to the DC component of the charge temporarily accumulated under 21d'.

and fifth gate electrodes 24a, 24a', 24b, 24
The charge accumulated under b', -24d t 24d' is
Sixth gate electrode 25a.

25a't 25b, 25b', -25d, 25ct
'Pulse φ given to each.

-3 by opening each of the sixth gate electrodes, the drain regions 26a, 26a', 26b
, 26b't-26d + 26d', respectively.

The operation described above will be explained in more detail with reference to FIGS. 4 to 6, focusing on the mechanism of charge inflow and outflow.

Figure 4 shows the pulses φ, φ, used in Figure 3 above.
A timing diagram showing an example of φ and DC voltage V,
Figure 5 is a cross-sectional view taken along the line A-A' in Figure 3, together with the state of the potential formed under each electrode.
This figure is a cross-sectional view taken along line BB/ in FIG. 3, together with the state of the potential formed under each electrode.

At time 1=1 in FIGS. 5 and 6, the pulse φ8 is at a low level as shown in FIG.
Charge is injected into the second gate electrode 21a through the second gate electrode 21a.

At time 1=1, since the pulse φ8 is at a high level, charge injection from the source region 19a is stopped, and the charge accumulated under the second gate electrode 21a is transferred to the first gate electrode 2.
Charges at a potential lower than the potential below 0a are in the source region 19.
Return to a.

. On the other hand, as described above, the transfer electrodes 288 to 28d.

30a to 30d are set in advance to have a lower potential than other transfer electrodes due to ion implantation, etc. Therefore, charges are transferred in one direction (from left to right in the figure) using a single-phase clock pulse φ and a DC voltage ■2. ) can be transferred to 1.

At this time t=t2, the clock pulse φ 2 is at a high level, so charges are transferred from the previous transfer electrode (in this case, from the electrode 17) to the lower side of the transfer electrode 27a.

At time t=t3, pulse φ.

-3 is at a high level, the third gate electrode 22a opens, and among the charges accumulated under the second gate electrode 21a, charges at a lower potential than the potential under the third gate electrode 22a are transferred to the transfer electrode 27a. It will be transferred below.

At the same time, the sixth gate electrode 25a of the DC charge draining means 13a
opens, and among the charges accumulated under the fifth gate electrode 24a, charges at a potential lower than the potential under the sixth gate electrode 25a flow out to the drain region 26a.

At time t-t, pulse φ.

-3 becomes low level, and the third gate electrode 22a and the sixth
Both gate electrodes 25a are closed.

At time 1=1, the clock pulse φ becomes a low level, so the charge accumulated under the transfer electrode 27a is first transferred to the fifth gate electrode 24a via the fourth gate electrode 23a, and the potential under the fourth gate electrode 23a decreases. Charges at a lower potential are transferred to the transfer electrode 29a via the fourth gate electrode 23a, completing a series of operations.

Next, signal charge input means 12a, 12a', 12b.

12b', 12d, 12d/second gate electrode 2
1a.

21a', 21bt21b', 21ct, 21d'
The charge accumulated below is the control voltage Vhk (+) 7 Vh
The manner in which the gain is controlled by k(-> will be explained.

That is, the capacitance C formed under each pair of second gate electrodes
(Vhk) is C(Vh
k)=-Vhk ・・・・・・(5
) satisfies the relationship.

Here K is a constant. Therefore, the charges θsigH and θsig(-) accumulated in each pair of second gate electrodes are calculated as follows.
))=KVhk(+)(■o-vB) −KVhk(+νin ”'...(6)081g
(-)=C[Vhk(→])(Vo-(τin-■B))
=KVhk(-) (vo-vB) + Vhk←Biin (7).

Here, ■ indicates the third gate electrodes 22a, 22a'. 22b
, 22b', . . . 22d, 22d'.

Reset voltage determined by the high level value of -3, ■8 is the first
Gate electrodes 20a, 20a't20b.

The DC biases, ν, and ν of the signal voltages applied to 20b', . The formula is for an inversion cuff.

In either case, the input charge is a DC charge Vhk (V
-Vhk), the signal charge is gain controlled by Vhk -KVhk
ν, and KVhkν, only In
In is superimposed.

7a and 7b, 8a and 8b, 9a and 9b, a pair of second gate electrodes 21at21a' and 21b, respectively.

21b', ... 21d, 21d' is a characteristic diagram showing an example of the typical relationship between the control voltages Vhk (a) and Vhk (-) and the relationship between the control voltage and the signal charge at this time. be.

FIG. 7a shows a case where V h k (+) and V hk □ are in a complementary relationship.

That is, Vhk(-)=V1-Vhk(+)(V,
>Vc) (8) This is the case.

Here, Vo is a constant voltage, and Vo is a control voltage when signal charges are no longer injected, that is, a cutoff voltage.

Figure 7 is a characteristic diagram showing the relationship between control voltage and signal charge at this time, where the characteristic curve shown by a dashed-dotted line is for the input signal ν, the broken line is for the inverted input signal 'in, and the solid line is for the input signal ν. The characteristic curve shown by is the sum of these two, and at this time the linearity of Vhk versus θsig is the best.

FIG. 8a shows a case where Vhk(+) changes and Vhk(-) remains constant.

That is, Vhk (g) two variable vhk = v (v > v)...
...(9) (-) 2 2 0 is the case.

Here, (2) is a constant voltage, and Vo is a cutoff voltage.

Figure 8 shows the characteristic curves showing the relationship between control voltage and signal charge at this time.The characteristic curve shown by the dashed line is for the input signal ν, the broken line is for the inverted input signal V, and the solid line is the characteristic curve for the input signal ν. The characteristic curve shown is the sum of these two.

At this time, the linearity of Vhk versus θsig becomes slightly worse than in the above case.

FIG. 9a shows a case where either Vhk(1) or Vhk(-) is in a cutoff state.

That is, Vhk (+) = variable (Vhk (-) <
Vo) Vhk(-) = variable (Vhk(,,4) <
This is a case of the relationship V(3) .''(10).

Here ■. is the cutoff voltage.

Figure 9 is a characteristic diagram showing the relationship between control voltage and signal charge at this time, and the characteristic curve shown by the broken line in the upper right corner of the figure is the input signal ν,
The characteristic curve shown by the dashed-dotted line at the bottom left is for an inverted input signal.

At this time, a dead zone is created in the relationship between Vhk and θ5.

On the other hand, each pair of fifth gate voltages 24a temporarily accumulates DC charges flowing out from each stage of the CCD 10.

24a't 24b, 24b', -24d, 24d'
, whose area is the second gate electrode 21a, 21a', 21
b.

Control voltages Vhk(+) and Vhk(-) equal to 21b', . . . 21dt21ct' and corresponding to the control voltage applied to the second gate electrode are applied.

Furthermore, each pair of fourth gate electrodes 23a. 23a't 2
3b t 23b't, 23dt 23d', the first gate electrode 20a + 20a'? 20b, 20b
A voltage V8 equal to the DC bias of the signal voltage applied to 't...20d, 20d' is applied to each pair of sixth gate electrodes 25a, 25a', 25b.

25b', 25 ct, and 25d' are the third gate electrodes 22a.

22a't 22b, 22b'・22d, 22a
The same pulse φ as that given to '.

−3 is given.

Therefore, each pair of fifth gate electrodes 24a. 24a',
24b = 24b'...24d t Charge θ accumulated under 24d' and then discharged.

ul(i)' out(-) is respectively θoutl-)-C(Vhi, H) (vo-v8)=
KVhk(-)-)(VC-v,) ・・・・・・0
υθ.

ul(-)-〇[Vhk(-)](■o-■B)=KV
h, , (-) (Vo-VB) -・-・-(12), and this outflow charge is expressed as (6L (formula) and θ
.

It is equal to the DC type component of the input charge θsig(1)' s t g(-).

Therefore, regardless of the value of the control voltage hk, the charge transferred under each transfer electrode and reaching the output means 14 is a constant DC charge Q0 input from the front stage of the CCD 10 and a control voltage input from each stage. ■Signal charge weighted by hk -K
Only Vhkvln, KV, and kvi are superimposed.

Note that the present invention is not limited to the above-mentioned embodiments. For example, the case where a float ink diffusion amplifier is used as the output means of a single-phase drive type CCD 1 as the charge transfer means has been described; It may be a phase- and four-phase drive type CCD, or even a BBD.

Further, a diode cutoff type may be used as the charge injection means, and a floating gate amplifier may be used as the output means.

As described in detail above, according to the present invention, it is possible to provide a DC charge compensation system for a charge transfer type transversal filter that can improve the degree of integration and signal detection sensitivity.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the DC charge compensation method of the charge transfer type transversal filter of the present invention, FIG. 2 is a schematic diagram for explaining the operating principle of the above embodiment, and FIG. 3 is a plan view specifically showing the block diagram shown in FIG. 1, FIG. 4 is a timing chart of pulses used in FIG. 3, and FIG. 5 is a cross-sectional view taken along line AA' in FIG. 3. FIG. 6 is a diagram showing the potential state together with a sectional view taken along line BB' in FIG. 3, and FIG. FIGS. 8A and 8B are characteristic diagrams for explaining the above embodiment, and FIGS. 9A and 9B are characteristic diagrams for explaining the above embodiment. 1...Charge transfer means, 2...DC charge injection means, 3a-3d, 3a'-3d'...Signal charge injection means, 6a-6d, 6a'- 6d'...
... Charge draining means, 8... Output means, 10...
...Single-phase drive type CCD111...DC charge injection means, 12a-12dt12a'-12d'...
... Signal charge injection means, 13a to 13d. 13a' to 13d'...DC charge draining means, 1
4...Output means, 15, 19a to 19d, 19
a' to 19d'... Source region, 16.20a
~20a, 20a'~20d'...First gate electrode, 17, 21a~21dt21a'~
21 d'-=second gate electrode, 18.22a to 22d
, 22a' to 22d'...Third gate electrode, 2
3a to 23d, 23a' to 23d'... Fourth gate electrode, 24a to 24d, 24a' to 24d'...
...Fifth gate electrode, 25a to 25d. 25a' to 25d'...Sixth gate electrode, 26
a-26d, 26a'-26d'...Drain region, 27a-27d, 28ar28d, 29a-
29d, 30a to 30d...Transfer electrode, 31
...Floating diffusion region, 32...
・MOSFET, 33... Resistor, 34...
. . . Source follower amplifier, 35 . . . Reset gate electrode, 36 . . . - Drain region.

Claims (1)

[Scope of Claims] 1. Charge transfer means for delaying and adding signals; input means for weighting and inputting input signals with predetermined coefficients corresponding to each stage of the charge transfer means; In an input weighted charge transfer type transversal filter comprising means for detecting a summed signal, the input means is provided in two sets independently at each stage, and the input means independently injects a signal charge from each of the input means. In response to this, two sets of means for draining a predetermined DC charge are provided independently at each stage, so that the DC charge is drained independently from each stage, and a DC charge injection means is provided at the first stage of the charge transfer means. A DC charge compensation method for charge transfer type transversal filters that is characterized by injecting DC charges. 2. DC charge injection means 3 of the charge transfer type transversal filter according to claim 1, wherein an input signal is applied to one of the input means and an inverted input signal is applied to the other input means. The DC charge transfer type transversal filter according to claim 1, wherein the DC charge injected from the charge injection means is approximately 1/2 of the maximum amount of charge that can be accommodated in each stage of the charge transfer means. Charge compensation method. )4 The charge transfer type according to claim 1, wherein the charge flowing out from the DC charge draining means is approximately equal to the DC portion of the charge injected from the input means provided at each corresponding stage. DC charge compensation method for transversal filters. 5. The DC charge injection means includes a source region, a first gate electrode, a second gate electrode, and a third gate electrode following the source region, and a predetermined DC voltage is applied to the first gate electrode and the second gate electrode, The third gate electrode is closed while charge is being injected from the source region through under the first gate electrode and under the second gate electrode, and the third gate electrode is closed during a period when charge injection from the source region is stopped. When opened, the charge under the second gate electrode is transferred to under the transfer electrode of the charge transfer means, and each of the input means has a source region, a first gate electrode, a second gate electrode, and a third gate electrode. a biased input signal is applied to each one of the first gate electrodes, a biased inverted input signal is applied to each other of the first gate electrodes, and a predetermined voltage is applied to each second gate electrode. applying a control voltage to give a weighting coefficient of , closing the third gate electrode while charge is being injected from the source region;
During the period when charge injection from the source region is stopped, the third
The gate electrode is opened to transfer the charge under the second gate electrode to the transfer electrode of the charge transfer means, and the DC charge drain means is adjacent to at least two phase electrodes of each stage of the charge transfer means. The fourth gate electrode includes a fourth gate electrode, a fifth gate electrode, a sixth gate electrode, and a drain region, each of which has a DC bias of a signal voltage applied to each of the first gate electrodes. , and each fifth gate electrode has an area equal to that of the second gate electrode, and each of the fifth gate electrodes has an equal control voltage applied to each of the second gate electrodes corresponding to the control voltage applied to each of the second gate electrodes. A voltage is applied, and charges are transferred from under each of the two phase electrodes adjacent to each of the fourth gate electrodes to the side of the phase electrode closer to the input stage, passing under each of the fourth gate electrodes, and under each of the fifth gate electrodes. Each sixth gate is closed until the surplus charge temporarily accumulated under the fifth gate electrode of the lever is transferred under the phase electrode on the side closer to the output stage, and then the sixth gate is opened to transfer the charge under the fifth gate electrode. 2. A DC charge compensation system for a charge transfer type transversal filter according to claim 1, wherein charges accumulated in the charge transfer type transversal filter are made to flow out to each drain region.