JPS58191529A - Logical circuit - Google Patents

Abstract

PURPOSE:To attain high-density circuit integration and high speed, by combining nodes having a high and a low precharge potential suitably and turning off the logical block at the post-stage at the precharge. CONSTITUTION:When a precharge signal phip is a high potential Vcc and an inversion phip' is a low potential Vss (at precharge), nodes 31, 32 are precharged to the voltage Vcc and a node 21 is precharged to the voltage Vss. At the operation (signal phip set to the voltage Vss, signal phip' set to the voltage Vcc), when inputs 11, 12 are set to the voltage Vcc, transistors(TRs) T2, T3 are set and the node 31 is discharged into the voltage Vss. Thus, TRT42 is turned on and an output 21 goes to the voltage Vcc. Then, the desired logic is realized. Through the constitution like this, an output inverter which is required for domino C-MOS logical circuits is eliminated, and the high-density circuit integration, high speed and low power consumption are attained.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor LSI (large scale integrated circuit), particularly a logic LSI.
SI, Memo')-Relates to a logic circuit suitable for use in LSI.

[Technical background of the invention and its problems]

Conventionally, as an n-input logic gate having a clock input, Domino CMOS has been known by Murphy et al. of Bell Labs (15SCC81, Technical D.
igest P 230). For example, when configuring a logic diagram consisting of NAND circuits 1, 2 and OR circuit 3 as shown in FIG. 1, transistors TI to Tl1 as shown in FIG.
A circuit using 1 is used. The precharge signal φP in FIG. 2 is a signal with a waveform as shown in FIG.
The period (interval, q s , s e ) of the low potential side power supply VIIF+ (connection +++ J) is called the time of nori charging,
The period when φP is at the high potential side power supply Yec (section 37) is called the operating time. During the above precharging, the transistor Tl *
Since TS #713 turns on (conducts), node 3
1,32.20 is precharged to vec. It's a transistor T,,T,IT! - is off (blocked), so node 3 J, ;? 2.

This is because 20 is separated from Vsm in terms of direct current. It is assumed that inputs 11 to 14 are determined before the precharge period ends and the operation starts. When transitioning to the above operation, transistor T1 + T5
+ 'r1g is turned off and transistor T4 +
'rs l ”ill turns on. If.

If inputs 11 and 12 are both at "H" (high) level, transistors 'r, ,'rs are turned on, and node 31 is discharged and falls to the low potential side power supply level Vss.

Therefore, the output of the inverter consisting of transistor Tg + 716 becomes H#, and transistor T14 is
turn on. Therefore, node 20 is discharged and drops to VSS. With this, the output of the inverter composed of the transistors TITlTl1l becomes 'H', and the desired logic can be constructed.The same applies when the combinations of logic inputs are different.

In this way, the Domino CMO8 logic circuit has low power consumption because there is no DC path between the high potential side power supply Vec and the low potential side power supply V+s. Also, unlike the conventional CMO8 circuit, the number of transistors that make up the logic has been halved.

However, in Domino CMO8 logic circuits, an inverter consisting of transistors Ts*Ttoq or Tll l T12 % or transistors TI7*T's is essential. This is because if there is no output inverter such as i], the node 33. J 4 is''
becomes H#, turning on transistor TI41 T'ts. Assuming that the inputs 11 and 12 are H#, the node 33 must be at L'' (low) level during operation.However, at the moment when the input is switched to operation, the node 33 is H'', so the node 20 is discharged through the transistor T14. Resulting in. Next, even if the node 33 becomes ``L'', the node 20 remains discharged and becomes t''L#, resulting in a malfunction.

As described above, an output inverter is indispensable in the Domino CMO8 logic circuit, and this output inverter delays the signal and makes it difficult to achieve high integration density and low power consumption.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and aims to provide a logic Io circuit that can achieve higher integration density, higher speed, and lower power consumption than the conventional Domino CMO8 logic circuit.

[Summary of the invention]

In the present invention, the 2s type, which is a node with a high potential precharge potential and a node with a low potential, is appropriately combined, and during precharging, the logic block on the subsequent stage is turned off to prevent malfunctions of the logic block on the subsequent stage. That is.

[Embodiment J of the Invention An embodiment of the present invention will be described below with reference to the drawings. Fourth
Although the figure shows the same embodiment, since it is an example in which it corresponds to that in FIG. 2, corresponding parts are given the same reference numerals and explanations will be omitted, and the characteristic points will be explained. As shown, the transistor T! l T @ Good logic pro, ri, transistor 'r,,'r, good logic pro, ri are each NAND configuration, transistor T41 e
T4! A good logic program is Noah's configuration. The node 31 (output end) of the NAND circuit is connected to the transistor 14 (r-), and the node 32 (output end) of the other NAND circuit is connected to the dart of the transistor T41.

Assuming that the precharge signals φP and φP in the figure have waveforms as shown in FIG.
．． The node 32 is precharged to the high potential power supply voltage Vec by the transistors T1+T11, and the node 21 is precharged to the low potential power supply voltage Vss by the transistor T4m. Next, during operation, if the input 11.12 is Vcc, the transistor T ze T s is turned on.
Node 31 is discharged and becomes Via. Therefore, when the transistor T4 is turned on, the output 21 is increased to VCC. It can be seen that the desired logic is realized through this. The same applies when the input is in other states. That is, the circuit of FIG. 4 performs the same function as the circuit of FIG. 2.

Although FIG. 4 shows an example using a P-channel type transistor and an N-channel type transistor, the concept of the present invention is quite wide-ranging. Figure 5 shows the negative logic switch (Figure 5 (&)) and positive logic switch (Figure 5 (b)) - symbols used in the following explanation.What is a negative logic switch/positive logic switch? , control gate 101/
When applying a low potential to 104, both terminals 102.103/1
It is a logic switch that turns on/off between 05 and 106, and turns off/on when a high potential is applied. Output negative logic dart (Figure 6 (1)) and output positive logic ff-) (Figure 6
Figure (b)) is constructed using the above logical switches.

11~InnI! in Figure 6! '~In' are logical inputs, 01
+01' is the output. 1 e L'2 is a logic processor configured by combining one or more logic switches.The positive logic switch is realized using an N-channel transistor, and the negative logic switch is realized using a P-channel transistor. In this case, in order to prevent the output logic amplitude from decreasing due to the threshold value, it is preferable to configure the logic circuit L1 with only N-channel temperature transistors, and to configure the logic circuit L12 with only P-channel transistors. 51 in the figure.
．． 52 is a high resistance (low conductance) for leak replenishment. In addition, the part 4.53 indicated by the dashed line in the figure may be dangerous if output O1 and Vsm are short-circuited during precharging, or output 0
It can be omitted if the 7-layer and Vce are not short-circuited.

Further, the portions 51 and 52 indicated by two-dot chain lines may be omitted if the precharge potential is held for a sufficiently long time (until the logic operation propagates to the final stage logic dart).

When the logic processor L 1 s L'l satisfies the desired conditions during operation, the output is 0.0 in the case of FIG. 6(a). and Vm
If s is as shown in FIG. 6(b), the output is 0'll! : Constructed so that vCC is electrically connected. Once this input condition is satisfied, the output is 0! changes from Vec to Vs@, and the output θ' weight changes from Vss to Wee.

What is important is that by connecting the output of the output angle (positive) logic dart to the control gate of the negative (positive) logic switch included in the logic pro- gram of the next stage logic logic! The fact that the terminals can be kept non-conducting will eliminate the malfunctions that occur when there is no output inverter in the Domino CMO8.

According to the configuration described above, the conventional Domino CMO8 required (n+4) transistors to configure an n-input logic gate, whereas the logic circuit according to the present invention does not require an output inverter. Therefore, only (n+2) transistors are required. If all n inputs are connected to the output of the logic circuit according to the invention, the transistor aU
(n+1) pieces are sufficient. Therefore, the degree of integration increases. Furthermore, since no output impark is required, there is no signal delay in this inverter, resulting in high speed. Furthermore, in a logic dart with a fanout of 1, the output only needs to drive one gate of the next stage MOS (MOS) Runnostar, and it is necessary to drive one gate of the MOS (MOS) runnostar in the next stage.
S) Compared to the case where it is necessary to drive two darts of two transistors, high-speed operation is possible by the reduction in output capacitance. Furthermore, since there is no output inverter, there is no need for the corresponding power consumption, and even lower power consumption can be achieved. Furthermore, in the conventional Domino CMO8, negative logic r-to (for example, NOT) is used.

Since it cannot create NAND, NOR), it is not complete as a logic system. By the way, the transistors T, ~T in Figure 2
4 1 Toe Tto is an AND circuit, and transistors Tts to T'+s are OR circuits. However, in the logic circuit according to the present invention, negative logic darts can be easily formed, which increases the degree of freedom in design.In addition, in the circuit according to the present invention, unlike the Domino CMO8, the number of P-channel and N-channel transistors is approximately equal. , which is well suited to modern gate arrays.

7 and 8 show other embodiments of the present invention, in which logic circuits of NAND circuits 71, 72, NOR circuits 73, and OR circuits 74 are realized by transistors 76 to 9o according to the idea of the present invention. This is a book written by

Note that the present invention is not limited to the embodiments only, and can be applied in many ways. For example, in the present invention, the channel type of each transistor may be reversed in FIG. 4. In addition, in the present invention, for example, FIG.
In a), the connection between the output 01 and Vec may be made by using only the leakage replenishment resistor 51 and omitting the transistor T1, or in Figure 6 (b), the output o'1 and Vec may be connected.
It is also possible to use only the resistor 52 between them and omit the transistor Tag. Further, in the present invention, for example, the sixth
In figure (a) transistor T4.

Instead of Vs-, the signal φP may be supplied to the node 6, and in FIG. 6(b), the transistor 53, V
The signal φP may be supplied to the node 62 in place of ce.

〔Effect of the invention〕

As explained above, according to the present invention, the conventional Domino CMO
Higher integration density, higher speed, lower power consumption than S logic circuit,
A logic circuit that can be easily designed can be provided.

[Brief explanation of the drawing]

Figure 1 is a logic circuit diagram, Figure 2 shows the same circuit in Domino CMO8
Fig. 3 is a signal waveform diagram showing the operation of the circuit, Fig. 4 is a circuit diagram of an embodiment of the present invention, Fig. 5 is a diagram symbolizing the logic switch, Fig. 6 is a generalized configuration diagram showing an embodiment of the present invention, and FIGS. 7 and 8 are diagrams showing other embodiments of the present invention. FIG. 2 is a logic circuit diagram for explaining an embodiment of the present invention. T1-Ts, T41-T43...MOS transistor, si, sx...high resistance (low conductance), L
1 + L'l...Logic pro, ri, 21.31.
32゜01 m ()l, ... Output end (node), 6
1.62...Node/Applicant's agent Patent attorney Suzue Takehiko District 1 Figure 2 Figure 3 35 37 36 Figure 6 (a) (b) 1

Claims (5)

[Claims] (1) A positive logic switch that becomes conductive between both ends when a high potential is applied to the control gate, and a negative logic switch that becomes conductive between both ends when a low potential is applied to the control gate are collectively referred to as logic switches. Also called the first
The node is electrically connected to the high-potential side power supply during precharging, and during operation, it is disconnected from the high-potential side power supply regardless of the input, or the first logic circuit is electrically connected. a first precharge means connected to a high potential side power supply with a conductance smaller than the conductance of the first precharge means;
a first means for connecting a second node to an operating extra-low potential side power supply; and a logic block provided with a logic switch between the first node and the second node. , the logic gate having the first node as the output terminal is called an output negative logic gate, and the third node is electrically connected to the low potential side power supply during precharging and is connected to the input during operation. a second precharging means that is either directly disconnected from the low potential power source or connected to the low potential power source with a conductance smaller than the conductance when the second logic circuit is conductive; a second means for electrically connecting a fourth node to a high potential side power supply at the time of creation; and a logic switch provided between the third node and the fourth node. When a logic dart having pro and gate terminals and having the third node as an output terminal is called an output positive logic dart, it has both an output negative logic dart and an output positive logic dart, and an output p logic gate. It has a connection to connect the output to the control gate of the negative logic switch included in the logic r-) of the next stage logic date, or the output of the output positive logic r-) is connected to the logic block of the next stage logic dirt. A logic circuit characterized in that it has a connection connected to a control ff-) of a positive logic switch included in the logic circuit. (2) Claim 1, wherein the first logic block is composed of only positive (negative) logic switches, and the second logic block is composed of only negative (positive) logic switches. Logic circuit described in Section. (3) The positive logic switch is an N-channel type MOS transistor, and the negative logic switch is a P-channel type MO8)
3. The logic circuit according to claim 1, wherein the logic circuit is formed of a transistor. (4) The first precharge means is a P-channel type MO
8) A transistor, the second precharging means is composed of an N-channel type MO8) transistor, and the second means is simply connected to the fourth node and the high potential side cloth. The first means can be configured by simply connecting the second node and the low potential side power source, or by using a P-channel type MO8) transistor, or by connecting the first means to the second node and the low-potential side power source, or by using an N-channel type MO8) transistor.
8) The logic circuit according to claim 1, which is constructed using transistors. (5) A means arranged in parallel with the first precharge means to connect the potential side power supply and the first node with low conductance even during operation, or a low potential side power supply arranged in parallel with the second precharge means. 2. The logic circuit according to claim 1, further comprising means for connecting the first node and the third node with low conductance even during operation.