JPS5819117A - Overload protecting system - Google Patents

Overload protecting system

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Publication number
JPS5819117A
JPS5819117A JP11814981A JP11814981A JPS5819117A JP S5819117 A JPS5819117 A JP S5819117A JP 11814981 A JP11814981 A JP 11814981A JP 11814981 A JP11814981 A JP 11814981A JP S5819117 A JPS5819117 A JP S5819117A
Authority
JP
Japan
Prior art keywords
voltage
load current
load
current
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11814981A
Other languages
Japanese (ja)
Inventor
洋一 植木
福留 経興
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11814981A priority Critical patent/JPS5819117A/en
Publication of JPS5819117A publication Critical patent/JPS5819117A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は過負荷保一方式、%に直列制御形定竜圧NmK
hけ4遥負荷保農方式に関す。
[Detailed Description of the Invention] The present invention is an overload maintenance type, series control type constant tow pressure NmK.
Concerning the four-way load maintenance method.

館tstt直列制御形定電圧回路における従来ある過負
荷保鏝方式の一例を示す図である。11図において、電
gIABから供給される直流電圧Vは、定電圧−御11
cTLによ〕制御される直列111111m)ランジス
−Qlt介して安定化された後、負荷りに厘m電圧vL
jIPよび負荷電流!Lt供給する〕鍍負荷電流ILは
直列制御トランジスタQlおよび過電流検出用抵抗R1
を経由して流れることによ1、前記過電流検出用抵抗R
IK電圧降下V恥を生ゼしぬる。前記負荷電流!Lが規
準値以内の場合には、鋏電圧鋒下v1mは規準電fEV
 *以下に保たれ、トランジスタQ2は阻止領域に維持
され。
1 is a diagram showing an example of a conventional overload protection method in a series control type constant voltage circuit. In Figure 11, the DC voltage V supplied from the voltage gIAB is constant voltage - control 11
After being stabilized through the series 111111m) Rangis-Qlt controlled by the cTL, the voltage vL
jIP and load current! Lt is supplied] The load current IL is connected to the series control transistor Ql and the overcurrent detection resistor R1.
1, the overcurrent detection resistor R
IK voltage drop V is embarrassing. Said load current! When L is within the standard value, the scissor voltage V1m is the standard voltage fEV
* and transistor Q2 remains in the blocking region.

盲九正椙入力錫子に電圧降下Vllが入力され、反転入
力端子に規準電圧V、が入力される比較器ムlかも出力
電圧VA+は出力さ?Lなi。かへる状城で負荷電流1
.が規準値を越えて増加すると、ll1r記電圧降下V
組は増加し、トランジスタQ2を線形領域に導び自腹列
制御トランジスタQlのペース電流を制御す為ことによ
り、該直列制御トランジスタQlk流れる負荷tIL流
!Lは制限されり、史に前記電圧降下V組が規準電圧v
1を越えると、比験器ム1から出力電圧VAsが出力さ
れ、ダイオードDIおよび抵抗R4に介してトランジス
タ920ベースに、またダイオードD鵞および抵抗R8
1?t、てトランジスタQ3のベース(供給され、両ト
ランジスタQ2およびQ3’を廟卯領域に導び〈。その
結果直列制御トランジスタQlはjIwr状鯵とな9、
負荷電tit I Lが阻止され為。なお負荷電*Ig
、による過電流検出用抵抗R1に生ずる電圧降下V組は
Oと1khが、比較器ムlの正相入力端子電圧V+はコ
ンデンtelが出力電圧VA+により充電し終る迄、飽
和領域に在ろトランジスタ93によp充分低電圧に維持
される反転入力端子電圧V−より高電圧に保たれるので
、その間出力電圧Vム、は維持され、トランジスタQ2
およびQaは飽和領域に保たれ、直列制御トランジスタ
Ql)11 Rjll断状ii+’を持続する。コンデンサCIが充
電し終ると1比較器AIの正相入力端子電圧V+は反転
入力端子電圧V−を下回るので、出力電圧VAtは停止
し、トランジスタQ2およびQaは初期状11Kj!I
I、直列1tlJl11)ランジスタQICも負荷電f
iILが流れ始める。以上の過程は負荷りが過負荷状−
KToる隈り繰返えされ5.直列制御トランジスJQl
l大電力損失による破壊から保護する。
The voltage drop Vll is input to the blind input terminal, and the reference voltage V is input to the inverting input terminal of the comparator.The output voltage VA+ is output? L na i. The load current is 1 in a tilted state.
.. When increases beyond the standard value, the voltage drop V
The set increases to bring the transistor Q2 into the linear region and control the pace current of the self-regulating series control transistor Ql, thereby causing the series control transistor Qlk to flow through the load tIL current! L is limited, and historically the voltage drop V set is the reference voltage v
When it exceeds 1, the output voltage VAs is output from the comparator 1, and is applied to the base of the transistor 920 through the diode DI and the resistor R4, and also to the base of the transistor 920 through the diode DI and the resistor R8.
1? t, is supplied to the base of transistor Q3 (supplied) and leads both transistors Q2 and Q3' into the mausoleum region. As a result, the series control transistor Ql becomes jIwr-shaped 9,
Because the load voltage tit I L is blocked. Note that the load current *Ig
The voltage drop V caused in the overcurrent detection resistor R1 by , is O and 1kh, and the positive phase input terminal voltage V+ of the comparator M1 remains in the saturation region until the capacitor tel is charged by the output voltage VA+. Since the inverting input terminal voltage V- is maintained at a sufficiently low voltage by 93, the output voltage V is maintained during that time, and the transistor Q2
and Qa are kept in the saturation region, maintaining the series control transistor Ql) 11 Rjll cutoff ii+'. When the capacitor CI finishes charging, the positive phase input terminal voltage V+ of the first comparator AI becomes lower than the inverting input terminal voltage V-, so the output voltage VAt stops and the transistors Q2 and Qa are set to the initial state 11Kj! I
I, series 1tlJl11) The transistor QIC also has a load current f
iIL begins to flow. The above process is like an overload.
KToru is repeated 5. Series control transistor JQl
lProtects from destruction due to large power losses.

以上の過程における各N1IcIEtIPよび11流波
形は第8図に示される。
The waveforms of each N1IcIEtIP and 11th stream in the above process are shown in FIG.

以上説明から明らかな如く、従来ある過負荷保護方式に
おいては、負荷電流ILが過負荷により増加すゐと直ち
に比較4m!AIが作動し、コンデンtelの充電期間
負荷電流IL¥t311断する。従って現用負荷t−稼
動状態とした値、新たな負荷t−並列接続し友場合には
、新たな負荷に通常設けられて−る平滑用コンデンサに
瞬間流入する充電電流によって4、前述の如く負荷電流
!Lが暫時値断されること−なり、現用負荷の稼動に妨
Wt−与える。
As is clear from the above explanation, in the conventional overload protection system, the load current IL increases by 4 m! due to overload. AI is activated and the load current IL\t311 is cut off during the charging period of the capacitor tel. Therefore, the current load t - the value in the operating state, and the new load t - in the case of parallel connection, the charging current momentarily flows into the smoothing capacitor normally installed in the new load. Current! L is temporarily cut off, which disturbs the operation of the current load Wt.

本発明の目的は、前述の如き従来ある過負荷保護方式の
欠点を除去し、新たな負荷を増設すゐ際に生ずる尖頭電
流によp貴荷電tI!、tf!I断させぬ如き過負荷保
1方式の実現にある。
It is an object of the present invention to eliminate the drawbacks of the conventional overload protection methods as described above, and to eliminate the p precious charge tI! by the peak current generated when adding a new load. , tf! The aim is to realize an overload protection system that will not cause interruptions.

この目的は、直列制御形定電圧回路において、負荷電流
が規定値を越えたことを検出して該負荷it流を制限す
る手段と、該負荷電流が規定値を越えた状態が一定時間
継続したことを検出して該負荷電流を所定時間遮断する
手段とt設は為ことにより達成される。
The purpose of this is to provide a means for detecting that the load current exceeds a specified value in a series control type constant voltage circuit and restricting the load current, and a means for detecting that the load current exceeds the specified value for a certain period of time. The means for detecting this and cutting off the load current for a predetermined period of time, and the setting of t, can be achieved.

以下、本発明の一実施例を絹3図およびm4図によp説
明す番。第3図は本発明の一実施例による過負荷保護方
式を示す図であり、第4図は第1aiにシはす各種電圧
および電流波形金示す図である。なお全図を通じて、同
一符号は同一対象を示す。第3図の111図と異なる点
は、過(流検出用抵抗R1の電圧降下VllはI[接比
較器A1に正相入力端子電圧V+として供給せず、比較
器A2および抵抗R6,R7およびコンデンサC2から
構成され為積分回路を介して供給されることに在1゜I
IEIIlIにお−て、直列制御トランジスタQITh
よび過電流検出用抵抗Rut介して負荷LK供給され1
負荷電流!、が、新たな負荷の増設により、瞬時的に規
定at越えたとすゐ(第4図参照)。
Hereinafter, one embodiment of the present invention will be explained using Figures 3 and 4. FIG. 3 is a diagram showing an overload protection system according to an embodiment of the present invention, and FIG. 4 is a diagram showing various voltage and current waveforms shown in FIG. Note that the same reference numerals indicate the same objects throughout the figures. The difference from Fig. 111 in Fig. 3 is that the voltage drop Vll of the current detection resistor R1 is It consists of a capacitor C2 and is supplied via an integrating circuit.
In IEIIII, the series control transistor QITh
and the load LK is supplied via the overcurrent detection resistor Rut.
Load current! However, due to the addition of a new load, the specified value at is instantaneously exceeded (see Figure 4).

その結果、過電流検出用抵抗R1に生ずる電圧降下Vl
+も瞬時的には増加し、それ迄阻止領域に在唯たトラン
ジスタQ2t−襟形領斌に導びき、直列Mill)ラン
ジスタQ1のベース電流を制御することによ〕%該直列
制御トランジスタQlt−流れる負荷電流!Lt制隈さ
せる、また比較iA2の正相入力端子十に入力されゐ前
記電圧降下VB、が、反転入力端子−に入力される規準
電圧Vstl’1時越えること九より、比11WA2か
ら出力電圧VAIが出力され、前記積分回路により積分
されゐ。該積分回路の出力電圧は、ダイオードD3t−
介して、比較@A1の正相入力端子十に正相入力端子電
圧V十として入力されるが、抵抗R6,R7およびコン
デンサC2より定まる時定数は充分長く定められている
ので、該正相入力端子電圧Y十が比較器ム1の反転入力
端子−に入力される規準電圧ηを越える以前に、負荷電
流!Lは規準値以下に戻p1前記電圧降下VRtも規準
電圧v、を下回〕、比較器A2も出力電圧Vム象全停止
する。その結果比較器A1は用力電圧Vム、を出力する
ことは無く。
As a result, a voltage drop Vl occurs across the overcurrent detection resistor R1.
+ also increases instantaneously, leading to the transistor Q2t- which was previously in the blocking region, and by controlling the base current of the series transistor Q1, the series control transistor Qlt- Load current flows! Since the voltage drop VB, which is input to the positive phase input terminal 10 of the comparison iA2, exceeds the reference voltage Vstl'1 inputted to the inverting input terminal 9, the output voltage VAI is reduced from the ratio 11WA2. is output and integrated by the integration circuit. The output voltage of the integrating circuit is connected to the diode D3t-
The positive-phase input terminal voltage V0 is input to the positive-phase input terminal 0 of the comparison @A1 through the voltage V0, but since the time constant determined by the resistors R6 and R7 and the capacitor C2 is set to be sufficiently long, the positive-phase input Before the terminal voltage Y0 exceeds the reference voltage η input to the inverting input terminal - of the comparator M1, the load current! L returns to below the reference value p1, and the voltage drop VRt also falls below the reference voltage v), and the comparator A2 also completely stops the output voltage V. As a result, the comparator A1 does not output the utility voltage Vm.

第1図におけるが如くトランジスタQ2およびQlが飽
和領域に導かれぬので、1列制御トランジスタQlが負
荷電流Ix、tlSl]止することは無−0次に負荷り
が連u的に過負荷状態となつた場合には、直列制御トラ
ンジスタQlが負荷電流!Lt−制隈した状態で比較器
A2が出力電圧Vh*に出力し続ける。その結果、比較
器A1の正相入力端子電圧V÷は規準電圧Vat越えて
増加すゐので、比較IIAIFi第1図におけると同様
に出力電圧vAlt−出力し、コンデンサCIが充電さ
れる迄継続すゐ。
Since transistors Q2 and Ql are not brought into the saturation region as shown in FIG. In this case, the series control transistor Ql is the load current! Comparator A2 continues to output the output voltage Vh* in the Lt-limited state. As a result, the positive-phase input terminal voltage V÷ of the comparator A1 increases beyond the reference voltage Vat, so the comparison IIAIFi outputs an output voltage vAlt- as in FIG. 1 and continues until the capacitor CI is charged. Wow.

その間トランジスタQ2およびC3は飽和領域に導びか
れ、直列制御トランジスタQl#i層断状態と1k)負
荷電RILが阻止される。
Meanwhile, transistors Q2 and C3 are brought into the saturation region, and the series control transistor Ql#i is cut off and the load current RIL is blocked.

以上のlIi@から明らかな如く、本実施例によれば、
負荷電流!Lが新たな負荷の増般時等の如く瞬時的に規
準値を越える場合には、直列制御トランジスタQltj
負荷電R1t、 t−制限するのみで、過負荷状態が積
分回路の時定数から定まる一定時間以上継続しt場合に
、初めて負荷電流を遮断する口 なお、第3図および114図はあく迄本発明の一実施例
に過ぎず、過負荷保護方式の実現に幾多の変形が考慮さ
れるが、何れの場合にも本発明の効果は変らない。
As is clear from the above lIi@, according to this example,
Load current! If L instantaneously exceeds the standard value, such as when a new load is added, the series control transistor Qltj
By simply limiting the load current R1t, t, the load current is cut off only when the overload condition continues for a certain period of time determined from the time constant of the integrating circuit. This is only one embodiment of the invention, and many modifications may be considered to realize the overload protection system, but the effects of the invention remain the same in any case.

以上、本発明によれば、直列制御形定電圧回路にシいて
、一時的な過負荷に対しては負荷tmt−制限するのみ
で、不必要に負荷゛電流を遮断するととは無いので、現
用負荷の稼動状1IIt−損なうこと無く、新たな負荷
を増設することが可能となぁ。
As described above, according to the present invention, in response to a temporary overload, the series control type constant voltage circuit only limits the load tmt, and does not unnecessarily cut off the load current. It is possible to add new loads without damaging the operating status of the load.

【図面の簡単な説明】[Brief explanation of the drawing]

ts1図は直列制御形定電圧回路における従来ある過負
荷保護方式の一例を示す図、112図は第1図におけ為
各種電圧および電流波形を示す図、第3図は本発明の一
実施例によゐ過負荷保護方式を示す図、第4図は第3図
における各種電圧および電流波形を示す図である。 図において、Bは電源、Lは負荷、CTLは定電圧制御
部%Q1は直列制御トランジスタ、R1は過電流検出用
抵抗、A1およびA2は比較器、C2およびC3はトラ
ンジスタ、Dl、D2.DBおよびD4はダイオード、
CIおよびC2はコンデンサ、R2乃至R7は抵抗、V
およびvLは直流電圧、vl、は電圧降下、■+は正相
入力端子電圧、V−は反転入力端子電圧、VAIおよび
Vム雪は出力電圧、v目およびvlFi規準電圧、IL
は負荷電流、を示す。 代理人よ一壇士 松 岡 宏四り 第  1  図 第3図 Wk時通婁攬     連記1拘 第  2  図 第  4  図
Figure 112 is a diagram showing various voltage and current waveforms in Figure 1, and Figure 3 is an example of an embodiment of the present invention. FIG. 4 is a diagram showing various voltage and current waveforms in FIG. 3. In the figure, B is a power supply, L is a load, CTL is a constant voltage control unit, Q1 is a series control transistor, R1 is an overcurrent detection resistor, A1 and A2 are comparators, C2 and C3 are transistors, Dl, D2 . DB and D4 are diodes,
CI and C2 are capacitors, R2 to R7 are resistors, V
and vL are DC voltages, vl is voltage drop, ■+ is positive input terminal voltage, V- is inverting input terminal voltage, VAI and V are output voltages, vth and vlFi reference voltages, IL
indicates the load current. My representative, Hiroshi Matsuoka, 1st figure, 3rd figure, Wk Shitong Roubin, 1st arrest, 2nd figure, 4th figure.

Claims (1)

【特許請求の範囲】[Claims] 直列制御形定電圧回路において、負荷電流が規定値を越
JL危ことt検出して該負荷電流を制限す暴手段と、#
負荷電流が規定値を越えた状態が一定時閏11*したこ
とt検出して該負荷電流七所定時間總断する手段とt設
けることt%黴とする過負荷保■方式。
In a series control type constant voltage circuit, a means for detecting that a load current is in danger of exceeding a specified value and limiting the load current;
An overload protection system in which a means is provided for detecting that the load current exceeds a specified value for a predetermined period of time and interrupting the load current for a predetermined period of time.
JP11814981A 1981-07-28 1981-07-28 Overload protecting system Pending JPS5819117A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11814981A JPS5819117A (en) 1981-07-28 1981-07-28 Overload protecting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11814981A JPS5819117A (en) 1981-07-28 1981-07-28 Overload protecting system

Publications (1)

Publication Number Publication Date
JPS5819117A true JPS5819117A (en) 1983-02-04

Family

ID=14729291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11814981A Pending JPS5819117A (en) 1981-07-28 1981-07-28 Overload protecting system

Country Status (1)

Country Link
JP (1) JPS5819117A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61157217A (en) * 1984-12-21 1986-07-16 シーメンス、アクチエンゲゼルシヤフト Short circuit and overload monitor device
JPS63157216A (en) * 1986-12-22 1988-06-30 Nippon Electric Ind Co Ltd Power unit having selecting/breaking function for faulty load

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4422578Y1 (en) * 1966-01-31 1969-09-24

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4422578Y1 (en) * 1966-01-31 1969-09-24

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61157217A (en) * 1984-12-21 1986-07-16 シーメンス、アクチエンゲゼルシヤフト Short circuit and overload monitor device
JPS63157216A (en) * 1986-12-22 1988-06-30 Nippon Electric Ind Co Ltd Power unit having selecting/breaking function for faulty load

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