JPS63186532A - Control system of reactive power compensator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a control method for a reactive power compensator.

(Prior art) As a typical example of a static passive power compensator (hereinafter referred to as SvC), a thyristor phase control reactor type configuration is described in the fourth example.
As shown in the figure. The figure shows a case where 5VC2 is installed in the power system 1.

5VC2 is a main circuit section consisting of a capacitor 3 that conducts the leading current IC, an accelerator 4 that conducts the lag current, and a thyristor device 5 that controls the lag current IL, and a voltage transformer (PT) that detects the voltage of the power system 1. ) 6. Voltage detection circuit 7 which inputs the detected voltage of PT 6 and outputs DC voltage V proportional to the voltage of power system 1. Delayed current 1 due to DC voltage V
．． The control section includes a reactive power compensation control circuit 8 for controlling the thyristor device 5, and a phase control circuit 9 for controlling the firing angle α of the thyristor device 5 based on the output ITCR of the control circuit 8.

The advantage of SvC is that it can control reactive power quickly and continuously from the lead to the lag region, but the power system 1 fluctuates at a slow cycle even at all times, so it is difficult to control the reactive power with a slow cycle over a long period. It is efficient to use SvC to compensate for voltage and reactive power control devices widely installed in power systems and suppress voltage fluctuations with relatively short periods. To achieve this purpose, a control circuit 8 as shown in FIG. 5 has conventionally been used. 10 is a first-order delay circuit, 11 is a subtracter, and 12 is a transfer function, such as a proportional-integral circuit. The operation of the conventional control circuit will be briefly explained below.

System voltage ■ is detected by PT6 and voltage detection circuit 7,
It is input to the control circuit 8. In the control circuit 8, the reference system voltage (
(hereinafter referred to as Vref) is formed, and the system voltage V and Vre
The error voltage (hereinafter referred to as △V) which is the difference between f is the subtracter 12
It can be obtained with Reference numeral 12 denotes a transfer function circuit, which is mainly composed of an integrator and a proportional integrator, and outputs a reactive power amount Qsvc to be output from the SVC in response to an input of Δ■. In this way, SvC is controlled so that ΔV becomes zero, that is, equal to the system voltage V7)'Vref.

The relationship between the system voltage V, Vraf and ΔV is shown in Part 3 (a).

They are shown in figures (b) and (c), respectively.

The premise of this error voltage detection circuit is that the fluctuation range of relatively fast voltage fluctuations is small, and the fluctuation range of slow voltage fluctuations is large.

(Problems to be Solved by the Invention) However, when the grid voltage fluctuates rapidly and greatly as in the case of a grid fault, the prior art has the following drawbacks. For example, when a three-phase ground fault occurs and the circuit is restarted after the fault is removed, the system voltage will respond as shown in Figure 3(a).In contrast, Vraf, which is the output of the first-order delay circuit 10, will The response as shown in Fig. 3(b) is shown, and as a result, ΔV is the third (c
) It should be noted that even though the actual system voltage V is approximately near lpu as shown in part A of Fig. 3(a), ΔV is not as shown in Fig. 3(c). As shown in part 0, the output after re-closing is as if the system voltage is overvoltage.

As a result, even though the system II voltage is at a preferable value of about lpu, the SvC misidentifies it as an overvoltage and controls the system voltage toward an undervoltage. The cause of this problem is that the response of the first-order lag circuit 10 is slow, so the output Vref becomes slower than the actual movement of the system voltage V.

SUMMARY OF THE INVENTION An object of the present invention is to provide a control method for a reactive power compensator that eliminates voltage fluctuations that normally have a fast rate of change and that does not misidentify normal voltage as overvoltage even in the event of a system fault.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention, as shown in FIG. -DELAY circuit 15
and a first-order delay circuit 16 that changes the time constant according to the output of the OFF-DELAY circuit 15.

(Function) When the system voltage is not undervoltage, the time constant of the first-order lag circuit 16 is the same value as the conventional circuit, so Vref is the zero-order system a voltage formed by the first-order lag circuit 16 with a large time constant. When the voltage becomes an undervoltage, the output of the undervoltage detection circuit passes through the OFF-DELAY circuit 15 to reduce the time constant of the first-order delay circuit 16.

As a result, Vref, which is the output of the first-order delay circuit 16, follows sudden changes in the system with a small delay. Next, when the grid voltage returns to normal voltage from the undervoltage due to reclosing, etc., the output of the undervoltage detection circuit indicates that the grid voltage is normal voltage, but the OFF-DELAV circuit 15 operates as a first-order delay circuit for a predetermined time. Since the time constant of 16 remains small, Vref can also follow the rapid recovery of the grid voltage at the time of reconnection with a small delay. After the predetermined period of time has elapsed, the time constant of the first-order lag circuit returns to the value of the conventional circuit, and the SVC is controlled to remove relatively fast fluctuations in the system voltage fluctuations.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. Note that components having the same numbers as those used in the conventional example have the same functions. In Fig. 1, 13 is a setting device that serves as a criterion for determining undervoltage, and 14 is a comparator that outputs a logic level rOJ when the system voltage is higher than the value set in 13, that is, when it is a normal voltage, and when it is low, it outputs a logic level rOJ. That is, when there is an undervoltage, "1" is output. 15 is an OFF-DELAY circuit. When the input changes from "0" to "1", the output changes from "0" to "1" at the same time, and when the input changes from "1" to "0", the output changes from "0" to "1". r from "1" after a delay of a predetermined time ΔT
Changes to QJ.

16 is a first-order delay circuit that changes the time constant according to the OFF-DELAY circuit (0FF-+)ELAY circuit I circuit quantity 5. When the output of the OFF-DELAY circuit 15 is "0", the time constant is a large value as in the conventional circuit, and the OFF- The output of the DELAV circuit 15 is “
1, the time constant becomes small. The specific configuration of this first-order delay circuit 16 is shown in FIG. 2, where 17 is an operational amplifier, 18-1 and 18-2 are resistors, 19 is a capacitor,
20-1 and 20-2 are resistors whose value is 18-1.18-
For example, if it is □ compared to 2, the time constant of the first-order lag will also be -.

21-1.21-2 is OFF with a switch -DELAV
It is open when the output of the circuit 15 is "0" and closed when it is "1".

In other words, when the grid voltage is the normal voltage, the time constant of the first-order delay circuit 16 is determined by the resistor 18-1 and the capacitor 9, and is a sufficiently large time constant. The time constant of the delay circuit 16 is determined by the resistor 20-1 and the capacitor 19. In FIG. OFF because there is
The output of the -DELAV circuit 15 is also "0", so the switches 21-1, 21-2 remain open, so the time constant of the first-order lag circuit 16 is a large value as in the conventional circuit. Therefore, since the action of SvC is the same as that of the conventional circuit, a description thereof will be omitted.

Next, when the grid voltage becomes undervoltage, the grid voltage V and the value of the setting device 13 are compared by the comparator 14, and the output changes from "o" to "1", and then the OFF DELAV circuit 1
The output of 5 also changes from "0" to "1". OFF-D
When the output of the ELAY circuit 15 becomes "1", the switch 21
-1.21-2 is closed and the time constant of the first-order lag circuit 16 becomes small.

As a result, as shown in Fig. 3(a), even if the grid voltage rapidly drops during an accident, the time constant of the first-order delay circuit 16 is small, so as shown in Fig. 3(d), it can respond quickly to changes in the grid voltage. I will follow.

Next, when an accident occurs or when the circuit is reclosed, the system voltage V recovers to approximately the normal voltage as shown in FIG. 3(a).

At this time, the output of the comparator 14 changes from "1" to rOJ, but the output of the OFF-DELAY circuit 15 changes from "1" to "O" with a delay of a predetermined time, so the predetermined time Δ
During τ, the switches 21-1 and 21-2 remain closed and the time constant of the first-order lag circuit 16 remains small, so it follows the system voltage V quickly enough and Vref as shown in Figure 3(d). is output.

As a result, Δ■ is output as shown in FIG. 3(e).

Only a small and fast part of the change in the system voltage is output as ΔV, and SvC is controlled to remove this part.

In the above explanation, the undervoltage detection circuit and the first-order delay circuit were constructed using analog circuits, but these can also be replaced with a microcomputer.

〔Effect of the invention〕

By using the present invention, it is possible to provide a control method for a reactive power compensator that removes a voltage fluctuation component with a fast rate of change without misunderstanding a normal voltage as an overvoltage as in conventional circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a partially detailed block diagram of FIG. 1, FIG. 3 is a characteristic diagram for comparing and explaining the present invention and the prior art, and FIG. FIG. 4 is a block diagram showing an example of a configuration of a reactive power compensator, and FIG. 5 is a block diagram showing a conventional control circuit for the reactive power compensator. 13... Setting device, 14... Comparator, 15
...0FF-DELAY circuit, 16...First-order delay circuit with variable time constant. Agent Patent Attorney ff1J Ken Chika Hirofumi Mitsumata

Claims (1)

[Claims] A reactive power supply circuit that variably supplies reactive power to the grid, and a reference grid voltage formed by passing the grid voltage through a first-order lag circuit, and the difference between the grid voltage and the grid voltage are calculated. A method for controlling a reactive power device, comprising: an error voltage detection circuit for detecting; and a reactive power compensation control circuit for controlling the reactive power supply circuit so as to suppress the grid voltage fluctuation using a detection signal from the error voltage detection circuit. A method for controlling a reactive power compensator, characterized in that the time constant of the first-order lag circuit is made small until a predetermined time after the system voltage drops below a predetermined voltage and returns to above the predetermined voltage again.