JPS5930581Y2 - power protection circuit - Google Patents

Description

[Detailed explanation of the idea] The present invention relates to a power protection circuit.

Conventional power supplies have been protected using Zener diodes, which respond quickly to abnormal load voltages.

However, in the event of a failure such as a power supply punch-through, the fuse would not break even if a considerable amount of current were to flow, and the Zener diode therefore required a considerable amount of power capacity.

In addition, in power supply protection circuits using SCR, if the protection operation is made to respond quickly to abnormal voltages, the fuses will be cut frequently due to short-term noise or load fluctuations, and the response will be slow. If this was done, there was a risk that the load would be damaged if, for example, the power supply voltage became high in a pulsed manner.

This invention was made to eliminate the above-mentioned drawbacks,
It is an object of the present invention to provide a power supply protection circuit with a simple configuration without requiring a large power capacity control element.

According to one embodiment of the present invention, the above object is achieved by combining Zener diode-like operation and SCR-like operation.

The present invention will be explained in detail below using the drawings.

The figure is a circuit diagram of a power protection circuit according to an embodiment of the present invention.

In the figure, a fuse 13 serving as a current breaker for the power source 1L and a load 15 form a closed circuit.

Furthermore, a common connection point 11 between the fuse 13 and the load 15,
An abnormal voltage detector 21 is connected between the common terminal 19 and the common terminal 19 .

The detector 21 is composed of a resistor 23 connected in series, a parallel circuit of a Zener diode 25 and a capacitor 2γ, and a resistor 29 connected in series.

Abnormal voltage response circuit 3 whose common connection point 31 is the input terminal
3 is connected between the common connection point 11 and the common terminal 19,
The circuit 33 includes a transistor 35 whose collector and emitter are respectively connected to the common connection point 3L17, and the connection point 31. A transistor 35 includes a transistor 3γ having a base and an emitter connected to a common terminal 19, and a parallel circuit of a capacitor 39 and a resistor 41.
A resistor 43 is connected between the emitter and base of the transistor 35, and a resistor 43 is connected between the base of the transistor 35 and the collector of the transistor 37.

Further, the transistor 3γ is connected to the voltage controller 4 connected to the next stage.
Control 1.

Therefore, the transistor 35, the capacitor 39, and the resistor 4L43 form a charging/discharging circuit, and the transistor 31 forms a control circuit.

Next, a voltage limiter 47 whose input terminal is a common connection point 45 between the resistor 43 and the collector of the transistor 31 is connected to the connection point 1γ.
and the common terminal 19, and the limiter 4γ
includes a transistor 51 with a resistor 49 connected between the emitter and base, a transistor 53 with the collector of the transistor 51 connected, the base and collector connected to the emitter, and a diode between the base and emitter of the transistor 53. 55, and a resistor 57 is connected between the base of the transistor 51 and the common connection point 45.

The operation of the above configuration will be described.

In this circuit, the appropriate voltage supplied to the load is selected to be lower than the Zener voltage Vz of the Zener diode 25.

First, it is assumed that the voltage (1) of the power supply 11 becomes an abnormal voltage exceeding the Zener voltage Vz in the form of a narrow pulse.

Then, a current flows through the resistor 23 and the Zener diode 25, and a voltage is generated at the common connection point 31 in relation to the abnormal voltage.

Then, the transistor 37 of the abnormal voltage response circuit 33 becomes conductive, and both transistors 5L and 53 of the voltage limiter 4T become conductive, operating to lower the voltage V]7 at the common connection point 1γ.

This operation continues until the voltage V17 becomes lower than the Zener voltage Vz, so even if the power supply voltage (1) becomes an abnormal voltage, the voltage supplied to the load 15 is maintained at approximately the appropriate voltage.

However, such a Zener diode-like operation is limited to a case where the period of the abnormal voltage is shorter than the time τd until the transistor 35 becomes conductive due to the charging of the capacitor 39 due to the conduction of the transistor 3T.

Next, let's look at SCR-like operation.

It is assumed that the power supply 11 fails and abnormal voltage continues to be generated.

The operation to suppress abnormal voltage is the same as in the above case, but
Since the abnormal voltage period Tv is longer than the time τd until the transistor 35 becomes conductive, the transistor 35 becomes conductive, and once it becomes conductive, the abnormal voltage response circuit 33 operates via both transistors 35 and 37 and the resistor 43. continue.

Therefore, both transistors 5L and 53 of the voltage limiter 4γ remain conductive and the current continues to flow until the fuse 13 is blown.

Further, it is assumed that the voltage V l 7 is a single pulse and becomes an abnormal voltage continuously.

The abnormal voltage suppression operation is the same as described above, but it is assumed that the period Tv of a single pulse-like abnormal voltage is shorter than the above-mentioned period τd.

If you keep it, resistor 41 (1M, 2) to resistor 43 (10,
If the resistance value is made considerably larger than in case 2), the discharging time of the capacitor 39 will be considerably longer than the charging time.

Therefore, if the voltage V17 becomes an abnormal voltage continuously in a pulsed manner, the transistor 35 of the abnormal voltage response circuit 33 becomes conductive by the several pulses, and the subsequent SCR operation is the same as in the above case.

The diode 55 is for preventing a reverse voltage from being applied to the load, and in this case, the transistor 53 acts as if it were a reverse-connected transistor via the diode 55.

Further, the capacitor 27 is for speeding up.

Note that if SCR-like operation is not performed in response to a continuous pulse-like abnormal voltage, the discharge time of the capacitor 39 may be shortened by reducing the resistance of the resistor 41.

Further, the fuse 13 may be another non-returning breaker.

As detailed above, according to the present invention, a power protection circuit with a simple configuration can be realized without requiring a current control element having a large power capacity, and is extremely effective in practical use.

[Brief explanation of drawings]

The figure is a block diagram of a power protection circuit according to an embodiment of the present invention, in which 11: power supply, 13: fuse, 15: load, 21:
Abnormal voltage detector, 33: Abnormal voltage response circuit, 4γ: Voltage limiter.

Claims (1)

[Scope of utility model registration request] a current breaker connected between a power source and a load; and an abnormal voltage detection device connected to the output side of the current breaker, which generates a first output signal during an abnormal voltage period in which the voltage on the output side exceeds a predetermined pupil. a control circuit connected to the abnormal voltage detector and generating a second output signal; connected between the control circuit and the output side, charging and discharging in response to the second output signal; The control circuit consists of a charging/discharging circuit that generates a third output signal when the charging voltage reaches a constant level, and a voltage limiter that controls the voltage across the load in response to the second output signal. The circuit is the first and third
A power protection circuit that generates the second output signal in response to an output signal.