JP3319906B2 - Circuit breaker with open phase protection - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit breaker having an open-phase protection function for interrupting an electric circuit when an open-phase of a single-phase three-wire power supply phase is detected.

[0002]

2. Description of the Related Art Conventionally, in this type of circuit breaker having an open-phase protection function, a load voltage between a neutral line on a load side and each phase,
When the load voltage exceeds the reference voltage and the load voltage exceeds the reference voltage, the main contact inserted in the electric circuit is opened to shut off the power and protect the load. However, for example, the rated voltage of 15
When a 0% voltage and a 200% voltage are applied, the load is cut off in the same time, and the load is such as a recent home appliance equipped with a microcomputer and having a reduced overvoltage withstand voltage. However, there is a problem that the load cannot be sufficiently protected.

Accordingly, the present applicant has disclosed in Japanese Patent Laid-Open No. 5-2906 / 1993.
No. 85 is proposed. This device compares the load voltage between the neutral line on the load side and each phase with the reference voltage, and when the load voltage exceeds the reference voltage, charges the capacitor with a constant current and the capacitor voltage reaches a certain level or more The configuration has a configuration for delaying the output of the open phase detection signal up to this point.

[0004]

The above-mentioned JP-A-5-29
In the conventional example shown in Japanese Patent No. 0685, a delay time corresponding to the value of the voltage applied to the load at the time of phase loss is ensured to improve the protection performance, however, it is difficult to set the operation time. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a circuit breaker having an open-phase protection function having a plurality of detection stages and setting a delay time in each detection stage. To provide.

It is an object of the present invention to provide a circuit breaker having an open-phase protection function which more reliably protects a load in addition to the object of the present invention. A third object of the present invention is to provide a circuit breaker with an open-phase protection function in which the number of parts is reduced in addition to the objects of the first or second aspect of the present invention. The object of the invention of claim 4 is that, in addition to the object of the invention of claim 3, it is possible to immediately detect an open phase when the power is turned on again after the open phase is cut off, thereby protecting the load. An object of the present invention is to provide a circuit breaker with a phase protection function.

[0006]

In order to achieve the above object, according to the first aspect of the present invention, a load voltage between a neutral line on the load side and each phase is compared with a reference voltage, and the load voltage is set to a reference voltage. A detection circuit that detects a phase loss when the voltage exceeds the voltage, and when the detection circuit detects a phase loss, charges the capacitor with a constant current from the detection circuit and delays the output of the phase loss detection signal until the voltage of the capacitor reaches a certain level or more An open-phase detecting means having a delay circuit for turning on, a switch means to be turned on by an open-phase detection signal output from the open-phase detecting means, and a trip coil for a main contact excited by the switch means. In a circuit breaker with an open-phase protection function that opens a main contact inserted into an electric circuit by excitation of a trip coil, the open-phase detection means have different reference voltages and are disconnected when the load voltage becomes higher than the reference voltage. Detect phase That those having at least two detection circuits.

According to a second aspect of the present invention, in the first aspect of the present invention, when a load voltage equal to or higher than a reference voltage is detected in at least one of the detection circuits, a load is applied to the capacitor with a constant current from the detection circuit. It is provided with charging control means for flowing a current corresponding to the voltage. According to a third aspect of the present invention, in the first or second aspect, the delay circuit comprises:
The common capacitor is used for each detection circuit, and when each of the detection circuits detects a phase loss, the common capacitor is charged with a constant current corresponding to each.

[0008] In the invention of claim 4, the invention of claim 3 is provided.
The time required for the reference voltage of the detection circuit having the higher reference voltage to be increased at a constant rate from power-on until reaching a steady value is longer than the time required for the reference voltage of the other detection circuit to reach a steady value. It was slow.

[0009]

According to the first aspect of the present invention, the open phase detecting means has at least two detection circuits which have different reference voltages and detect the open phase when the load voltage becomes higher than the reference voltage. , A plurality of detection stages, and a delay time can be set in each detection stage.

According to a second aspect of the present invention, in the first aspect of the present invention, when a load voltage equal to or more than a predetermined voltage is detected in at least one of the detection circuits, the capacitor together with a constant current from the delay circuit is detected. Since charge control means for supplying a current according to the load voltage to the load is provided, when the load voltage becomes a predetermined voltage or more, the charging of the capacitor can be accelerated, and the load protection can be further ensured. .

According to the invention of claim 3, claim 1 or 2
In the present invention, the delay circuit charges a common capacitor with a constant current from each detection circuit when each detection circuit exceeds the respective reference voltage. Therefore, the delay circuit can be shared and the number of circuit components can be reduced. According to a fourth aspect of the present invention, in the third aspect of the present invention, the time from when the power supply is turned on to the time when the reference voltage of the detection circuit having the higher reference voltage is increased at a constant rate to reach a steady value is determined by the other detection circuit. Since the time required for the reference voltage of the circuit to reach the steady-state value is delayed, when the detection circuit with the higher reference voltage in the steady state is turned on, the other detection open circuit is disconnected earlier than the timing of detecting the open phase. Because it is possible to detect the phase, even if the power is turned on in the open phase state, the open phase can be detected immediately and the load can be protected immediately. The load protection can be ensured even when the power supply is re-input without removing.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.
I do. (Embodiment 1) FIG. 2 shows a basic circuit configuration of the present invention.
And each single-phase three-wire circuit L₁, L _TwoAnd neutral line N
Is the main contact S₁Are inserted respectively. Surrounded by a dashed line frame
The shaded portion indicates the neutral phase loss protection circuit.
Electric circuit L in the road₁, L_TwoIs full-wave rectified by diode DB
Input to the terminal of the open-phase detection circuit section A,
The detection line Ln from the neutral line N₁, L_TwoBetween
Connected resistor R₁, R _Two(= R₁) Connected to the partial pressure point
This partial pressure point is further added to the resistance R_ThreeOpen phase detection circuit section through
1 detection terminal.

When the power supply and the load are normally connected, a pulsating voltage having a uniform amplitude appears as the voltage at the detection terminal.
L ₁ phase, becomes the ripple voltage becomes large and small alternately by dividing ratio according to the load of the L ₂ phase, phase loss potential of the terminal is performed the open phase detected exceeds a predetermined level open-phase detecting circuit section A detection signal is outputted from an output terminal, in this open phase detection signal to turn on the thyristor SCR is switching means performs opening of the main contact S ₁ by passing the tripping exciting current to the coil CL, achieve load protection It is. ZNR
₁ are surge absorbing elements.

Here, the open phase detecting circuit section A in the present embodiment is configured as shown in FIG. That is, the terminal is connected to the input terminal of the constant voltage circuit 1, the terminal is connected to the ground,
The pulsating voltage from the diode bridge DB is converted into a constant DC voltage to obtain an operating power supply for each circuit of the phase loss detection circuit A.

The detection terminals are connected to the non-inverting terminals of the comparators 2a and 2b, respectively.
Reference voltages Vs ₁ and Vs ₂ applied to the inverting terminal of 2b
Is to be compared to. The comparators 2a and 2b form first and second detection circuits I and II together with the waveform shaping circuits 3a and 3b, respectively.
Appears pulsating voltage as shown (a), the comparator 2a or comparator when 2b becomes the reference voltage Vs ₁ or Vs ₂ or more, the comparator 2a or the period during detection output from 2b occurs.

The waveform shaping circuit 3a (or 3b) is configured as shown in FIG. 5, and the comparator 2a (or 2b)
Becomes the output is "H", the capacitor C ₁ (or C ₂₎ the charge of the discharge through the NOT gate, comparator 2a load voltage becomes equal to or lower than the reference voltage Vs ₁ or Vs ₂
When the output of (or 2b) becomes “L”, the capacitor C ₁ (or C ₂ ) is charged by the constant current source 20 as shown in FIG. 3 (b) or (c). The "L" output from the comparator 21 occurs when the voltage exceeds the threshold level Vth ₁ of the comparator 21 of the waveform shaping circuit 3a (or 3b) within (or Vth _2), hereinafter sometimes "H"
Output occurs. Where capacitor C ₁ (or C ₂ )
Is charged to the threshold level Vth ₁ (or Vth _1
2) at least AC power supply frequency of 3 cycles or more in excess, are set to be required to load voltage to continue the reference voltage Vs ₁ or Vs ₂ below.

The outputs of the waveform shaping circuits 3a and 3b are connected to delay circuits 4a and 4b, respectively.
a and 3b receiving the "H" output of the comparator 21 and the delay circuit 4
As shown in FIGS. 3D and 3E, a and 4b charge capacitors C ₃ and C _{4 provided} at a constant current, respectively. That is, as shown in FIG. 5, when the output of the comparator 21 becomes “H”, the delay circuit 4 a (or 4 b) charges the capacitor C ₃ (or C ₄ ) with a constant current by the constant current source 22. The voltages of the capacitors C ₃ and C ₄ are supplied to the comparators 5 a and 5 b, respectively, and the threshold levels Vth ₃ and Vth
₄ is adapted to be compared, and outputs a signal "H" from the comparator 5a, 5b when the threshold level Vth _3, Vth ₄ is the voltage of the capacitor C _3, C ₄ and withstand exceeded.

The outputs of the comparators 5a and 5b are connected to the OR gate 6.
Input to the output circuit 7 via the
When the outputs of the comparators 5a and 5b become "H", the open phase is detected.
The signal is output from the output terminal as shown in FIG.
You. Thus, in the present embodiment, the first and second detection circuits I,
II and the reference voltage Vs set in each₁,
Vs_TwoDelay circuits 4a and 4b
Capacitor C at_Three, C_FourTo start charging
And has a plurality of (two in the embodiment) detection stages, and
C of the delay circuits 4a and 4b corresponding to _Three, C_Four
The magnitude of the charging current or the capacitance of the capacitor
The second detection circuit on the side where the high reference voltage is set.
The delay circuit 4b corresponding to the road has a shorter time from the start of charging.
And the threshold level Vth_ThreeTo reach
You. Therefore, if the load voltage is high, the open-phase detection
Signal is generated and load protection can be achieved promptly.
If it is low, the time until the open phase detection signal is generated is long
To improve reliability by preventing transient operation, etc.
You.

FIG. 4 shows a protected area in this embodiment.
Yes, X₁Are the first detection circuits I and X _TwoIs the second detection circuit
The protected area of II is shown. (Embodiment 2) In the phase loss detection circuit section A of Embodiment 1 described above,
Delay circuits 4a and 4b are provided corresponding to the first and second detection circuits.
However, in the present embodiment, as shown in FIG.
4b is shared and one delay circuit 4 and comparator 5 are missing.
The phase detection signal is delayed to reduce the number of circuit components.
You.

That is, in this embodiment, the waveform shaping circuits 3a and 3
b outputs the delay circuit 4 receives with the adapted to charge the capacitor C _5, the first detecting circuit I side delay circuit as shown in FIG. 7 (d) receiving an output of the waveform shaping circuit 3a of 4 begins charging the capacitor C _5, then receives the output of the second detecting circuit II side of the waveform shaping circuit 3b when exceeding the detection level increases the charging current is to charge the capacitor C _5. In this case, the delay circuit 4 is provided with a constant current source 22 corresponding to each of the waveform shaping circuits 3a and 3b, and the currents are added.

[0021] When the receiving output of the second detecting circuit II side of the waveform shaping circuit 3b, increase in the charging voltage of the capacitor C ₅ is faster, the time until it exceeds the threshold level Vth ₅ of that amount comparator 5 As a result, the time until the output of the phase loss detection signal from the output circuit 7 shown in FIG. The operation of the first and second detection circuits I and II is the same as that of the first embodiment. FIG. 7A shows the voltage of the detection terminal and the reference voltages Vs ₁ and Vs ₁ of the comparators 2a and 2b.
7 (b) and 7 (c) show the relationship with Vs ₂ .
7B and 7C show waveforms of the operating states of the waveform shaping circuits 3a and 3b, respectively.

FIG. 8 shows a protected area in this embodiment.
Yes, X₁Are the first detection circuits I and X _TwoIs the second detection circuit
The protected area of II is shown. (Embodiment 3) The open phase detection circuit section A of the present embodiment is
In addition to the basic circuit configuration, as shown in FIG.
Voltage is reference voltage Vs₁Figure 1 performed when it becomes the above
0 (d) constant current I₁Of delay circuit 4a
Sensor C_ThreeIn addition to charging the battery,
Style I_TwoTo the capacitor C as shown in FIG._ThreeFlow
The voltage-current conversion circuit 8 for charging by charging the first detection circuit I
It is attached to.

[0023] That Zener diode DZ voltage to the Zener voltage of the same voltage as the reference voltage Vs ₁ of the comparator 2a in the present embodiment - when the load voltage is connected to the input side of the current converter circuit 8 exceeds a Zener voltage, the Zener current I ₂ corresponding to the magnitude of the voltage input via a diode DZ is to charge flowing to the delay circuit 4a capacitor C ₃ of, as shown in FIG. 10 (e).

Therefore, when the level of the load voltage shown in FIG. 10A increases, the charging current for charging the capacitor C ₃ increases correspondingly, and the voltage of the capacitor C ₃ shown in FIG. rise is earlier and reduces the time to reach the threshold level Vth ₃ comparators 2a. That is, the delay operation time can be varied according to the load voltage.

[0025] Note that operation of the second detection circuit II side is prepared analogously to Example 1, the charging voltage of the capacitor C ₄ of the delay circuit 4b shown in FIG. 10 (g) and the threshold level Vth ₄ in comparator 5b compares Is done. The outputs of the comparators 5a and 5b enter the output circuit 7 through the OR gate 6, and the output circuit 7 detects the open phase shown in FIG. 10 (h) when any of the outputs of the comparators 5a and 5b becomes "H". Output a signal.

FIGS. 10 (b) and 10 (c) correspond to FIGS.
7C shows the waveforms of the operating states of the waveform shaping circuits 3a and 3b, respectively, as in FIG. FIG. 11 shows a protection area in the present embodiment, where X ₁ is the first detection circuit I, and X ₂ is the second detection circuit.
3 shows a protection area of the detection circuit II. (Embodiment 4) An open-phase detection circuit portion A of this embodiment is obtained by adding the circuit configuration of Embodiment 3 to the circuit configuration of Embodiment 2 and FIG.
Voltage load voltage to charge flowing to the capacitor C ₅ of the reference voltage Vs ₁ or more when the became current shown in FIG. 13 (e) corresponding to the magnitude of the load voltage I ₂ a delay circuit 4 as shown in - It is provided with a current conversion circuit 8.

[0027] That the Zener diode DZ to Zener voltage of the same voltage as the reference voltage Vs ₁ of the comparator 2a in the present embodiment the voltage - the load voltage is connected to the input side of the current converter circuit 8 exceeds a Zener voltage, the Zener current I ₂ corresponding to the magnitude of the voltage input via a diode DZ is to charge flowing to the capacitor C ₅ of the delay circuit 4 as shown in FIG. 13 (e).

[0028] Thus, in addition to the waveform shaping circuit 3a, receives the output of the 3b to the capacitor C ₅ of the delay circuit 4 is a constant current I ₁ shown in FIG. 13 (d) are charged flows 13
Since the current I ₂ corresponding to the level of the load voltage illustrated in (a) charges the capacitor C _5, increase in the voltage of the capacitor C ₅ is faster shown in the-figures 13 (f), the threshold level of the comparator 5 time to reach the Vth ₅ is shortened. That is, the delay operation time can be varied according to the load voltage.

Since the operations of the first and second detection circuits I and II are in accordance with the first and second embodiments, the description of the configuration and operation is omitted. FIGS. 13B and 13C show the waveforms of the operating states of the waveform shaping circuits 3a and 3b, respectively, as in FIGS. 3B and 3C. FIG. Indicates a signal.

FIG. 14 shows a protected area in the present embodiment. X ₁ indicates a protected area of the second detection circuit I and X ₂ indicates a protected area of the second detection circuit II. The present embodiment configured as described above has both the features of the second embodiment and the features of the third embodiment. (Embodiment 5) The voltage-current conversion circuit 8 in Embodiment 3 is provided in the first detection circuit I, but in this embodiment, the voltage-current conversion circuit 8 is provided in the second detection circuit II as shown in FIG. It is. That is, in the present embodiment, the constant current I shown in FIG. 16D performed when the load voltage becomes equal to or higher than the reference voltage Vs ₂ .
In addition to charging of the capacitor C ₄ of the delay circuit 4b according to _1,
The current I ₂ corresponds to the magnitude of the reference voltage Vs ₂ or more load voltage flowing in the capacitor C _4, as shown in FIG. 16 (e) are to be charged.

[0031] That the Zener diode DZ 'to the Zener voltage of the same voltage as the reference voltage Vs ₂ of the comparator 2b in the present embodiment the voltage - the load voltage is connected to the input side of the current converter circuit 8 exceeds a Zener voltage is to charge by applying a current I ₂ corresponding to the magnitude of the voltage input through the Zener diode DZ 'to capacitor C ₄ of the delay circuit 4b as shown in FIG. 16 (e).

Therefore, the reference voltage Vs shown in FIG.
₂ or more and the load voltage is generated increases the charging current for charging the capacitor C ₄ in accordance with the load voltage, increase in the voltage of the capacitor C ₄ shown in FIG. 16 (g) is fast, the comparator 5
b time to reach the threshold level Vth ₄ of is shortened. That is, the delay operation time can be varied according to the load voltage.

It should be noted operation of the second detection circuit I side is prepared analogously to Example 1, the charging voltage of the capacitor C ₃ of the delay circuit 4a that shown in FIG. 16 (f) and the threshold level Vth ₃ the comparator 2a comparison Is done. The outputs of the comparators 5a and 5b enter the output circuit 7 through the OR gate 6, and the output circuit 7 detects the phase loss shown in FIG. 16 (h) when one of the outputs of the comparators 5a and 5b becomes "H". Output a signal.

FIGS. 16 (b) and 16 (c) correspond to FIGS.
7C shows the waveforms of the operating states of the waveform shaping circuits 3a and 3b, respectively, as in FIG. FIG. 17 shows a protection area in the present embodiment, where X ₁ is the first detection circuit I, and X ₂ is the second detection circuit.
3 shows a protection area of the detection circuit II. (Embodiment 6) The open phase detection circuit section A of this embodiment is obtained by adding the circuit configuration of the fifth embodiment to the circuit configuration of the second embodiment.
As shown in FIG. 19, when the load voltage becomes equal to or higher than the reference voltage Vs _2, the current I ₂ corresponding to the magnitude of the load voltage is
(E) it is shown so that the voltage charged by flowing in the capacitor C ₅ of the delay circuit 4 - is obtained by attaching a current converting circuit 8.

[0035] That the Zener diode DZ 'to the Zener voltage of the same voltage as the reference voltage Vs ₂ of the comparator 2b in the present embodiment the voltage - the load voltage is connected to the input side of the current converter circuit 8 exceeds a Zener voltage is to charge by applying a current I ₂ corresponding to the magnitude of the voltage input through the Zener diode DZ to the capacitor C ₅ of the delay circuit 4 as shown in FIG. 19 (e).

[0036] Accordingly, the waveform shaping circuit 3a, to receive the output of the 3b to the capacitor C ₅ of the delay circuit 4 is a constant current I ₁ also I ₃ shown in FIG. 19 (d) or (f) are charged flows since the addition current I ₂ corresponding to the reference voltage Vs ₂ or more load voltage shown in FIG. 19 (a) and charges the capacitor C _5,
Increase in the voltage of the capacitor C ₅ is faster shown in the-figures 19 (g), the threshold level Vth ₅ of comparator 5
The time it takes to reach That is, the delay operation time can be varied according to the load voltage.

Since the operations of the first and second detection circuits I and II are similar to those of the first and second embodiments, the description of the configuration and operation will be translated. FIGS. 19B and 19C show the waveforms of the operating states of the waveform shaping circuits 3a and 3b, respectively, as in FIGS. 3B and 3C. FIG. Indicates a signal.

FIG. 20 shows a protected area in the present embodiment. X ₁ indicates a protected area of the first detection circuit I and X ₂ indicates a protected area of the second detection circuit II. The present embodiment configured as described above has both the features of the second embodiment and the features of the fifth embodiment. (Embodiment 7) As shown in FIG. 21, a comparator 2c and a waveform shaping circuit 3 are provided in the configuration of the fifth embodiment.
A third detection circuit III composed of a c, a delay circuit 4c and a comparator 5c corresponding to the third detection circuit III are added, and a three-input OR gate 6 is used.

[0039] That comparator 2c of the third detection circuit III is the reference voltage Vs ₃ or more of the load voltage, as shown in FIG. 22 (a) generating a detection output to an input to the detection terminal. Corresponding waveform shaping circuit 3c performs in accordance with the detected output of the charge, discharge comparator 5c of the capacitor C _6, as shown in FIG. 22 (d), the threshold level Vth ₆ capacitor C
_When the voltage of ₆ does not exceed, the output is given to the delay circuit 4c. Delay circuit 4c charges the capacitor C ₇ at a constant current by receiving the output as shown in FIG. 22 (i). Comparator 5c is an OR gate the "H" signal when the voltage of the capacitor C ₇ exceeds the threshold level Vth ₇ 6
Is output to

That is, the operation of the third detection circuit III, the delay circuit 4c, and the comparator 5c are performed by the first and second detection circuits I,
It performs the same operation as II. When an "H" signal is output from any of the comparators 2a to 5c, the output circuit 7
Outputs an open phase detection signal as shown in FIG.
FIGS. 22 (b) and 22 (c) show the waveforms of the operating states of the waveform shaping circuits 3a and 3b, respectively, as in FIGS. 3 (b) and 3 (c).
2 (e) shows the constant current I ₁ flowing through the capacitor C ₄ of the delay circuit 4b corresponding to the output of the waveform shaping circuit 3b, FIG. 22
(F) a voltage - indicates current I ₂ flowing in the capacitor C ₄ by the current converting circuit 8, and FIG. 22 (g) (h) shows the respective delay circuits 4a, a capacitor C _3, the voltage of C ₄ to 4b.

According to the present embodiment, in addition to the features of the fifth embodiment, the number of detection steps is increased to three, thereby making it easier to set the operation time. FIG. 23 shows a protection area in the present embodiment, where X ₁ is the first detection circuit I, and X ₂ is the second detection circuit.
The detection circuit II, X ₃ represents a protecting region of the third detection circuit III. (Embodiment 9) The open-phase detection circuit section A of the present embodiment is different from the configuration of the embodiment 6 in that the comparator 2c and the waveform shaping circuit 3 as shown in FIG.
c, a third detection circuit III including a delay circuit 4c and a comparator 5c corresponding to the third detection circuit III.

The operation of the third detection circuit III is similar to that of the eighth embodiment.
The delay circuit 4 receiving the output of the waveform shaping circuit 3c of the third detection circuit III corresponds to the output of the waveform shaping circuits 3a and 3b of the first and second detection circuits I and II. In addition to the charging by the constant currents I ₁ and I ₂ shown in FIGS. 25E and 25F, and the charging by the current I ₃ by the voltage-current conversion circuit 8 shown in FIG. It was charged by constant current I ₄ shown in FIG. 25 accelerate the rise of the charging voltage of the capacitor C ₅ shown in (i), accelerating the time to exceed the threshold level Vth ₅ of comparator 5, FIG. 2
The delay time until the generation of an open phase detection signal output from the output circuit 7 shown in FIG.

FIG. 25 (a) shows the load voltage inputted to the detection terminal, and FIGS. 25 (b) and (c) show FIGS. 3 (b) and 3 (c).
25 shows the waveforms of the operating states of the waveform shaping circuits 3a and 3b, respectively, and FIG. 25D shows the waveforms of the operating states of the waveform shaping circuit 3c. This embodiment has both the features of the sixth embodiment and the features of the eighth embodiment. (Embodiment 10) The phase loss detection circuit section A of this embodiment is the same as that of the first embodiment.
26, a third detection circuit III composed of a comparator 2c and a waveform shaping circuit 3c, a delay circuit 4c and a comparator 5c corresponding to the third detection circuit III as shown in FIG. Things. The operation of the third detection circuit III is the same as that of the eighth embodiment, and the description thereof is omitted.

FIG. 27 (a) shows the load voltage input to the detection terminal, and FIGS. 27 (b) and (c) show the operating states of the waveform shaping circuits 3a and 3b, respectively, as in FIGS. 3 (b) and 3 (c). FIG. 29 (d) shows the waveform of the operation state of the waveform shaping circuit 3c, and FIGS. 27 (e), (f) and (g) show the delay circuit 5 respectively.
a, 5b and 5c denote capacitors C ₃ , C ₄ and C ₇ ,
FIG. 27H shows an open phase detection signal of the output circuit 7.

In this embodiment, the number of detection steps is three, and the protection area is as shown in FIG. It should be noted that X ₁ is the first
The detection circuit I, X ₂ of the second detection circuit II, X ₃ represents a protected area of the third detection circuit III. (Embodiment 11) The phase loss detection circuit section A of the present embodiment is different from that of the second embodiment.
As shown in FIG. 29, a third detection circuit III comprising a comparator 2c and a waveform shaping circuit 3c, a corresponding delay circuit 4c and a comparator 5c are added to the configuration shown in FIG. Things. In other words, Example 10
In this example, one delay circuit and one comparator behind it are used, and an OR gate is not required.

Since the operation of the third detection circuit III is the same as that of the eighth embodiment, its explanation is omitted. Thus, in this embodiment, the number of circuit components can be reduced as compared with the tenth embodiment. FIG. 30A shows the load voltage input to the detection terminal,
FIGS. 30B and 30C show the waveforms of the operating states of the waveform shaping circuits 3a and 3b, respectively, as in FIGS. 3B and 3C, and FIG. 30D shows the operating states of the waveform shaping circuit 3c. FIG. 30E shows a capacitor C of the delay circuit 5,
FIG. 30F shows an open phase detection signal of the output circuit 7.

(Embodiment 12) As shown in FIG. 31, the configuration of the open-phase detection circuit section A of this embodiment is different from that of Embodiment 2 in that the reference voltage at the steady state is the same as that of the comparator 2a of the detection circuit I at the steady state. 2b of the detection circuit II higher than the reference voltage Vs ₁
Then, the detection circuit I detects the time from when the power is turned on to when the reference voltage value is increased at a constant rate to reach the reference voltage Vs ₂ in the steady state.
It is slower than the rise of the reference voltage Vs ₁ of the comparator 2a for. Pressure specific to the terminal, the voltage, that is external to the resistor R ₁ to the voltage of the capacitor C ₀ which is connected as shown in FIG. 2 between the two terminals, R ₂ minute, the reference voltage Vs in the divided voltage _{This is} to get ₂ .

[0048] Thus the comparator reference voltage Vs ₁ of 2a of the main contact S ₁ is turned on is the detection circuit I power is supplied is rises immediately as shown in FIG. 32 (a), the detection circuit
Reference voltage Vs ₂ of II comparators 2a would take time to reach a predetermined voltage starts increasing at a constant rate with increasing the charging voltage of the capacitor C ₀ of the external. Therefore, when the main contact S ₁ is being turned in a state in which the phase failure occurs, the voltage of the detection terminal is beyond immediate reference voltage Vs ₂ of comparator 2b, the detected output from the comparator 2b is generated. The delay circuit 4 as shown in FIG. 32 (d) receiving the detection output begins to charge the capacitor C _5, to increase the charging current in response to an output of the subsequent detection circuit I side of the waveform shaping circuit 3a, a capacitor than is to charge the C _5.

[0049] That threshold level V of charging voltage comparator fifth capacitor C ₅ early from power
th ₅ the past becomes the this output phase loss detection signal from the output circuit 7 shown in FIG. 32 (e), the open phase immediately when the main contact point S ₁ is being turned in the open phase state The circuit is detected and the circuit is cut off, so that the load can be protected quickly. Note for operation in open phase occurs, from the rise reference voltage Vs ₂ are the same as in Example 2, a description thereof will be omitted.

FIGS. 32 (b) and (c) correspond to FIG. 7 (b)
7C shows the waveforms of the operating states of the waveform shaping circuits 3a and 3b, respectively, as in FIG. FIG. 33 shows a protected area in the present embodiment. X ₁ indicates the protected area of the first detection circuit I, X ₂ indicates the protected area of the second detection circuit II, and X ₃ indicates the second detection area when the power is turned on. 4 shows a protection area of the detection circuit II.

[0051]

According to the first aspect of the present invention, the open phase detecting means has at least two detection circuits each having a different reference voltage and detecting an open phase when the load voltage becomes higher than the reference voltage. , A plurality of detection stages, and the delay time can be set in each detection stage.

According to a second aspect of the present invention, in the first aspect of the present invention, when a load voltage equal to or more than a predetermined voltage is detected in at least one of the detection circuits, a load is applied to the capacitor with a constant current from the delay circuit. Since the apparatus is provided with the charge control means for supplying a current corresponding to the voltage, when the load voltage becomes equal to or higher than the predetermined voltage, the charging of the capacitor can be accelerated, and the load protection can be further ensured.

The invention of claim 3 is the invention of claim 1 or 2.
In the above, the delay circuit is common to each of the detection circuits, and when each of the detection circuits detects a phase loss, a common capacitor is charged with a constant current corresponding thereto, so that the delay circuit can be shared and circuit components can be used. There is an effect that the score can be reduced. According to a fourth aspect of the present invention, in the third aspect of the present invention, the time from when the power supply is turned on to the time when the reference voltage of the detection circuit having the higher reference voltage is increased at a constant rate until the reference voltage reaches a steady value is determined by the other detection circuit. Since the time until the reference voltage reaches the steady-state value is later than the time when the detection circuit with the higher reference voltage at the steady state detects the phase loss at the time of power-on, the other detection open circuit detects the phase loss earlier than the timing of detecting the phase loss. It is easy to detect, so even if the power is turned on in the open phase state, the open phase can be detected immediately and the load can be protected quickly, especially after the open phase is cut off, the cause of the open phase is removed. There is an effect that load protection can be surely achieved even when the power is re-input without being performed.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an open phase detection circuit unit according to a first embodiment of the present invention.

FIG. 2 is an overall circuit configuration diagram of the same.

FIG. 3 is a waveform diagram for explaining the operation of the above.

FIG. 4 is a diagram illustrating a protected area according to the first embodiment;

FIG. 5 is a specific circuit diagram of a main part of the above.

FIG. 6 is a circuit configuration diagram of an open phase detection circuit unit according to a second embodiment of the present invention.

FIG. 7 is a waveform diagram for explaining the operation of the above.

FIG. 8 is an explanatory diagram of a protection area according to the embodiment.

FIG. 9 is a circuit configuration diagram of an open-phase detection circuit unit according to a third embodiment of the present invention.

FIG. 10 is a waveform chart for explaining the operation of the above.

FIG. 11 is an explanatory diagram of a protected area according to the embodiment.

FIG. 12 is a circuit configuration diagram of an open phase detection circuit unit according to a fourth embodiment of the present invention.

FIG. 13 is a waveform diagram for explaining the operation of the above.

FIG. 14 is an explanatory diagram of a protected area according to the embodiment.

FIG. 15 is a circuit configuration diagram of an open phase detection circuit unit according to a fifth embodiment of the present invention.

FIG. 16 is a waveform chart for explaining the above operation.

FIG. 17 is an explanatory diagram of a protected area according to the embodiment.

FIG. 18 is a circuit configuration diagram of an open phase detection circuit unit according to a sixth embodiment of the present invention.

FIG. 19 is a waveform chart for explaining the operation of the above.

FIG. 20 is an explanatory diagram of a protected area according to the embodiment.

FIG. 21 is a circuit configuration diagram of an open phase detection circuit unit according to a seventh embodiment of the present invention.

FIG. 22 is a waveform diagram for explaining the operation of the above.

FIG. 23 is an explanatory diagram of a protected area according to the embodiment.

FIG. 24 is a circuit configuration diagram of an open phase detection circuit unit according to an eighth embodiment of the present invention.

FIG. 25 is a waveform diagram for explaining the operation of the above.

FIG. 26 is an explanatory diagram of a protected area according to the third embodiment.

FIG. 27 is a circuit configuration diagram of an open phase detection circuit unit according to a ninth embodiment of the present invention.

FIG. 28 is an explanatory diagram of a protected area according to the embodiment.

FIG. 29 is a circuit configuration diagram of an open phase detection circuit section according to Embodiment 10 of the present invention.

FIG. 30 is a waveform diagram for explaining the above operation.

FIG. 31 is a circuit configuration diagram of an open phase detection circuit section according to Embodiment 11 of the present invention.

FIG. 32 is a waveform chart for explaining the operation of the above.

FIG. 33 is an explanatory diagram of a protected area according to the third embodiment.

[Explanation of symbols]

1 constant voltage circuit 2a, 2b comparator 3a, 3b waveform shaping circuit 4a, 4b delay circuit 5a, 5b comparator 6 OR gate 7 output circuit I, II detecting circuit A phase loss detection circuit unit C ₁ to C ₄ capacitors Vs _1, Vs ₂ reference voltage Vth ₃ threshold level

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-169220 (JP, A) JP-A-3-104038 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H02H 3/08-3/253

Claims (4)

(57) [Claims] 1. A detection circuit for comparing a load voltage between a neutral line on a load side and each phase with a reference voltage and detecting an open phase when the load voltage exceeds the reference voltage. When the phase is detected, the capacitor is charged with a constant current and a delay circuit for delaying the output of the phase loss detection signal until the voltage of the capacitor reaches a certain level or more, and the phase loss detection means outputs the phase loss detection signal. It has a switch means that is turned on by a phase loss detection signal and a trip coil for the main contact that is excited by the switch means, and has a phase loss protection function that opens the main contact inserted into the electric circuit by excitation of the trip coil. In the circuit breaker, the open phase detecting means has at least two detection circuits each having a different reference voltage and detecting an open phase when the load voltage becomes higher than the reference voltage. Functional shielding Vessel. 2. At least one of the detection circuits includes a charge control unit that, when a load voltage equal to or more than a predetermined voltage is detected, supplies a current corresponding to the load voltage to the capacitor together with a constant current from the detection circuit. A contract that is characterized by
The circuit breaker with an open-phase protection function according to claim 1 . 3. The delay circuit according to claim 1, wherein the delay circuit is common to each of the detection circuits, and charges a common capacitor with a constant current in response to each of the detection circuits detecting a phase loss. 2. The circuit breaker with open-phase protection function according to item 2. 4. The time from when the power supply is turned on to the time when the reference voltage of the detection circuit having the higher reference voltage is increased at a constant rate until the reference voltage reaches the steady-state value is determined. The circuit breaker with an open-phase protection function according to claim 3, wherein the circuit breaker is set later than the time.