JPS58190751U - Program monitor device - Google Patents

Program monitor device

Info

Publication number
JPS58190751U
JPS58190751U JP8680582U JP8680582U JPS58190751U JP S58190751 U JPS58190751 U JP S58190751U JP 8680582 U JP8680582 U JP 8680582U JP 8680582 U JP8680582 U JP 8680582U JP S58190751 U JPS58190751 U JP S58190751U
Authority
JP
Japan
Prior art keywords
program
monitor device
address
circuit
setting circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8680582U
Other languages
Japanese (ja)
Inventor
弘 菅原
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP8680582U priority Critical patent/JPS58190751U/en
Publication of JPS58190751U publication Critical patent/JPS58190751U/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図はこの発明によるプログラムモニタ装置の一実施例を
示すブロック回路図であ呂。 図中、Ａ１〜Ａｎはプログラム開始アドレス設定回路、
Ｂ１〜Ｂｎはプログラム終了アドレス設定回路、Ｐはプ
ログラムカウンタ、Ｃ１〜Ｃｎは比較回路、Ｄ１〜Ｄｎ
はプログラム実行中信号、Ｅ１〜Ｅ。はプログラム実行
回数加算回路、Ｆ１〜Ｆｎはプログ・ラム実行時間積算
回路である。The figure is a block circuit diagram showing one embodiment of a program monitor device according to the present invention. In the figure, A1 to An are program start address setting circuits;
B1 to Bn are program end address setting circuits, P is a program counter, C1 to Cn are comparison circuits, D1 to Dn
are program execution signals, E1 to E. is a program execution number addition circuit, and F1 to Fn are program execution time integration circuits.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] プログラム実行中に、プログラムが起動されたことを検
出するためのプログラム開始アドレスおよびプログラム
が処理を終了したことを検出するためのプログラム終了
アドレスを格納するための、　　アドレス設定回路と、
上記設定回路のプログラム開始アドレスとプログラムカ
ウンタの値が一致した時に実行中信号をＯＮにし、一方
上記設定回路のプログラム終了アドレスとプログラムカ
ウンタの値が一致した時に上記実行中信号をＯＦＦにす
る比較回路と、上記実行中信号がＯＮになった時に実行
回数を加算する加算回路と、上記実行中信号がＯＮの間
、実行時間を積算する積算回路とを備えたことを特徴と
するプログラムモニタ装置。an address setting circuit for storing a program start address for detecting that the program has been started and a program end address for detecting that the program has finished processing during program execution;
A comparison circuit that turns on the running signal when the program start address of the setting circuit matches the value of the program counter, and turns the running signal OFF when the program end address of the setting circuit matches the value of the program counter. A program monitor device comprising: an adding circuit that adds up the number of executions when the executing signal is ON; and an integrating circuit that adds up the execution time while the executing signal is ON.
JP8680582U 1982-06-11 1982-06-11 Program monitor device Pending JPS58190751U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8680582U JPS58190751U (en) 1982-06-11 1982-06-11 Program monitor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8680582U JPS58190751U (en) 1982-06-11 1982-06-11 Program monitor device

Publications (1)

Publication Number Publication Date
JPS58190751U true JPS58190751U (en) 1983-12-19

Family

ID=30095572

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8680582U Pending JPS58190751U (en) 1982-06-11 1982-06-11 Program monitor device

Country Status (1)

Country Link
JP (1) JPS58190751U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63301334A (en) * 1987-06-02 1988-12-08 Fujitsu Ltd Measuring system for performance of virtual computer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63301334A (en) * 1987-06-02 1988-12-08 Fujitsu Ltd Measuring system for performance of virtual computer

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