JPS58190041A - Preparation of drive circuit substrate for display device - Google Patents

Preparation of drive circuit substrate for display device

Info

Publication number
JPS58190041A
JPS58190041A JP57072414A JP7241482A JPS58190041A JP S58190041 A JPS58190041 A JP S58190041A JP 57072414 A JP57072414 A JP 57072414A JP 7241482 A JP7241482 A JP 7241482A JP S58190041 A JPS58190041 A JP S58190041A
Authority
JP
Japan
Prior art keywords
electrode
drive circuit
film
thin film
electrode wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57072414A
Other languages
Japanese (ja)
Inventor
Koji Suzuki
幸治 鈴木
Mitsushi Ikeda
光志 池田
Toshio Aoki
寿男 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57072414A priority Critical patent/JPS58190041A/en
Publication of JPS58190041A publication Critical patent/JPS58190041A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To effectively prevent inter-layer short-circuit between multi-layer wirings and accordingly improve yield of display panel and also reliability by converting short-circuit defect between multi-layer wirings to open defect and by solving such defect in the comparatively initial stage of the manufacturing processes. CONSTITUTION:The Al film is vacuum-deposited in the thickness of 1,500Angstrom on a glass substrate 21 and the first electrode wiring which also concurrently operates as the gate electrode of thin film transistor and address line 221 and a ground line 222 which also concurrently operates as the one electrode of capacitor are formed by patterning said Al film. The SiO2 film 23 is etched by the ammonium fluoride and a substrate is then dipped into the 10% rare fydrochloric acid solution for partly removing the earth line 222 by etching. Thereafter, undoped amorphous silicon (a-Si) silm 24 is deposited in the thickness of 3,000Angstrom and patterning is carried out by the CDE in such a manner as said film is left only in the element region. A drive circuit substrate can be completed by forming the second electrode wiring which also concurrently operates as the source electrode of a thin film transistor and the data line 251 and the drain electrode which operates as a capacitor electrode 252 by patterning laminated film.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、*膜トランジスタアレイと多層配線構造を含
む液晶表示装置等の駆動回路基板の製造方法C−関する
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a manufacturing method C of a driving circuit board for a liquid crystal display device or the like including a membrane transistor array and a multilayer wiring structure.

〔発明の技術的背景とその間線点〕[Technical background of the invention and the points between them]

最近、薄膜トランジスタアレイを用いたディスプレイパ
ネルが各所で研究されている(例えばI E h4 W
’1Transactions on l1ilect
ron Devicaa。
Recently, display panels using thin film transistor arrays have been researched in various places (for example, IE h4 W
'1Transactions on l1ilect
Ron Devicaa.

vol、fm−20,no、 11. Novembe
r 197L p 995−](101参照)0第1図
は一般的な薄膜トランジスタアレイを用いたディスプレ
イパネルの等価(ロ)路であるoIIC11@  5J
jl  *・−t J n )は行方向の#膜トランジ
スタ13のゲート電極を共通Cニドライブするアドレス
ライン、12()J  、/ 2B  、−,12m 
)はデイヌブレイ信号を列方向の薄膜トランジスタノ3
のソース(1送るチータラインである。薄膜トランジス
タ13はアドレスラインllとチータライン12の各ク
ロスポイント(ユ対応した画素毎≦二相いられ、各ドレ
イン電極は表示素子15と共にキャパシタ14(−も接
続されている。表示素子15は例えば液晶やエレクトロ
ルミネセンス素子である。具体的に液晶ティスプレィパ
ネルを例にとると、アドレスライン1]、データライン
12トランジスタノ3およびキャパシタ14f集積形成
した駆動回路基板とこれに対1川する透明電極を全面C
二形改した基板との曲C二液晶膚を挾持することにより
構成される0このようなディスプレイパネルはアドレス
ライン毎Cニデータを書き込む線順次方式で駆動され5
表示素子ノ5をデユーティ比はぼ100%で#JFA!
できる利点がある0 ところで、この樟のディスプレイを旨詳細にあるいは犬
面槓表示で実現する場合、トランジスタの数は非常C二
条くなる。例えばアドレス200Xチー5’200or
とき、40000素子が必要となり、データライン、ア
ドレスラインのクロスポイント、忘よひキャパシタの数
もそれぞれ40 if (10必要と7(る。このよう
な大規模のトランジスタアレイをもつ駆動回路基板を歩
留りよく製造することは非常(ユ困難である。欠陥の主
原因としては■多層配線間あるいはキャパシタ(1)’
Q気的短絡、■配線の開放、■トランジスタの欠陥等が
考えられる0しかし、ディスプレイの点欠陥がある捏良
許されるときは、配線開放やトランジスタの欠陥は通常
欠陥であるため大きな問題とはならない口例えば第1図
(二おいて、アドレスラインllかその途中カ一点で切
断されても、アドレスライン1)の両方向から信号を入
れることC二より、他の画素(−は全く動作上影響な及
はさないし、又、切m王の位@によっては全ての画素が
正常動作をすることが期待されるからである。
vol, fm-20, no, 11. November
r 197L p 995-] (Refer to 101) 0 Figure 1 is an equivalent (b) circuit of a display panel using a general thin film transistor array oIIC11@5J
jl *・-t J n ) is an address line that drives the gate electrodes of the # film transistors 13 in the row direction in common C, 12()J , / 2B , -, 12m
) transfers the Denubray signal to the thin film transistor No. 3 in the column direction.
The thin film transistor 13 is connected to each cross point of the address line 11 and the cheater line 12 (≦2 phases for each corresponding pixel, and each drain electrode is connected to the capacitor 14 (- is also connected to The display element 15 is, for example, a liquid crystal or an electroluminescent element. Taking a liquid crystal display panel as an example, a drive circuit including an address line 1, a data line 12, a transistor 3, and a capacitor 14f is integrated. The entire surface of the substrate and the transparent electrode facing it
This type of display panel is constructed by sandwiching two liquid crystal panels with a modified substrate and is driven in a line-sequential manner in which data is written in each address line.
Display element #5 has a duty ratio of almost 100% #JFA!
By the way, if this camphor display is to be realized in detail or in a dog-faced display, the number of transistors will be very large. For example address 200X Chi 5'200or
In this case, 40,000 elements are required, and the number of cross points of data lines, address lines, and capacitors are also 40 if (10 and 7) respectively. It is extremely difficult to manufacture well.The main causes of defects are ■ between multilayer interconnections or capacitors (1).
Q: Possible causes include short circuit, open wiring, defective transistor, etc.0However, if there is a point defect in the display and fabrication is allowed, open wiring and defective transistors are usually defects, so it is not a major problem. For example, in Figure 1 (in Figure 1, even if the address line 11 is cut off at one point on the way, it is possible to input signals from both directions). This is because all the pixels are expected to operate normally depending on the order of magnitude.

これC二対し、多層配線間の短絡は点欠陥では済まない
から、ディスプレイf二とって大きな影響を与える・し
かも短絡位置をレーザー等で分離することは可能である
が、そのためC−は、短絡位置を知る必要かあり、これ
は開放チェックと異r(す、横置(二はう犬な時m1か
かかる。アドレスラインとチータライン曲だけでなく、
キャパシタの短絡チェックも含めると、きわめて非能率
的な横骨となる0更直二、短絡個所の分陥を行なう工程
も壇えるため、生産性が低下することはさけられμいに
の様な短絡欠陥は1層間絶縁膜が、結晶シリコンの熱酸
化膜と異なり低温でスパッタ法やCVD法で形成しなけ
ればならす、その膜質が非常C二劣ることに起因してお
+)、特にディスプレイの大面積化(二伴ってかなりの
数【二なることが予想される〇 〔発明の目的〕 この発明tま上述した従来の間地点を解決し。
On the other hand, a short circuit between multilayer wiring is not just a point defect, and has a big impact on the display f2.Moreover, it is possible to separate the short circuit position using a laser, etc., but for this reason, C- You need to know this, and this is different from the open check.It takes m1 when the horizontal position (second crawling dog).In addition to the address line and cheetah line songs,
Including the short-circuit check of the capacitor, the process of zero-resetting, straightening, and short-circuiting, which is extremely inefficient, is also included, so a decrease in productivity can be avoided. Short-circuit defects are caused by the fact that the interlayer insulating film, unlike the thermal oxide film of crystalline silicon, must be formed at low temperatures by sputtering or CVD, and its film quality is extremely poor, especially in displays. [Object of the Invention] This invention solves the above-mentioned problems of the conventional technology.

多層配線の層間短絡を効果的≦二防止してディスプレイ
パネルの歩留り同上、信頼性同上を図り得る表示装置用
駆動回路基板の製造方法を提供することを目的とするー 〔発明の概要〕 本発明は、薄膜トランジスタアレイと多層配線を含む駆
動回路基板の生産性を著しく阻害する多層配線間の短絡
欠陥を開放欠陥に変換し。
It is an object of the present invention to provide a method for manufacturing a drive circuit board for a display device that can effectively prevent short circuits between layers of multilayer wiring to improve the yield and reliability of display panels. [Summary of the Invention] The present invention converts short-circuit defects between multilayer interconnections into open defects, which significantly impairs the productivity of drive circuit boards containing thin film transistor arrays and multilayer interconnections.

かつ製造工程の比較的初期段階で対策することC−よl
] 、変換された開放欠陥が多数の場合はそのサンプル
の製造を中止し、無駄な生産を行なわないようCユする
。即ち本発明C−おいては、絶縁性基板上C1第1の電
極配線を形成し、全面を層間絶縁膜でおおった後、第2
の電極配線を形成する前に、基板全面を第1の電極配線
材料の工゛ソテング液でエツチングするーこれ(二より
、層間絶縁膜にピンホールがあった場合C二そのピンホ
ール下の第1の電極配線材料を除去して。
Also, countermeasures should be taken at a relatively early stage of the manufacturing process.
], If there are a large number of converted open defects, the production of that sample is stopped to avoid wasteful production. That is, in the present invention C-, after forming the first electrode wiring C1 on the insulating substrate and covering the entire surface with an interlayer insulating film, the second electrode wiring is formed on the insulating substrate.
Before forming the electrode wiring, the entire surface of the substrate is etched with an etching solution of the first electrode wiring material. 1 by removing the electrode wiring material.

第1.第2の電極配線の短絡を防止するものである〇 〔発明の効界〕 本発明C二よれば、多層配線層間の短絡を効巣的(二防
止して、ディスプレイパネルの歩留り同上、信頼性同上
ン図ることができる。また本発明f−おいて、エツチン
グ工程の後、サンプルを検査しピンホールの程度を知る
ことは、このエツチング工程前に層間絶縁膜U〕ピンホ
ールを見つけるよりも非常(=簡単(二かつ正確(′−
行なうことができる。何故なら、この種の駆動回路基板
には通常カラス基板が用いられ、ピンホール部の第1の
電極配線がエツチングされるとこの部分か透明となるか
らである。従ってピンホールの程#iによってこのサン
プルを次の工程C二進めるか否か力判断も下しやすく、
無駄な工程な貞くことができ、駆動回路基板の庄産性を
著しく尚めることか可能である。
1st. According to the present invention C2, short circuits between multilayer wiring layers can be effectively prevented, thereby improving the yield and reliability of display panels. In addition, in the present invention f-, it is much easier to inspect the sample after the etching process and find out the extent of the pinholes than to find the pinholes in the interlayer insulating film U before the etching process. (= easy (two and exact (′-
can be done. This is because a glass substrate is normally used for this type of drive circuit board, and when the first electrode wiring in the pinhole portion is etched, this portion becomes transparent. Therefore, it is easy to judge whether or not to proceed with this sample to the next step C2 based on the pinhole depth #i.
It is possible to eliminate unnecessary processes and significantly improve the productivity of the drive circuit board.

〔発明の実施例〕[Embodiments of the invention]

第2図(a) 、 (b)は本発明の一実施例C−より
製造された液晶表示装置の駆動回路基板の一画素部分乞
示す平面図とそのA−A’断面図である。製造工程を説
明すると、まずガラヌ基板2ノ上(−厚さ150OAの
Atl1!1を蒸暑しこれをパターニングして第1の電
極配縁である薄膜トランジスタのチー)’!$i!li
兼アドレスライアドレスライン22パシタの一万の電極
を兼ねる接地ライン・22□を形成する◎この後RI−
スパッタ法またはCVD法(ユよ113(it)OA 
0r8i(J、膜23を全面(二堆積する。この81(
J、膜23は薄膜トランジスタのゲート絶縁膜と配線の
層間絶縁膜を兼ねる。その後、この810.膜23をフ
ッ化アンモニウムで約15秒間エツチングし1次いで基
板を10%希塩酸溶液(二約3分程浸す。これにより、
5i(J、膜23(二図不U〕ようなピンホール26が
あったとき、その下の接地ライン22□が部分的にエツ
チング除去される◎この後、基板温度250℃で8 +
 )1.カブロー放゛醒分解法C二より、アンドープ0
〕アモルファスシリコン(a−s l )膜24を30
0OA堆積しこれを素子頭載(二σ〕み残すよう(二C
DEIユよりパターニングする。そして厚さ500Aの
M。膜、次いで厚さ6000AのAt膜を蒸暑し、これ
らの積層膜なパターニングして、第2の電極配縁である
薄膜トランジスタのソース電極兼データライン25、お
よびドレイン電極兼キャパシタ電極゛252を形成して
駆動回路基板が完成する、こうしてこの実施例によれば
1層間絶縁膜である810*$z3の形成後のエツチン
グ工程で。
FIGS. 2(a) and 2(b) are a plan view showing one pixel portion of a driving circuit board of a liquid crystal display device manufactured according to Example C- of the present invention, and a sectional view thereof taken along line AA'. To explain the manufacturing process, first, heat the 150 OA thick Atl1!1 on the Galanu substrate 2 and pattern it to form the thin film transistor which is the first electrode. $i! li
◎After this, form the ground line 22□ which also serves as the 10,000 electrodes of the address line 22 pacita.◎After this, the RI-
Sputtering method or CVD method (Yuyo 113 (it) OA
0r8i(J, deposit the film 23 on the entire surface (2). This 81(
J, the film 23 serves both as a gate insulating film of a thin film transistor and as an interlayer insulating film for wiring. After that, this 810. The film 23 is etched with ammonium fluoride for about 15 seconds, and then the substrate is immersed in a 10% dilute hydrochloric acid solution for about 3 minutes.
5i (J, When there is a pinhole 26 like the film 23 (U in Figure 2), the ground line 22□ below it is partially etched away. ◎After this, the substrate temperature is 250°C.
)1. From Kaburo release decomposition method C2, undoped 0
] Amorphous silicon (a-sl) film 24 is
0OA is deposited and this is left on top of the element (2σ) (2C).
Patterning is done using DEI. And M with a thickness of 500A. Then, the At film with a thickness of 6000 A was steamed, and these laminated films were patterned to form the source electrode/data line 25 of the thin film transistor, which is the second electrode wiring, and the drain electrode/capacitor electrode 252. According to this embodiment, the driving circuit board is completed by the etching process after the formation of 810*$z3, which is one interlayer insulating film.

8i(J、膜23にあるピンホール部の第1の電極配線
を除去することC二よって、第1.第2の電極配線の短
絡が防止される。
8i (J) By removing the first electrode wiring in the pinhole portion in the film 23 C2, a short circuit between the first and second electrode wirings is prevented.

具体的なデータC−より本発明の効果を明らかC二する
。上記実施例の工程(ユ従ったサンプルをAグルレープ
とし、]゛ソ化アンモニウム(二よるSin、膜エツチ
ング工程を省略した他は上記実施例と同様の工稈口従っ
たものをBグループ、また上記実施例1/Jような87
0.膜形成後のエツチング処理を行わなかったものをC
グループとして特性評価を行った◎駆動回路基板は、薄
膜トランジスタアレイ部が10X10d、)ランジヌタ
数は 50行×50列=2500(画素)。
The effects of the present invention are clearly demonstrated by specific data. The samples that followed the process of the above example were referred to as group A, and the samples that followed the process of the above example were referred to as group A, and the samples that followed the same process as in the example above were used as group B, and 87 like the above Example 1/J
0. C is the one that was not subjected to etching treatment after film formation.
Characteristics were evaluated as a group. ◎ The drive circuit board has a thin film transistor array section of 10 x 10 d, and the number of lungs is 50 rows x 50 columns = 2500 (pixels).

1つの画素の大きさは2 (10X 200μm、であ
る。下表はA、B、C各グループlO枚ずつのサンプル
(二対して、50本のアドレスライン中の開放があった
アドレスライン数の各グループ平均値およびアドレスラ
インとチータラインの短絡のあったサンプル枚数を示し
ている。
The size of one pixel is 2 (10 x 200 μm).The table below shows the number of open address lines out of 50 address lines, with 10 samples in each group A, B, and C. The average value for each group and the number of samples in which the address line and cheetah line were short-circuited are shown.

表から明らかなよう(二1本発明す)方法i二より多層
配線の短絡欠陥は着しく識少する。第1の電極配線すj
エツチング液でエツチングする削(二予め層間絶縁膜エ
ツチングを行うことは、AとBを比較して明らかなよう
(ユ有効であるが、Cとの関係でみれは、こり〕1@間
絶縁膜エッチング工程を行わなくても十分大きな効果が
得られることは明らかである。
As is clear from the table, short-circuit defects in multilayer interconnections are significantly reduced by Method I2 (according to the present invention). First electrode wiring
Etching with an etching solution (2) It is clear from comparing A and B that the interlayer insulating film is etched in advance. It is clear that a sufficiently large effect can be obtained without performing an etching process.

一万、表からアドレスラインの開放(断線)欠陥が増加
していることがわかる◎しかしこの欠陥は前述のようf
二、基板からの電極配線の収出し方BによiJ点欠陥C
二変換する対策が可能である。即ち、液晶を実装した後
、表示状態で開放欠陥位置を目視し、開放となっている
アドレスライン(二ついては両側から駆動信号を供給す
るような配線を施すことでこQ]対策が可能であI)、
余II問題とならない。
10,000, it can be seen from the table that the number of address line open (disconnection) defects is increasing◎However, as mentioned above, this defect
2. iJ point defect C due to method B of extracting electrode wiring from the substrate
Two conversion measures are possible. In other words, after mounting the liquid crystal, you can visually check the location of the open defect in the display state, and countermeasures can be taken by wiring the address line that is open (or wiring to supply drive signals from both sides). I),
It is not a problem.

以上のように本発明(−よれば、従来生産性を者しく低
下させていた多層配線(二おける層間短絡な大きく改善
でき、又、不良の基板を製造工程の比較的早い時期(二
発見できるため、むだな製造を減らすことができるなど
、表示装置用駆動回路基板の生産性を大幅に同上させる
ことができる◎ なお本発明は上記実施例C二限定されるものではない。
As described above, according to the present invention, it is possible to greatly improve the problem of interlayer short circuits in multi-layer interconnects (2), which had previously significantly reduced productivity, and to detect defective boards at a relatively early stage of the manufacturing process (2). Therefore, wasteful manufacturing can be reduced, and the productivity of the display device drive circuit board can be greatly improved. Note that the present invention is not limited to the above-mentioned Example C2.

薄膜トランジスタの半導体材料は。Semiconductor materials for thin film transistors.

a−ailユ限らすII−Vl族のCd8e、  Cd
8゜あるいはTeなどの材料でもよ(、層間絶縁膜は8
i(J、l1限らず、第1 +[i ’電極配線のエラ
チン1 グ液C−エツチングされないものであれはSi、N、等
イ11!の絶縁膜でもよい。更C二、第1層南極配線材
料としても、All二限らず、他の金属材料や透明電極
材料が使用できる。
A-ail limited II-Vl group Cd8e, Cd
8° or a material such as Te (the interlayer insulating film is 8°
i (not limited to J, l1, first + [i 'electrode wiring erating solution C- as long as it is not etched, it may be an insulating film of Si, N, etc.11!). The south pole wiring material is not limited to Al2, but other metal materials and transparent electrode materials can be used.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は表示装置駆動用のS膜トランジスタアレイの等
価回路図、第2図(a) 、 fb)は本発明の一実施
例C二よる駆動回路基板の1画集部の平面図とそのA 
−A’断面図である。 2ノ・・・ガラス基板、22.・・・ゲート峨極兼アド
レスライン、22.・・・キャパシタ電極兼接地ライン
、23・・・51(J、膜(ゲート絶縁膜兼層間絶縁膜
)24・・・a−8i膜、25I ・・・ソース電極兼
データライン、26.・・・ドレイン゛磁極兼キャパシ
タ゛atria 26・・・ピンホール〇出願人代理人
 釉土鈴江武 彦 2 第1図 1i2ツ (a) (b)
FIG. 1 is an equivalent circuit diagram of an S-film transistor array for driving a display device, and FIGS.
-A' sectional view. 2 No. Glass substrate, 22. ...Gate terminal and address line, 22. ... Capacitor electrode/ground line, 23...51 (J, film (gate insulating film/interlayer insulating film) 24... a-8i film, 25I... Source electrode/data line, 26...・Drain (magnetic pole and capacitor) atria 26...Pinhole〇Applicant's agent Takehiko Suzue 2 Figure 1 1i2 (a) (b)

Claims (1)

【特許請求の範囲】 (1)絶縁性基板C二薄膜トランジスタアレイと多層配
線を含む表示集子駆動回路が集積形成された駆動回路基
板を製造する亀−際し、絶縁性基板上(1第1の電極配
線を形成し全面をj−開維縁膜でおおった後、第2の電
極配線を形成する前C−5基板全面を前記第lの電極配
線材料のエツチング液でエツチングする工程を設けたこ
とを特徴とする表示装置用駆動回路基板の製造方法、(
2)表示素子は液晶表示素子であり、第1の電極配線は
行方向の薄膜トランジスタのゲートを共通接続するアド
レスラインおよび各薄膜トランジスタと対をなして設け
られるキャパシタの一万の電極となる接地ラインであり
、第2の電極配線は列方向の#綾トランジスタのソース
を共通接続するチータラインおよび各AI換トランジヌ
タのドレイン電極を兼ねるSiJ記キャパシタの他方の
電極である特許請求の範囲第1項記載の表示装置用駆動
回路基板の製造方法。 (3)  層間絶縁膜は薄膜トランジスタのゲート絶縁
膜を兼ねるスパッタ法またはCVD法C二よる8IO1
膜である特許請求の範囲第1項記載の表示装置用駆動回
路基板の製造方法。
[Scope of Claims] (1) When manufacturing a drive circuit board on which a display concentrator drive circuit including two thin film transistor arrays and multilayer wiring is integrated, an insulating substrate C (1 first After forming the electrode wiring and covering the entire surface with a J-open fiber edge film, a step of etching the entire surface of the C-5 substrate before forming the second electrode wiring with an etching solution of the first electrode wiring material is provided. A method for manufacturing a drive circuit board for a display device, characterized in that (
2) The display element is a liquid crystal display element, and the first electrode wiring is an address line that commonly connects the gates of the thin film transistors in the row direction, and a ground line that serves as the electrode of 10,000 capacitors provided in pairs with each thin film transistor. According to claim 1, the second electrode wiring is a cheater line that commonly connects the sources of the #transistors in the column direction and the other electrode of the SiJ capacitor that also serves as the drain electrode of each AI conversion transistor. A method for manufacturing a drive circuit board for a display device. (3) The interlayer insulating film is made of 8IO1 by sputtering method or CVD method C2 which also serves as the gate insulating film of the thin film transistor.
A method for manufacturing a display device drive circuit board according to claim 1, which is a film.
JP57072414A 1982-04-28 1982-04-28 Preparation of drive circuit substrate for display device Pending JPS58190041A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57072414A JPS58190041A (en) 1982-04-28 1982-04-28 Preparation of drive circuit substrate for display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57072414A JPS58190041A (en) 1982-04-28 1982-04-28 Preparation of drive circuit substrate for display device

Publications (1)

Publication Number Publication Date
JPS58190041A true JPS58190041A (en) 1983-11-05

Family

ID=13488593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57072414A Pending JPS58190041A (en) 1982-04-28 1982-04-28 Preparation of drive circuit substrate for display device

Country Status (1)

Country Link
JP (1) JPS58190041A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60175032A (en) * 1984-02-20 1985-09-09 Sanyo Electric Co Ltd Manufacture of thin film transistor
JPS61183972A (en) * 1985-02-08 1986-08-16 Matsushita Electric Ind Co Ltd Manufacture of thin film semiconductor device
JPS6444419A (en) * 1987-08-11 1989-02-16 Fujitsu Ltd Liquid crystal display panel
JPH01158776A (en) * 1987-12-16 1989-06-21 Toshiba Corp Manufacture of thin film device
JPH0451120A (en) * 1990-06-19 1992-02-19 Nec Corp Liquid crystal display element array driven by thin-film electric field effect type transistor
JPH04299315A (en) * 1991-03-28 1992-10-22 Sanyo Electric Co Ltd Liquid crystal display device
JPH04120172U (en) * 1991-04-02 1992-10-27 オムロン株式会社 Coin slot structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS551150A (en) * 1978-06-19 1980-01-07 Matsushita Electric Ind Co Ltd Method of fabricating semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS551150A (en) * 1978-06-19 1980-01-07 Matsushita Electric Ind Co Ltd Method of fabricating semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60175032A (en) * 1984-02-20 1985-09-09 Sanyo Electric Co Ltd Manufacture of thin film transistor
JPS61183972A (en) * 1985-02-08 1986-08-16 Matsushita Electric Ind Co Ltd Manufacture of thin film semiconductor device
JPS6444419A (en) * 1987-08-11 1989-02-16 Fujitsu Ltd Liquid crystal display panel
JPH01158776A (en) * 1987-12-16 1989-06-21 Toshiba Corp Manufacture of thin film device
JPH0451120A (en) * 1990-06-19 1992-02-19 Nec Corp Liquid crystal display element array driven by thin-film electric field effect type transistor
JPH04299315A (en) * 1991-03-28 1992-10-22 Sanyo Electric Co Ltd Liquid crystal display device
JPH04120172U (en) * 1991-04-02 1992-10-27 オムロン株式会社 Coin slot structure

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