JPS5818956A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the formation of parasitic transistors and cut down the chip size, by a method wherein a resistor region and the base and emitter region of a transistor are provided in an island region isolated electrically and the base region is surrounded by a region of the same conductive type as the island region but high impurities concentration. CONSTITUTION:Transistor elements Q1 and Q2 are provided which are parallel- connected between the terminal of a power supply terminal (1) and a ground terminal (2), and each collector is connected with said terminal (1) and each emitter with the terminal (2) through respective resistors R3 and R4. The emitter of the element Q1 is connected with the base of the element Q2. Resistors R1 and R2 are provided in parallel with these circuits, and the neutral is connected with the base of the element Q1. In such IC, an N<+> type maximum bias potential supply region (4) mounted on the semiconductor substrate is rendered to combine the collector regions of the elements Q1 and Q2 and render it the higher impurity concentration than an N<-> type epitaxial layer (3) in existance of the resistor. In such a case, the base regions (6) and (16) of the elements Q1 and Q2 are surrounded by the region (4') to prevent the occurrence of parasitic effect.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a putter layer 9 for a semiconductor integrated circuit.

A semiconductor integrated circuit is mainly composed of resistors and transistors, and when converting the circuit shown in FIG. 1 into a semiconductor integrated circuit, the pattern layout shown in FIG. 2 has conventionally been used. In Figure 1, Te, R, and ~ electric are the resistances bQt
-Q* is a transistor, 1 is a Vcc power supply terminal which has the highest potential of the circuit, and 2 is a ground terminal. In the circuit shown in FIG. 1, the transistor QhQ- is connected in Darlington and the m tv
It has the function of performing bell shift and increasing the output current capacity. In the conventional 0 pattern layout shown in Figure 2, mR
Although the resistance regions 1 to FL4 can be manufactured in the same epitaxial region 3, transistors Q and Qt are individually separated by an isolation region 8. If Qt −Q
If the conventional technology is used to form i in the region of 3, a parasitic effect will occur and the circuit will no longer operate. Note that 4 is a portion that biases the island-like epitaxial region 3, which is normally biased at the highest potential Vcc. Further, 5, 6 and 7 indicate the emitter region, base region and collector extraction region of the transistor, respectively.

FIG. 3 shows a sectional view taken along line AA' in FIG. 2. As shown in Fig. 3,) transistor Q,
In order to separate from the island-like epitaxial layer 3, it is necessary to set the distances e, , e, taking into consideration not only the separation region 1jR8 but also the spread of the depletion layer. This 11
．． 12 must be made larger as the element becomes a higher breakdown voltage element, resulting in an increase in chip size.

An object of the present invention is to provide a semiconductor integrated circuit in which chip size can be reduced.

That is, an integrated circuit according to the present invention is one in which a transistor whose collector is connected to the highest potential is formed without forming a parasitic transistor in the resistor manufacturing epitaxial region, and will be described in detail below with reference to the drawings.

FIG. 4 is a top view of a pattern layout according to an embodiment of the present invention. In the present invention, the highest bias potential supply region 4
′ is the collector region of the transistor Q, ,Q, and the collector is formed with an impurity region with a higher concentration than the epitaxial region of N″″ where the resistance exists, and the collector region is the base region of the transistor Q, ,Q. It encompasses the entire circumference of 6.16. This area A is created at the same time as Entsuta. In order to avoid parasitic effects, it is important to surround the entire periphery of the N+ region base region of the collector. As shown in FIG. 5, there is a partial loss of the N+ region of the collector.

At point A in the epitaxial region, a current flows from the highest potential 4 to the collector deposit 7, and the potential also drops from the highest potential 4. When this potential drop exceeds the base-emitter forward voltage Via (approximately 0.7 V) of the transistor, the transparent transistor Qp shown in FIG. 6 operates, causing a circuit malfunction. Same b Q' is resistance Rt-emitter,
This is a parasitic PNP transistor whose base is at point A in the epitaxial region and whose collector is at the substrate 12. Further, 10 is an aluminum wiring, and 11 is a silicon oxide film.

In one embodiment of the present invention shown in FIG. 4, the collectors of Qt, t, and h are connected to each other by a diffusion layer, but as shown in FIG. They may be connected by metal wiring 13 such as aluminum wire. In this case as well, it is important to surround the entire circumference of the base to the collector in order to avoid parasitic effects. If the entire circumference is surrounded by the transistor, even if the inside N+15.16 drops below the highest potential when current flows through the transistor, the outside of the transistor will be held at the highest potential Vcc, so no parasitic effects will occur. Note that 14 is the ninth hole for making contact with the aluminum wiring.

As described above, according to the present invention, since the transistor and the resistor can be formed in the same epitaxial region, the pellet size can be significantly reduced.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram to be made into a semiconductor integrated circuit, Fig. 2 is a conventional pattern layout diagram, Fig. 3 is a sectional view taken along the line A- in Fig. 2, and Fig. 4 is a pattern layout diagram of the present invention. FIGS. 5 and 6 are diagrams for explaining parasitic effects, and FIG. 7 is a top view showing another embodiment of the pattern layout according to the present invention. ---...Electric 1 terminal (Vcc), 2------Jtl1m terminal, 3-... Island-like epitaxial layer %4.4'... Maximum potential bias region, 5-・
...Emitter region, 6.-1 base region, 7..
... Collector extraction area %8 --- Insulating isolation region, 9--- Buried layer, 10-- Aluminum wiring, 11-- Oxide film, 12-- --One board. +,,5. :, 1 Conclusion 5 Illustration 7 Illustration

Claims (1)

[Claims] A resistor region and a base and emitter region of a transistor are provided in one electrically isolated island region, and the base region is surrounded by a region having a higher concentration and the same conductivity type as the island region. A semiconductor integrated circuit characterized by: