JPS58188391A - Non-volatile memory circuit - Google Patents

Abstract

PURPOSE:To prevent the change in the content of memory due to electrostatic noise and to attain high reliability, by integrating a voltage impressed to a write/erase external terminal and applying a gate of a memory. CONSTITUTION:In impressing +30V to a common terminal VM9, when a gate potential of a control FET13 is a low potential VSS +30V is impressed to a gate of a memory 12 and the memory 12 is the write state. In applying +30V to a terminal WM9, when the gate of the FET13 is a high potential Vdd, the FET13 is set on, and a voltage subtracting the voltage drop of a diode 14 from the VSS is impressed to the gate of the memory 12, and the content of memory is erase state. A resistor 11 and a capacitor 15 added to the gate of the memory 12 form an integration circuit to the impressed voltage to the terminal VM9, a voltage at a connecting point B at the gate of the memory 12 is a waveform as shown in a curve (b), the maximum value of the voltage at the point B is about 14V and the content of memory 12 is unchanged.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile memory circuit, and its purpose is to prevent memory contents from changing due to the influence of noise due to static electricity or the like.

The following explanation will be given based on the drawings. FIG. 1 is a circuit diagram showing an example of a nonvolatile memory circuit, and shows an external write terminal W.
1 is connected to the gate of a nonvolatile memory 4 (hereinafter simply referred to as memory) via a resistor 2, and is also connected to the drain of a control transistor 6. The source of the control transistor B is connected to the external erasing terminal E6. The north of the memory 4 is connected to the high potential side Vdd of the power supply, and the train is connected to the low potential side Vdd of the power supply via a load resistor 5.
SS and the connection point between the drain of the memory 4 and the resistor 5 becomes an output terminal OUT.

Data is supplied to the gate of the control transistor 3. The operation of this circuit is as follows.

First, when a negative high voltage (-30V) is applied to the external erasing terminal E6, the control transistor 6 is turned on regardless of the contents of the switch.

The reason for this is that the level of the data is Vdd or VLS, which is sufficiently higher than the negative high voltage (-30V). Therefore, the gate of the memory 4 has a negative high voltage (
Or a voltage lower than this (voltage obtained by subtracting the VSSO value) is applied. The memory 4
When a high negative voltage (approximately -26 V or more) is applied to the gate, the contents of the memory 4 are erased. After the erase operation is completed, the erase external terminal (-E6) is externally connected to the low potential side VSS.

Next, a positive high voltage (+3°■) is applied to the external write terminal W1. At this time, if the content of the voltage applied to the gate of the control transistor B is VSs, then the control transistor B is in an OFF state, so that the gate of the memory 4 is applied to the gate of the memory 4. A high positive voltage is applied to the gate of the memory 4.
-4-26V or higher) is applied, the contents enter the write state. Further, when a positive high voltage is applied to the internal correction writing external terminal W1, if the level of data applied to the gate of the control transistor 6 is at the high potential Vdd. Since the control transistor 6 is turned on, a voltage at the Vss level is applied to the gate of the memory 4, so that the contents of the memory 4 are maintained in the erased state. After the writing process is completed, connect the terminal W HV d
Connect to level d externally.

- The normal usage situation of the memory circuit mentioned above is as follows.

That is, the gate of the control transistor B is configured to be at the VSS level except when reading the memory circuit.

Then, the control trans distal is in the off state,
The gate of the memory 4 is connected to Vdd through the resistor 2.
A voltage force of level 1 is applied. This condition can reduce the phenomenon of deterioration that changes with the content of the memory 4 over time. Next, when reading the memory 4, the gate potential of the control transistor B is set to a high potential Vd.
Make it d. At this time, the control transistor 3 is turned on, and a voltage at the Vss level is applied to the gate of the memory 4. At this time, if the memory 4 is in the erase state, the memory 4 is in the off state, so the potential of the memory output terminal OUT becomes the Vss level, and if the memory 4 is in the write state, the memory 4 is in the on state. Therefore, a voltage at the Vdd level appears at the memory output terminal OUTK.

In the configuration described in 1-, it is necessary to connect the external erasing terminal E6 and the external writing terminal W1 to a power supply line at the end of erasing and writing operations, which makes the work process complicated. Not only that, but microelectronic devices such as watches require space for external wiring, which impedes miniaturization.

Therefore, as shown in the circuit diagram of Fig. 2, external write terminal W1
There is no way to think of a way to connect the erase external terminal E6 to the power supply using a resistor 7.8 inside the integrated circuit. However, this method has the following drawbacks. That is, after the erasing and writing operations are completed, electrical noise due to static electricity or induction may be applied to the erasing external terminal E6 or the writing external terminal W1. Since this induced noise generally has a high source impedance, if the resistors 7 and 8 are made sufficiently small, the influence will be eliminated, but the problem of static electricity noise remains.

The static electricity that is normally considered when dealing with integrated circuits is mainly caused by the human body, and its magnitude is represented by a model charged to 160 V with a capacity of 200 F, ie, the circuit diagram shown in Figure 3 (a). It will be done.

When considering the memory circuit configuration shown in Figure 2 using this model, the switch S is shown in the circuit diagram of Figure 3 (a).
When the voltage is turned on, a voltage as shown in FIG. 3(b) appears at the write external terminal W1 or the erase external terminal E6.

The time constant is determined by I( and C in FIG. 3(a)), but since the maximum voltage appears as is, 160V, there is a possibility that the contents of the memory 4 will change due to this.

The present invention provides a nonvolatile memory circuit that solves the above problems, and FIG. 4 shows a circuit diagram of a memory circuit that is an embodiment of the present invention. In FIG. 4, the functions of both the writing external terminal and the erasing external terminal are performed by a common terminal VM9, and the common terminal V,
9 is grounded to the high potential side Vdd by a resistor 10 and connected to the gate of the memory 12 via a resistor 11. The gate of the memory 12 is further connected to the drain of the control transistor 16, and the control transistor 1
The 60 source is connected to the low potential side Vss via the diode 14. The gate of the memory 12 is 1Hco15
is grounded to the high potential side Vdd.

The normal erasing and writing operations in the embodiment 1-1 are as follows. First, -30V is applied to the common terminals V and 9. At this time, due to the action of the diode 14, -30V is applied to the gate of the memory 12, so that the contents of the memory 12 are erased. Next, apply +30V to the common terminal vw9.
Apply. At this time, if the gate potential of the control transistor 13 is a low potential Vss, the control transistor 16 is off, so -+-30V is applied to the gate of the memory 12, and the memory 12 is written. It becomes a crowded state. Further, when +30V is applied to the common terminals V and 9, if the gate potential of the control transistor 16 is at the voltage potential Vdd, the control transistor 16 is turned off, and the gate of the memory 12 is supplied with a voltage lower than the low potential Vss. Only a voltage equal to the voltage drop across the diode 14 is applied, so the memory contents remain erased.

In the memory circuit having the above configuration, if we consider an equivalent circuit using the noise model described above, it will be as shown in the circuit diagram of FIG. 5(,). If the ambiguity of the noise model is 01 and the value of the resistor 10 is R1, R1 becomes a discharge circuit for discharging C1, and the voltage at the connection point A is as shown in Fig. 5 (
As shown in curve (a) of b), it decays with a time constant of <C+XR+.

On the other hand, if the value of the resistor 11 is RO, the memory 12
If the value of volumetric weight 15 added to the gate of is C0, then (
(0 and CO form an integrating circuit that integrates the voltage applied to the external terminal VM9, and the voltage at the output terminal of the integrating circuit, that is, the voltage at the connection point B at the gate of the memory 12 is as shown in FIG. ) will have a waveform as shown in curve (b).Here, if the value is set so that f(o x Co is larger than R, xC, the voltage at the connection point B will be sufficient) It can be made smaller.-For example, "+=
200PF, R, = 10Ω, Co = 2PF', too
=4 KO, when C+ is charged with 160V and switch S is turned on, the maximum value of the voltage appearing at the point B is approximately 14V, and the contents of the memory 12 are not changed.

As described above, according to the present invention, changes in memory contents due to electrostatic noise can be prevented, and an extremely reliable product can be provided, and its effects are outstanding.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional memory circuit, Figure 2 is a circuit diagram of a conventional memory circuit showing an improved example of the conventional memory circuit, and Figure 3 (a
) and FIG. 3(b) are circuit diagrams and waveform diagrams of equivalent circuits that model an electrostatic noise source and some of the circuit components of FIG. 2, and FIG. 4 shows an embodiment of the present invention. The circuit diagrams of the memory circuit, FIGS. 5(a) and 5(b), are circuit diagrams and waveform diagrams of equivalent circuits that model the electrostatic noise generation source and some of the circuit components shown in FIG. be. 9... Common external terminal VM (external terminal for writing/erasing),
10.11.Resistor, 12..Nonvolatile memory, 15..Rongjun. 1rjA Figure 2 ■ ■ Shi-hi Figure 3 (a) (b) Figure 4 Figure 5 (CI) (b)

Claims (1)

[Claims] 1. A nonvolatile memory circuit comprising: an integrating circuit that integrates a voltage applied to an external write/erase terminal; and an output terminal of the integrating circuit connected to a gate of a nonvolatile memory.