JPS6262497A - Writing device for eprom - Google Patents

Abstract

PURPOSE:To fully enhance a writing control voltage and shorten a writing processing time without sacrificing the reliability by providing a pumping circuit between a word line and the second reference voltage source and raising the writing control voltage on the selected word line higher than the second reference voltage. CONSTITUTION:A pumping circuit 10 inserted between word lines 1, 2... selectively selected and floated by the first reference voltage Vcc as a writing control voltage and the second reference voltage source 7 supplying the second reference voltage Vpp higher than the first reference voltage Vcc fills and accumulates an electric charge on the floated word line and raises its voltage to above the second reference voltage Vpp. Thereby, a voltage value of the second reference voltage commonly supplied to other circuit elements is kept as in the conventional case, while avoiding an increase of a current density, and at the same time raises the writing control voltage supplied to a gate of a memory cell via the selected word line to shorten a writing processing time.

Description

[Detailed Description of the Invention] [Technical Field] This invention relates to an electrically rewritable read-only memory.
(Electrica11y Programmable
e Read Only Memor7. Below, EP R
(abbreviated as OW), whose storage cells are typically MOS (Metal Oxide Semiconductor
FAMOS (Fl
oating gate Avalanche 1nj
This article relates to a writing device for a device that is a MOS transistor, and relates to an improvement in which the writing control voltage on the word line is increased to shorten the writing processing time. The configuration is shown in FIG.

That is, typically, a plurality of memory cells X11 . X12・Fist・X21. X22... are arranged in a matrix, of which memory cells (x11, X12...) forming a group in one row direction,
The gates of (X21,
, (X12.X22...) (7) One end of each is connected to the bit lines 3, 4..., respectively. The word line 1.2-Φ extends to each output terminal of the write control voltage distributor 5 to which the first reference voltage Vcc as the write control voltage is applied to its input terminal, while the bit line 3.2-Φ. 4 extend to each output terminal of the write voltage distributor 6 to which the write voltage Vw is applied.

Further, a second reference voltage source 7 supplies each word line l, 2 (word line 2 is omitted from illustration) and a second reference voltage Vpp higher than the first reference voltage Vcc.
Two field effect transistors 8.9 (hereinafter abbreviated as FETs) are connected in series through a node F, and the gate of FET 8 is connected to node F.

Then, the gate of FET9 is connected to rl only during write processing.
A write signal SR which is transferred to J is supplied.

In this configuration, during the write processing operation, the write control voltage distributor 5 and the write voltage distributor 6 step forward while maintaining synchronization, and the word lines 1, 2, . . . and the bit lines 3, 4, . is alternatively selected, the storage cell located at the intersection is identified, and a predetermined rlJ rQJ state is written thereto.

That is, first, the write control voltage distributor 5 selectively selects the word line 1 from among all the word lines kept at ground, and for each bit period during the selected word period, A signal that either precharges the word line 1 to a first reference voltage Vcc and puts it in a floating state, or keeps the word line l grounded, based on predetermined write information. Process.

Meanwhile, during this time, the write voltage distributor 6
All bit lines 3.4... kept open
Starting from the middle, bit lines 3, 4, and
-. is selected alternatively, and during that period, signal processing is performed to constantly maintain the selected only bit line at the write voltage V%#, and when this signal processing is completed for all bit lines, , the write control voltage distributor 5 steps forward, and this time selects the next word line 2.

Thus, the first reference voltage Vcc as a write control voltage is supplied to its gate via the alternatively selected word line, and at the same time, the first reference voltage Vcc is supplied via the alternatively selected bit line. , "0" is written into the memory cell to which the write voltage Vw is supplied between its drain and source.

In such a conventional circuit, in order to shorten the write processing time, the word line voltage applied as the write control voltage to the gate of the memory cell during rOJ writing is changed to the first reference voltage by the pull-up FET 8. A second reference voltage vpp higher than Vcc.

It is lifted up to.

That is, if FET 9 is considered short-circuited, the voltage on word line l is maintained at a voltage approximately equal to the second reference voltage due to the well-known pull-up action of FET 8. In addition, in such conventional circuits, the first
In order to reduce the burden of sink current when many word lines other than the only word line floating at the reference voltage Vcc are grounded at the same time at the distributor 5, their gates are Write signal S to
FET 9 for gating becomes conductive upon receiving R
, the pull-up effect on the word line is limited in time.

Problems with the prior art > Therefore, in order to ensure the above-mentioned effects, FET 8 and FET 9 are inserted in series between the second reference voltage source 7 and each word line 1.2... In the above conventional circuit consisting of
During this time, the threshold voltage of two FETs will be generated, but even if a normal improvement is made to use a debracygon type as FET 8 to compress this, the threshold voltage of one FET 9 will be generated. Since the Lessjord voltage still remains, that amount is applied to the second reference voltage Vp.
There was a problem in that the word line voltage could only be raised to a voltage subtracted from p, and the write processing time was not completely shortened.

In particular, if the second reference voltage Vpp, which is commonly supplied to other circuit elements, is selected to a higher voltage value, the current density in the circuit elements will become excessive as the integration density tends to increase. However, these problems have been contradictory: they generate heat and cause wiring failures, leading to a decrease in reliability.

Means for Solving the Problems 〉 The object of the present invention is to solve the two contradictory problems of the problem of insufficient shortening of write processing time due to circuit configuration constraints based on the above-mentioned conventional technology and the problem of reliability deterioration. In view of this, a pumping circuit is added between the word line and the second reference voltage source.
The above problem is solved by increasing the write control voltage on the selected word line above the second reference voltage,
It is an object of the present invention to provide an excellent EP RON writing device that allows the appropriate selection of the second reference voltage value and significantly shortens the writing processing time without sacrificing reliability in any way.

Effect> As shown in FIG. 1, the configuration of the present invention in accordance with the above object is such that the word line 1 is selectively selected and floated at the first reference voltage Vcc as the write control voltage. .2... and the second reference voltage source 7 that supplies the second reference voltage Vpp higher than the first reference voltage Vcc, the pumping circuit 1G is connected to the floating word. A voltage value of the second reference voltage Vpp that is commonly supplied to other circuit elements by injecting and depositing charge into the line and increasing its voltage to a level higher than the second reference voltage Vpp. remains unchanged to avoid an increase in current density, while at the same time increasing the write control voltage supplied to the gate of the storage cell via the selected word line to reduce the write process time. Embodiment> The configuration of an embodiment of the present invention will be described below based on FIG. 1.

A pumping circuit 10 is inserted between the word v; A first . It includes second FETs B and C and a coupling capacitor A whose one end (output end) is connected to node D, and the gate of the first FETB is connected to word line 1 via node E. The gate of the second FET C is connected to node D.

The other end (input end) of the coupling capacitor A is connected to the output terminal of the driver 11, the input terminal of the driver is connected to the output terminal of the square wave oscillator 12, and the control signal terminal of the oscillator is connected to the output terminal of the driver 11. The driver 11 and the square wave oscillator 12 are supplied with the signal SR, and are supplied with power from the second reference voltage source 7.Other components are the same as those indicated by the same reference numerals in FIG. 3, respectively.

The operation of the configuration of such an embodiment will be explained below with reference to FIG. 2.

During a write operation, a write signal S is sent to the control signal terminal.
Upon receiving R, the rectangular wave oscillator 12 generates a rectangular wave pulse train as shown in FIG.

At this time, word line 1 has already been selected and is floating at the first reference voltage Vcc, so the first reference voltage Vcc is supplied to the gate of the first FET H. Then, the FETB wanders in the boundary region between the on state and the off state, and as a result, the voltage VD at the node D is as follows: VD = Vcc - VT(B) However, VT(B) Once the threshold voltage of FIT H has settled (FIG. 2(B)a), the second FET C remains off.

Then, when the first leading edge of the square wave pulse rises (FIG. 2(A)b).

A second reference voltage Vpp higher than the first reference voltage Vcc
A voltage change equal to is directly transmitted from the input terminal of the coupling capacitor A to the output terminal of the capacitor, but that voltage change is divided by the ground capacitance CD of the node D and the capacitance CA of the coupling capacitor A. So, at node D,
It is expressed as a voltage change of ΔV. This voltage change Δ
V is represented by.

As a result, the voltage VO at node D is.

It rises to VD = Vcc - VT (B) + ΔV - (Fig. 2 (B) C).

During this period, the voltage VD at node D reaches the threshold voltage of the second FET C and exceeds it, as follows: At that point, the second FET C turns on and the first FET B is forced into the off state, so the voltage vE at node E at that point is VE = VE(1) = V cc - VT( B) +Δ
V -VT(c) (Fig. 2(C)d).

Thus, it is a necessary condition for the operation of this pumping circuit that the second FET C is turned on at the rising edge of the first front of the square wave pulse. The capacitance CA of the coupling capacitor A must be selected within a range that satisfies the variation Vpp.

Thereafter, there is no change in the circuit state until the first trailing edge falls half a cycle after the subsequent rectangular wave pulse, and the voltage values at each part are maintained as they are. Figure 2 (A) e) In response to the voltage change ΔV, the voltage VD at node D decreases, which increases the gate voltage of the first FET B at that point, that is, the node at that point. E
When the first FET H reaches a value lower than the voltage V E (1) by the threshold voltage V T (B) of the first FET H, the first FET B starts wandering again in the boundary region between the on state and the off state. Therefore, the voltage VO at node D is: V D = VE (1) - V TCB) = Vcc
−VTCB) + ΔV−VT(c) −VT(B) (Fig. 2(B) f), that is, at this point, the voltage VD at node D is before the first leading edge of the square wave pulse. ΔV −V for the initial value (V cc −T(B))
This means that the voltage has increased by T(C) -V T(B).

During that time, since the second FET C remains off, the voltage VE at the node E remains unchanged (FIG. 2(C)g).

Thereafter, the same operation is repeated for each leading edge and trailing edge of the rectangular pulse train, and the voltage VD at node D and the voltage VE at node E increase in a stepwise manner.
i.e., the write control voltage V on word &11
E is VE = Vpp + VT (B) However, 7 (B)... is the threshold voltage of the first FET B, under the condition that the substrate is at a negative potential with respect to the source.

, the first FET B turns to the ON state in the opposite direction and starts wandering in the boundary region between the ON state and the OFF state, so that the voltage VE at the node E, which is the gate voltage of the FET B, becomes equal to the above-mentioned value. It is held at a constant value (Fig. 1(C)h).

In other words, the write control voltage on the word line l becomes higher than the second reference voltage Vpp by the threshold voltage V T (B) of the first FET B;
B has a negative substrate potential with respect to its source, so its threshold voltage V T (C
) is normally increased to about 2.4V, - for example,
If the second reference voltage Vpp is selected to be 12.5V, a voltage of about 15V can be obtained as the write control voltage VE on the word line 1.

At that time, the second FET C is also wandering in the boundary region between the on state and the off state, and the voltage VD of the node D is higher than the voltage VE of the node E at that time.
A value lower by the threshold voltage VT(C) of C, that is.

V D = V pp + V T (B) + V T (
It settles on C) (Fig. 2 (B) i).

Effects> As described above, according to the present invention, the write control voltage supplied to the gate of the memory cell via the word line selected and floated at the first reference voltage Vcc is lower than the reference voltage Vcc. By adding a pumping circuit that increases the voltage to a level higher than the high second reference voltage Vpp, the second reference voltage Vpp that is commonly supplied to other circuit elements is not changed to a high voltage. Since only the write control voltage can be raised to a sufficiently high voltage, it is possible to simultaneously solve the conflicting problems of shortening the write processing time and ensuring reliability, and to increase the second reference voltage Vpp. The excellent effect is that the write control voltage can be sufficiently increased and the write processing time can be significantly shortened without sacrificing reliability at all.

[Brief explanation of drawings]

1 and 2 relate to one embodiment of the present invention, with FIG. 1 being a circuit diagram showing its configuration, and FIG. 2 being a time chart showing its essential waveforms. FIG. 3 is a circuit diagram showing the configuration of a conventional device. 1.2...word line 3,4...bit line 5...
-Write control voltage distributor 6...Write voltage distributor X11, X12. X2
1. X22. ...Storage cell lO...Pumping circuit B, C...Field effect transistor (FET) Vc
c...First reference voltage Vpp...Second reference voltage Vw...Write voltage SR...Write signal Fig. 3

Claims (2)

[Claims] (1) A plurality of memory cells X11, X whose one end is grounded
12...X21, X22... and a plurality of memory cells X11, X12...X21, X22...
. . , memory cell groups x11 and X arranged in the row direction
word lines 1, 2, . , X12...X21, X22, memory cell groups X11,
The bit lines 3 and 4 are commonly connected to the other ends of the bit lines 3 and 4, which are selectively selected and floated to the write voltage V_W.
..., a second reference voltage Vpp higher than the first reference voltage Vcc.
a second reference voltage source 7 that supplies the word lines 1, 2,
An EPROM writing device comprising a pumping circuit 10 inserted between the word line 12 and the second reference voltage Vpp to maintain the word line 12 at a voltage higher than the second reference voltage Vpp. (2) The pumping circuit 10 includes first and second field effect transistors B connected in series via a node D between the second reference voltage source Vpp and the word lines 1, 2, . , C, and a coupling capacitor A whose one end is connected to node D and whose other end is supplied with a square wave, the gate of the first transistor B is connected to the word line 1, and the gate of the second transistor C is connected to the word line 1. The gate is connected to node D, and the capacitance CA of the coupling capacitor is CA/[CA+CD]>[VT(B)+VT(C)]/
Vpp However, Vcc...First reference voltage Vpp...Second reference voltage VT(B)...Threshold voltage of transistor B VT(C)...Threshold voltage of transistor C CA...Coupling The EPROM writing device according to claim 1, wherein the capacitance CD of the capacitor A is selected so as to maintain the following relationship: ground capacitance of the node D.