JPS58188378A - Automatic stop mechanism of tape deck - Google Patents

Automatic stop mechanism of tape deck

Info

Publication number
JPS58188378A
JPS58188378A JP57072134A JP7213482A JPS58188378A JP S58188378 A JPS58188378 A JP S58188378A JP 57072134 A JP57072134 A JP 57072134A JP 7213482 A JP7213482 A JP 7213482A JP S58188378 A JPS58188378 A JP S58188378A
Authority
JP
Japan
Prior art keywords
time
circuit
signal
measuring
recording
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57072134A
Other languages
Japanese (ja)
Inventor
Kiyoshi Kaneko
潔 兼子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Akai Electric Co Ltd
Original Assignee
Akai Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Akai Electric Co Ltd filed Critical Akai Electric Co Ltd
Priority to JP57072134A priority Critical patent/JPS58188378A/en
Publication of JPS58188378A publication Critical patent/JPS58188378A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B15/00Driving, starting or stopping record carriers of filamentary or web form; Driving both such record carriers and heads; Guiding such record carriers or containers therefor; Control thereof; Control of operating function
    • G11B15/02Control of operating function, e.g. switching from recording to reproducing

Abstract

PURPOSE:To minimize the power consumption and to attain stable performance, by limiting a time kept to the recording and reproduction waiting state and stopping the operation of the entire device for a prescribed time. CONSTITUTION:When a waiting signal representing the recording waiting state is inputted to the entire control circuit 3 with an operation key 4, the waiting signal is given to a time measuring circit 5. The circuit 5 starts the measuring of time and transmits a time signal corresponding to the measuring value to a comparison circuit 8. The comparison circuit 8 reads out the set time of a set circuit 7 and compares it with an input time signal, and when the signals are coincident, a stop signal is outputted from the comparison circuit to the control circuit 3 and a clear signal is outputted to the measuring circuit 5 at the same time. Thus, when the value of the circuit 5 is cleared to zero, no current flows to a mechanism block 1 and a signal system amplifier block 2 and all operations are stopped.

Description

【発明の詳細な説明】 本発明はビデオデツキを含むテープデツキのオートスト
ップ機構に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an auto-stop mechanism for tape decks including video decks.

側法のテープデツキは、リール台駆動機構、ヘッド台駆
動機構郷かも成るメカニズムブロックと、増幅器を含む
信号系アンプブロックと、これらのメカニズムブロック
及び信号系アンプブロックを制御する全体制御回路を備
えており、全体制御回路に入力された操作キーによる信
号に応じてメカニズムブロックの駆動機構が作動し、あ
るいは信号系アンプブロックK[流が流れるようKなっ
ている。
The side tape deck is equipped with a mechanism block consisting of a reel drive mechanism and a head drive mechanism, a signal system amplifier block including an amplifier, and an overall control circuit that controls these mechanism blocks and signal system amplifier block. The drive mechanism of the mechanism block operates in response to a signal from an operation key inputted to the overall control circuit, or the signal system amplifier block K [K is designed to flow smoothly.

ところで従来のこの種のテープデツキにあっては、記録
・再生時期状態例えば碌音時期状態にある。I#合には
、この時期状態を所定時間に制限する+段が具備されて
いないために、テープデツキの使用者の不注意等により
当該時期状態が長くなると、それに伴いメカニズムブロ
ック、信号系アンプブロックを構成する機器例えば発振
器、プランジャに無制限に電流が流れ続け、それ故無駄
な電力を消費して不経済な不具合があるとともに、この
時期状態に伴ってプランジャ、トランスを含めた装置内
部の温度が上昇し、装置内部に具備される機器、S相の
性能に悪影響を及ぼす不具合かあった。
By the way, conventional tape decks of this type are in a recording/playback state, for example, in a high-performance state. In the case of I#, since there is no + stage to limit this period state to a predetermined time, if the period state becomes longer due to the carelessness of the tape deck user, etc., the mechanism block and signal system amplifier block are For example, current continues to flow unrestrictedly through the devices that make up the device, such as the oscillator and plunger, resulting in unnecessary power consumption and uneconomical malfunctions.During this period, the temperature inside the device, including the plunger and transformer, increases. There was a malfunction that adversely affected the performance of equipment installed inside the equipment and the S phase.

本発明はこのような従来技術における実情に蟲みてなさ
れたもので、その目的は、1碌・再生時期状態が所定時
間縦続された場合に、自動的に、装置の全ての作動を停
止させることのできるテープデツキのオー トストップ
機構を提供することにあるD この目的を達成するために本発明は、F録・再生時期状
態に保持される時間を計測する時間針側回路と、あらか
じめ所定の時間が設定される設電回路と、時間計測回路
で計測された時間と設定回路で設定された時間とを比較
する比較回路とを備え、この比較回路から出力される信
号によって全ての作動を停止させる構成にしである。
The present invention has been made in view of the actual situation in the prior art, and its purpose is to automatically stop all operations of the device when the 1-perform/regeneration time state continues for a predetermined period of time. An object of the present invention is to provide an auto-stop mechanism for a tape deck that can be used for a tape deck. It is equipped with a power installation circuit in which the time measurement circuit is set, and a comparison circuit that compares the time measured by the time measurement circuit with the time set by the setting circuit, and all operations are stopped by the signal output from this comparison circuit. This is the composition.

以下、本発明のテープデツキのオートストップ機構を図
に基づいて説明する。
Hereinafter, the auto-stop mechanism of the tape deck of the present invention will be explained based on the drawings.

図は本発明の一実施例の概略構成を示すブロック図であ
る。この図において、1はメカニズムブロックで、リー
ル台駆動機構、ヘッド台駆動mw等からなっている。2
は信号系アンプブロックで、増幅器壽かも成って(・る
。3はこれらのメカニズムブロック1及び偏号系アンプ
ブロック2を制御する全体制御回路、4は全体制御回路
3に各種の操作信号を出力する操作キーで、複数のキー
から成ッテイるー、これらのメカニズムブロック1、信
号系アンプブロック2、全体制御回路3及び操作キー4
は従来のテープデツキにも具備されているもので公知で
ある。
The figure is a block diagram showing a schematic configuration of an embodiment of the present invention. In this figure, reference numeral 1 denotes a mechanism block, which includes a reel stand drive mechanism, a head stand drive mw, and the like. 2
is a signal system amplifier block, which also includes an amplifier. 3 is an overall control circuit that controls these mechanism block 1 and polarization system amplifier block 2, and 4 is an output of various operation signals to the overall control circuit 3. The operation key consists of multiple keys, including a mechanism block 1, a signal amplifier block 2, an overall control circuit 3, and an operation key 4.
is well known and is also included in conventional tape decks.

5は全体制御回路3に接続した時間計測回路で、この時
間計側回wI5には矢印6で示すよ5に記録・再生時期
状態を示す時期信号が入力可能になっている。Iは設定
回路で、記鐘拳再生時期状態に保持される時間の限界で
ある限界時間が設定される。
Reference numeral 5 denotes a time measuring circuit connected to the overall control circuit 3, and a timing signal indicating the recording/reproduction timing state can be inputted to this timer side circuit wI5 as shown by an arrow 6. Reference numeral I designates a setting circuit in which a limit time is set, which is the limit of the time that the state of regeneration time is maintained.

この限界時間は例えば10分とすることができる。This time limit can be, for example, 10 minutes.

8は比較(ロ)路で、上述した時間計測回路5と設定回
路7、及び全体制御回路3に接続してあり、時間計測b
1路5から出力される時間信号と設定回路7から出力さ
れる時間信号とを比較し、これらの時間信号の値が一致
したときに全体制御回路3に、装置の全体の作動、すな
わちメカニズムブロック1及び信号系アンプブロック2
の作動を停止させるストップ信号を出力する。なお、蚕
体制御回路3、時間計測回路5、設定回路7、及び比較
回路8によって形成される回路は、iイクロコンピュー
タによって構成することが可能である。
8 is a comparison (b) path, which is connected to the above-mentioned time measurement circuit 5, setting circuit 7, and overall control circuit 3;
The time signal output from the first path 5 and the time signal output from the setting circuit 7 are compared, and when the values of these time signals match, the overall control circuit 3 is instructed to control the overall operation of the device, that is, the mechanism block. 1 and signal amplifier block 2
Outputs a stop signal to stop the operation. Note that the circuit formed by the silkworm body control circuit 3, the time measurement circuit 5, the setting circuit 7, and the comparison circuit 8 can be configured by an i-microcomputer.

このように構成しである一実施例にあっては、操作キー
4によって例えば録音時期状態な示す時期信号が全体制
御回路3に入力されると、四時期傷号はこの全体制御回
路iを軽て時間計測回路5に送られる。時間計測回路5
は時期信号が入力された時から時間の計測を開始し、同
時に七〇計#jした値に相応する時間信号を比較回路8
に出力する。比較回路8はこの時間信号を入力した時に
設定回路7にあらかじめ設定されている時間な読出し、
これらの時間信号の値を比較する。そしてこれらの時間
(T号の値が一致した時に、比較回路8かも全体制御回
路3にストップ信号が出力され、同時に時間計測回路5
にクリヤ信号が出力される、これによって時間計測(ロ
)路5の計測値がゼロにクリヤされるとともに、メカニ
ズムブロック1及び信号系アンプブロック2に電流か流
れなくなり、全ての作動が停止する。このようにして時
期状態に保たれる時間を、設定回路Iで設定される時間
例えば10分8!度に確実に制限することができる。
In one embodiment configured in this manner, when a timing signal indicating, for example, a recording timing state is inputted to the overall control circuit 3 by the operation key 4, the four timing signal is used to lighten the overall control circuit i. and is sent to the time measurement circuit 5. Time measurement circuit 5
starts measuring time from the time when the timing signal is input, and at the same time compares the time signal corresponding to the value calculated by 70 times with the comparison circuit 8.
Output to. When the comparison circuit 8 receives this time signal, it reads out the time preset in the setting circuit 7.
Compare the values of these time signals. When these times (T values) match, a stop signal is output to the comparison circuit 8 and the overall control circuit 3, and at the same time the time measurement circuit 5
A clear signal is outputted to , thereby clearing the measured value of the time measurement (b) path 5 to zero, and at the same time, no current flows through the mechanism block 1 and the signal system amplifier block 2, and all operations stop. The time for which the period state is maintained in this way is set by the setting circuit I, for example, 10 minutes 8! can be reliably limited.

なお設定回路1において設定される時間を超えないうち
に、操作キー4によって例えば骨身継続信号が全体制御
回路3に入力された場合には、その時点で時間計測回路
5への時期信号の入力が停止されるが、例えばこのとき
同時に時間計測回路5の計測値はクリヤされるようにな
っている。
If, for example, a bone-and-body continuation signal is input to the overall control circuit 3 using the operation key 4 before the time set in the setting circuit 1 is exceeded, the timing signal is not input to the time measurement circuit 5 at that point. However, at the same time, for example, the measured value of the time measuring circuit 5 is cleared.

本発明のテープデツキのオートストップ機構は“以ヒ述
べたように、記録拳再生時期状態に保たれる時間を望ま
しい所定時間に制限し、当該所定時間に至った場合には
装置全体の作製を停止させる構成にしであることから、
従来に比べて記鎌・再生時期状態における′1力の消費
を最少−に抑制できるとともに、この時期状恕に伴って
生じる装置内部の温度上昇を防止することができ、それ
故、紅済性が同上するとともに、安定した性能を確保す
ることができる効果がある7、
The auto-stop mechanism of the tape deck of the present invention limits the time during which the recording playback timing state is maintained to a desired predetermined time, and stops the production of the entire device when the predetermined time is reached, as described below. Because of the structure,
Compared to the conventional method, it is possible to suppress the consumption of power to the minimum in the recording/regeneration period state, and also to prevent the temperature rise inside the device that occurs due to this period state. is the same as above, and has the effect of ensuring stable performance7.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明のテープデツキのオートストップ機構の一実
施例の概略構成な示すブロック図である01・・・・・
・メカニズムブロック、2・・・・・・信号系アンプブ
ロック、3・・・・・・全体制御回路、4・・・・・・
操作今一、5・・・・・・時間計銅回路、I・・・・・
・設定回路、8・・・・・・比較(ロ)路。 「=−−−−−−一−−一■
The figure is a block diagram showing a schematic configuration of an embodiment of an auto-stop mechanism for a tape deck according to the present invention.
・Mechanism block, 2...Signal amplifier block, 3...Overall control circuit, 4...
Operation, 5...Hour meter copper circuit, I...
- Setting circuit, 8... Comparison (b) circuit. ``=-------1--1■

Claims (1)

【特許請求の範囲】[Claims] 記録・再生時期状態に保持される時間な計#Iする時間
計測回路と、あらかじめ所定の時間が設定される設定回
路と、上記時間計側回路で針側された時間と上記設定回
路で設定された時間とを比較する比較回路とを備え、記
録・再生時期状態に保持される時間が設定回路で設定さ
れる所定の時間に至ったときに、上記比較回路から全て
の作動を停止させるストップ信号が出力されるようKし
であることを特許とするテープデツキのオートストップ
機構。
A time measurement circuit that measures the time held in the recording/playback timing state, a setting circuit that sets a predetermined time in advance, and a time measurement circuit that sets the time on the hand side of the above-mentioned time meter side circuit and the time that is set by the above-mentioned setting circuit. a stop signal that stops all operations from the comparison circuit when the time to be maintained in the recording/playback state reaches a predetermined time set by the setting circuit; The tape deck's auto-stop mechanism is patented to ensure that the output is accurate.
JP57072134A 1982-04-27 1982-04-27 Automatic stop mechanism of tape deck Pending JPS58188378A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57072134A JPS58188378A (en) 1982-04-27 1982-04-27 Automatic stop mechanism of tape deck

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57072134A JPS58188378A (en) 1982-04-27 1982-04-27 Automatic stop mechanism of tape deck

Publications (1)

Publication Number Publication Date
JPS58188378A true JPS58188378A (en) 1983-11-02

Family

ID=13480508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57072134A Pending JPS58188378A (en) 1982-04-27 1982-04-27 Automatic stop mechanism of tape deck

Country Status (1)

Country Link
JP (1) JPS58188378A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4635145A (en) * 1984-02-22 1987-01-06 Sharp Kabushiki Kaisha Floppy disk drive with stand-by mode
US5448427A (en) * 1989-08-21 1995-09-05 Hitachi, Ltd. Magnetic recording and reproducing apparatus

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5644A (en) * 1979-06-12 1981-01-06 Matsushita Electric Ind Co Ltd Magnetic recording and reproducing unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5644A (en) * 1979-06-12 1981-01-06 Matsushita Electric Ind Co Ltd Magnetic recording and reproducing unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4635145A (en) * 1984-02-22 1987-01-06 Sharp Kabushiki Kaisha Floppy disk drive with stand-by mode
US5448427A (en) * 1989-08-21 1995-09-05 Hitachi, Ltd. Magnetic recording and reproducing apparatus

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