JPS5818717B2 - Recurrent read/write memory that can regress embedded patterns - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to binary information storage means such as semiconductor memories, and in particular to read/write memories that contain a unique bit pattern as an initial value but can be freely written to and read from during normal operation. The present invention relates to an IC memory that can operate as an IC memory.

In other words, the IC memory provided by the present invention is, so to speak, a ROM! It has the functions of lmRAM, and during normal operation, it can perform read and write operations freely as read/write memory (RWM) or random access memory (RAM). However, when a certain configuration is commanded, it can potentially The embedded bit pattern is activated and regenerated, and prepared to be read out using normal procedures.

Conventionally, so-called ROM and RWM have been designed, manufactured, and used as completely different types of ICs with mutually different structures and manufacturing processes.

Therefore, in a simple data processing system such as a μCPU system, especially when an external storage device is not used, the address space occupied by ROM and RAM (RWM), which are directly connected in hardware, is unique to the system and unchangeable. , the address space occupied by the ROM containing the system program cannot be used as a data buffer or work area.

This is extremely uneconomical from the standpoint of utilization of the address space available to the μCPU, which is otherwise relatively small.

Generally speaking, the program running at a given moment is only a small part of the entire system's program, and it is always a program that has little to do with the current work or is permanently resident, which takes up a lot of work space. This is because it becomes narrower.

In view of such circumstances, the present invention provides RW during steady operation.
The present invention aims to provide a new type of IC memory that can be used as M or RAM, but whose unique embedded pattern can be instantly recalled and used when necessary.

By using a RAM that has such embedded pattern recollection ability, there is no need to use pure ``hard'' ROM to set startup programs and initial values of data, and the address space can be used as a work space during normal operation. It offers the convenience of being used as a

This is particularly advantageous in small systems with limited address space.

Furthermore, even if the data processing is not limited to a particularly small scale, when processing data that is particularly high-speed and highly mobile, it is important to consider the initial The IC memory according to the present invention also eliminates the need to re-roll in data, initialization or diagnostic programs from an external storage device.

That is, the embedded pattern recallable RAM according to the present invention
(Hereinafter, this will be referred to as regression memory or REM;
entMemory;) is the normal R
This is achieved by "embedding" a reversible bias pattern into each memory cell of the AM using a procedure that does not interfere with normal operation.

This bias pattern can be applied to flip-flop circuit elements, which have a completely symmetrical electrical and/or physical structure in the case of a normal RAM, by using various methods such as those described below, or variations or combinations thereof. This is achieved by applying

The biased pattern in this manner is completely harmless while operating as a RAM under a given power supply condition, but some or all of the power supply or bias is reduced or increased, and each flip-flop (memory When it becomes difficult for a cell (cell) to maintain its own logic content, or when there is a transition state that should be passed when rising from a no-power state, the memory cell is recursively introduced into the flip-flop of each memory cell.

That is, the method of asymmetricalization is as follows: (a) β or gm of one transistor of a flip-flop forming a memory cell is made significantly different from that of the other transistor.

(b) Similarly, pinch-off voltage or Vg~Id
make the characteristic curves different.

(c) Similarly, insert a diode or resistor, etc., in series with one of the electrodes of one of the transistors.

(d) Similarly, the load resistance or bias resistance, or the supply current of the active load is made different.

There are other methods.

Furthermore, this type of REM can also be realized by separately wiring a special return command line and energizing this line to set or reset each memory cell according to a predetermined pattern.

That is, (e) wire one "current line" to reach each cell, and as soon as this line is energized, all cells are immediately cleared to the same logic level, and then At the moment when the energization is released, the transition state as described above is passed through, and the bit pattern to be returned is called out somewhere in each cell or in particular, the bit pattern embedded by being connected to this regression command line.

This method may also be used.

However, even without rewiring the cant line (regression command line) and in a steady state (without intermittent power supply), carriers that would not normally exist within the chip can be generated by light energy, etc. By doing so, it is possible to bring about a transition state in the same sense as above, and to bring about regression of the embedded pattern.

That is, (f) irradiate the chip with light of necessary and sufficient illuminance all at once to generate photoexcited carriers almost uniformly, bring both transistors of the flip-flops of each memory cell into the ON state, and then stop the light irradiation. The embedded pattern prepared in any of the forms described above is caused to regress during the transition state that passes immediately after.

(g) In particular, - preparing a pattern with a light-blocking substance on the pattern of the chip, selectively exciting a specific region or a specific transistor through the pattern, and subsequently, while the light is being reduced or immediately after being blocked; During the transition state where the light shielding layer passes through, the embedded pattern defined by the light shielding layer is caused to regress.

This kind of REM or regression memory can also be realized by other methods.

Although each of the above methods can be applied when the memory cell is in the form of a flip-flop, they are essentially charge sample and hold methods, i.e. dynamic methods such as one transistor/cell structure (periodically It can also be applied to memory (requiring refresh) with necessary modifications.

In particular, in that case the refresh command is preferably given in conjunction with or instead of the refresh command.

However, especially in this type of dynamic RAM type, (h) the embedded pattern is used to determine the "charge holding capacity" of the sample-and-hold transistor of each memory cell, that is, the time constant of potential dissipation, for example, the recombination speed, that is, the impurity distribution, etc. embedding by coding the factors.

In order to regress this, by applying 1 (high potential, or full charge) to all cells and then waiting much longer than the normal refresh cycle, the remaining charges and the This pattern is obtained as a distinction from cells that disappear below the threshold.

This method is possible.

Of course, writing all 1's here may be performed by optical excitation, and each of the above methods, whether static or dynamic, can also be implemented in a serial memory such as a shift register, which is not a random access method.

On the other hand, as precedents that can be classified as 'REM', we will introduce some primitive ideas that are less practical.

First of all, the idea of setting a single flip-flop to a certain logical value whenever the power is turned on is found here and there.

For example, in Utility Model No. 52-54269 devised by Mr. Totsuka, programmable "geta" or unbalanced elements can be obtained by varying the number of diodes inserted in series with the emitters of each transistor in a flip-flop circuit. ing.

However, his idea was to program flip-flops one by one using jumper lines, and he did not come up with the concept of embedding a bit pattern.

Furthermore, in Japanese Patent Application Laid-open No. 50-11754, which was invented by Mr. Nomiya, the above-mentioned "geta" was achieved by varying the threshold values of MISFETs.

However, it still only deals with a single flip-flop.

On the other hand, instead of handling flip-flops individually, as a memory capable of accommodating some kind of bit pattern, RAM and ROM or EAROM as physical means are provided separately and used while being switched appropriately within the same address space. For example, so-called backup type non-volatile RAM or non-volatile counters or registers have been commercially available for a long time.

For example, Toshiba's TMM142P falls under this category.

Also, ``mixed memory'' can be shared by RAM and ROM.
This idea was published as an invention by Torii Shiki et al.
seen in

However, his method is limited to RAM and ROM (EARO).
The true nature of M) is that although it is integrated on the same chip, it exists independently and separately, and only uses a special discrimination circuit to distribute signals, and each memory cell is assigned to RA.
It is not possible to perform both the operation of M and the embedded pattern regression operation here.

The idea of sharing the same memory cell for RAM and regression operation is proposed in US Pat. Nos. 3,662,351 and 3.
Seen in No. 757313.

The former is ■.

In Mr. T-Ho's proposal, a drain terminal is used as an unbalanced element so that each flip-flop is preset to a predetermined polarity when the power is turned on or when the voltage is boosted between two predetermined supply voltages. It takes advantage of the difference in capacitance imposed on .

Although his proposal has the feature that DC operation can be the same as the normal case, it cannot be denied that high-speed operation as a RAM is hindered by the intended balance of this stray capacitance.

On the other hand, the US% license proposed by H-W-Hines et al.
In No. 757313, how the memory cells are preset is essentially done by wiring, so the wiring on the chip becomes unnecessarily complicated, making it impossible to increase the density.

The regression operation involves directly writing a bit pattern prepared in a wiring manner to each cell.
Each cell is essentially uniform and has no bit pattern embedded within itself.

In the following, improved embodiments of some of the important methods described above will be introduced.

First, FIG. 1 is a circuit diagram showing a cell with a bipolar REM as an example.

This basic structure is a flip-flop 1 formed by Ql and Q2.
1, Q3 and Q4 are constant current sources.

This basic structure itself is nothing but a well-known general-purpose memory cell, but R61e R, which is not normally adopted,
32 or Re1 s Re2 etc. are incorporated.

These series resistances have a sufficiently small value and do not affect normal RAM operation.

Even if they are intentionally unbalanced, a sufficiently stable unbalance can be embedded in the read circuit and write circuit (not shown) placed at one end of the bit line, and When creating an unbalance in Re□, 2, which defines the collector current of both transistors, since the current-voltage relationship of transistors in the same position in the same substrate is relatively well matched, the steady state Even if the current is unbalanced by at most 2 to 3 currents, it is possible to provide stable embedded information as described above.

This also applies to Rb.

In order to recover this embedded information, it is possible to temporarily turn off the power and then turn it on again as described above, or to use the bias bus line Q that biases the constant current sources Q3 and 4 as shown in the figure. Apply a negative pulse to the terminal Re with a potential lower than 10VCC by two terminals (approximately 1..2v) specified by D□Q
This can also be done by momentarily shorting to +VCC due to the action of .

At that moment, Q3, 4, and Ql, 2 as well, are no longer able to pass their collector currents, so the information they held is lost, and is subsequently absorbed by the collector current again into its noise margin and threshold gap. This will cause no effect.

Here, making it unbalanced means, for example, R81,
If either of 212 is omitted or shorted, it becomes 75A.
Parallel (or series) to either Re 1.213
In addition.

The solution is to add Re3 or the like.

Also, both transistors Ql-21 forming a flip-flop
This unbalance can also be obtained by passing a relatively high resistor R6 from the power supply bus +VCC towards either lao collector of 1.

Therefore, in situations where these imbalances exist, this flip-flop will always transfer its base to one side, that is, to the earlier or larger current, as the power supply bus VCC rises from zero to the specified voltage. The transistor that is biased is set to the ON state.

This means that in the steady state with respect to the presence or absence of RB 1 s 2, a fraction of Vbe, that is, a high
When the value of R81#2 that causes a potential difference of about mv is already given, as mentioned above, the one that is easier to ONL is ONL first, and the embedded information is activated and regressed, as usual. It is prepared so that it can be read out via the bit line.

The above example mainly shows a method of coding the embedded pattern by the value of the resistance in the circuit, but although it is not shown in the diagram, this method involves intentionally making β of Ql and Q2 different, or using the same bias current. This can also be done by making their physical dimensions larger or smaller in order to provide different current densities.

However, making transistors with different dimensions is not preferable as it will have a large effect on masks and other parts throughout each diffusion process, so it is necessary to make R55Re etc. contribute to the circuit by extending or shortening the wiring pattern, or to remove it. It is much easier to encode the embedded pattern with just a few modifications.

According to this method, uniform chips are prepared and small-volume production is possible in which only the final wiring layer is encoded according to the order, and it is possible to realize the same flexibility as a normal mask ROM.

Furthermore, as shown in Figure 2, diodes 22.2 are placed at key points.
3 can also be added to the load resistance Rc1 = 2 2
Making the values of 1 significantly different is also effective as a method of encoding embedded patterns.

In this case, if a potential difference equivalent to one PN junction is applied to the emitter side, it will result in too large an imbalance, and R
It is preferable to use a Schottky barrier diode or an amorphous diode instead of a PN junction diode because there is a possibility that writing and reading functions as an AM will be impaired.

Even when diodes are used in this way, encoding of the embedded pattern can be performed with the same flexibility as mask ROM by creating diodes on both sides and selectively shorting them when forming the final wiring layer. obtain.

Next, FIG. 3 shows an example of REMO using the MO8 structure (Q□ to Qa are all enhancement types). In this case as well, Re1y
In addition to embedding unbalance using 234 or Re1y234, the pair of Ql t 2 or Q
By making the pinch-off voltages different between 3 and 40 pairs, it is possible to effectively compensate for the unbalance.

Modification of the pinch-off voltage for this purpose can be achieved by trapping charge carriers on the insulating film of the gate or on the conductor strip of the gate itself as a floating structure.

This is realized using a structure and programming procedure that are exactly the same as the well-known MNO8 structure, FAMO8 structure, floating gate structure, or stacked gate structure EPROM (electrically programmable ROM).

However, the purpose here is REM, and R
Since it is not OM, the RAM (RWM) during normal operation
In order to ensure proper operation, it must not be programmed as tightly as in pure EPROM.

Therefore, although the general structure and programming method are similar to any of the above-mentioned EPROM methods, the nitride layer (in the case of MNOS), the position, thickness, effective area or It is necessary to control the degree of contribution to the channel (isometric gm) to an appropriate value1-1.If necessary, it is also necessary to control the amount or density of trapped charge carriers to ensure operation as a RAM (RWM). .

However, analog control of the amount of charge carrier supplementation is generally quite difficult.

Therefore, it is preferable to define the above-mentioned degree of contribution mainly based on only the mechanical positional relationship of the charge trap to be programmed (nitride layer, floating gate, stacked gate, etc.) with respect to the channel as a determining factor.

That is, specifically, only a part of the channel is covered with these programmed charge traps, while other parts are not affected by the charge at all, and the RAM (RWM)
It is preferable to configure it so that it continues to exist as an active element that is a component of a flip-flop that guarantees operation.

In any case, as mentioned above, there is an imbalance of about 20 to 30% of gm between Qt and Q2 (Fig. 3), or a pinch-off voltage of 200 to 300 mV (■
Programming as described above, which can be equivalent to an unbalance of about 5mm (assuming the potential of CC to SSs as 5mm), is quite effective as an embedded pattern, and does not impede steady operation as a RAM (RWM) at all. be.

If a structure in which such a charge trapping body is arranged at the gate is adopted, this REM becomes capable of electrically writing a buried pattern.

This is exactly the case with the various "pure" EPROMs discussed above.

Furthermore, erasing during rewriting can be similarly performed electrically or using ultraviolet light.

The above-mentioned structure, which should be called EPREM, can of course be implemented alone, but it is a mask REM structure, that is, a REM structure having a pattern embedded in an unerasable manner by any of the above-mentioned methods. By adding the EPREM structure on top of the above, the embedded pattern given in Ready Mate can be partially or completely rewritten as needed, thus reducing the user's power. A convenient EPREM can be realized in which the old embedded pattern can be erased using ultraviolet light or the like to return to the originally existing ready mate embedded pattern.

In this case, if the user (user) writes more 1s or 0s into a cell in which 1s or 0s have been embedded in the ready mate, it will result in an imbalance in any of the above senses, or an excessive It becomes too much, and the RAM (R
Therefore, it is preferable for the user to modify only the cells that need to be modified within a given embedded pattern.

Therefore, the level of the "geta" freely pressed by the user is almost twice the level of the geta provided by the readymate (converted into "differential input" for each flip-flop).
This is preferable in order to minimize the possibility of interference with RAM operation due to waste or unbalanced components.

This is because the amount of 2@ that should be canceled out is a necessary and sufficient amount in order to cancel out the Readymate component and make the wearer wear clogs of the same height in the opposite direction.

Therefore, the RE according to the MO3 structure shown in FIG.
In the case of M or EPREM, in addition to turning on and off the entire power supply, the return command is to turn the bus of Vss shown in the figure to Vs
It can also be performed by instantaneously pulling down to Vss (or ground, usually Vss - used as ground).

Furthermore, in the example shown in the figure, Q3 and Q4 are of the enhancement type, but it is also preferable to use a derejection load in order to further increase the speed.

In that case, the bus bar of vGo can be omitted and each gate is directly connected to the source.

Furthermore, it is of course possible to use a mere resistance as a load instead of an active load.

In either case, the procedure for realizing the embedded pattern can be carried out in essentially the same manner as described above.

On the other hand, FIG. 4 again shows an example of the bipolar structure REM, 7), but in this case, it is the optical energy 42.43 selectively applied to each transistor that provides the buried pattern. The choice is light shielding mask 44
This is done by

The return command is also executed by exciting the bias generating transistor Q with the same light energy and momentarily shorting the bias bus to vCC.

That is, after the bias current is lost and all cells are cleared, when the bias condition is restored again, the transistor on the side that is selectively irradiated with alternating current or the transistor on the side that is biased by the transistor , a bit pattern is developed in the cell group so that the bit pattern becomes ON.

Here, although the mechanical structure is not shown in FIG. 4, the light-shielding mask 44 is made by attaching a transparent layer of an appropriate thickness to the wafer after all processes such as diffusion, wiring, and overlay have been completed. It is obtained by laminating a photosensitive insulating layer and depositing a thin metal film on top of the layer.

As this light-transmitting insulating layer, a 5i02 film formed by vapor phase growth or low-temperature thermal oxidation, a fusion layer of low-yield glass, or a film of epoxy resin or polyimide resin can be used.

Further, the appropriate thickness is 1 μm to several μm.

This film can be considered in the same way as passivation on the surface of a chip.

In particular, when resin is used, it is advantageous in the subsequent formation of a light-shielding mask because it absorbs the unevenness of the surface of the chip and provides a flat surface.

On the other hand, the light-shielding mask may be formed in the same way as a normal aluminum or gold wiring layer.

A buried pattern may be formed using a vapor deposition mask, but
It is also possible to form a buried pattern by photo-etching after forming a metal layer on one surface, which is more suitable for small-scale customization.

Furthermore, the material of the light-shielding mask is not limited to metal, and of course any light-shielding material that can be formed as a stable and harmless film in this area may be used.

However, if a conductor such as metal is used, it is preferable to ground its potential to eliminate unexpected disturbances.

In the case of REM, which uses such a luminous flux as a return command, it is difficult to perform the return operation by providing a translucent window above the chip when mounting the chip, and shining flash light through this window. I can do it.

However, it may be housed in a light-shielding package together with one or several LEDs (light emitting diodes) while being optically coupled.

One feature of such a photo-excited REM is that it can ensure that there is no unbalance anywhere on the circuit in the dark state, and therefore, regarding steady operation as a RAM (RWM) in the dark state, Normal RA without any interference
The point is that exactly the same operation as M can be guaranteed.

By the way, Figure 5 shows a one-transistor/cell structure;
This figure shows a channel silicon MOS dynamic RAM, in which a is its circuit diagram and b is a cross-sectional view.

When the switch transistor Q150 is turned on, the capacitor 51, which is a memory cell, is connected to the read/write line 53, and the charge that is to be held or has been held is exchanged.

Specifically, a polysilicon gate 55, which is also a word line, is formed on the chip surface between the source 53 and the node 52.
is formed.

This node 52 is formed as an n+ diffusion layer like the source 53, and receives positive carriers (holes) from the source 53 through the channel 50, that is, from the bit line 53, and is applied to its surface and surroundings. Fill it up.

At this time, immediately adjacent to this node 52, a polysilicon layer 56 connected to Vdd acts on the substrate surface in the same way as the gate 55, so a surface inversion layer 51 is generated on the substrate surface layer below it. The carriers injected into the node as described above are mainly stored by this inversion layer 51.

Opposing negative carriers (electrons) are also induced on the opposite side of the polysilicon layer 56 at the VDD potential, but since the insulation of the oxide layer between them is excellent, carriers are not directed in that direction. No discharge occurs at all.

However, on the other side, toward the back of the p-substrate of the chip, there is only the boundary of the inversion layer and the pn+ junction of node 52, so carriers are lost due to thermal excitation, recombination, and other reasons. go.

Because of the finite lifetime of the carriers, this type of dynamic RAM requires refreshing, but the lifetime, or equivalent time constant, is largely dependent on these local physical conditions.

That is, by changing the lifetime of this carrier for each memory cell, it is possible to embed the embedding pattern by changing the length of the carrier half-life.

That is, the dimensions (width, depth) and position of the node 52, or the effective area of the inversion layer 51, that is, the polysilicon layer 56.
This can be done by modifying the effective area of, etc.

However, the most effective method is to change the impurity concentration near the inversion layer 51, and this method can also modify the equivalent depth of the inversion layer.

This modification of impurity concentration can be effective even if it is only slightly, and if atoms that can become donors are distributed by diffusion or ion implantation, so as to form a very thin neutralization layer or a single layer on the surface or shallowly inside. good.

Thus, the charge half-life of a cell subjected to such treatment will be shorter than that of a cell not subjected to such treatment, but it can be made sufficiently longer than the refresh period of normal dynamic operation.

In general, a dynamic RAM with a one transistor/cell structure with a capacity of about 4 to 16' is 1 to 2 m5ec.
It is specified that the maximum refresh cycle is approximately 100 m5ec at room temperature, and 70° at the maximum operating temperature.
Even around C, it has a retention capacity of about 10 m5ec.

Therefore, even if the performance is degraded by half or one-fourth, operation as a dynamic RAM can be ensured with sufficient safety.

The operation of reverting the embedded pattern in a MOS dynamic RAM having a one-transistor/cell structure in which the embedded pattern has been embedded in the form of a half-life of a charge as described above is performed as follows.

Also, Figure 6 a, b, and c are countries for explaining this.

That is, all cells are first set to 1, that is, to a charged state.

This is an internal state of 1, and does not mean a logical state that provides 1 to the read output terminal.

If you place a sense amplifier in the center of the chip, as is often done, and try to use the differential input of the sense amplifier effectively by using positive logic and negative logic on the left and right sides, the state with charge will change to 1 for each address. The difference is whether it is output or 0.

Therefore, keep this in mind when writing so that all cells are photoelectrically charged.

Of course, this can be done quickly by writing using -h addressing, or by using a refresh mechanism and executing row by row as a group.

Further, a dedicated control circuit for simultaneous photoelectric control may be provided on the chip.

That is, in Fig. 6a, Q2 aj b and Q3a, b
A total of 41 transistors form a flip-flop that functions as a sense amplifier, and after being neutralized by Ql at a timely timing, it receives the potential of one of the holding capacitors C8 to C63, and receives the potential at the falling edge of Δ. At that time, the potential settles into a logic state corresponding to whether it is above or below a threshold level defined by the precharge voltage generator PVG.

Here, when any one of R8-R31 is selected, the dummy on the right is used for comparison, and when any one of R3□-R63 is selected, the dummy on the left is used for comparison. In the former case, there is a charge. In contrast, it is positive logic, and in the latter case it is negative logic.

(The write amplifier is omitted and not shown.

) In other words, when Q4, which is intervening at the lower end of the flip-flop forming this sense amplifier, is turned off and the state is 1, the entire sense amplifier becomes a high potential, and R
C6-C6 according to o-R63 scanning or simultaneous energization
It is also possible to photoelectrically charge g to a high potential.

This C4 is always kept on during normal operation, and therefore its gate acts as a terminal for accepting simultaneous photoelectric commands.

Therefore, if we wait for a certain period of time without performing any refresh after photoelectric charging all at once, all the cells whose charge retention time has been shortened as described above will become zero (in the internal logic) and will not be subject to such correction. The cells are all 1 and each state as observed is realized.

Therefore, if normal operation is resumed from this time and refresh and random access reading as required are started, the bit pattern that has been accommodated and is being read out will be exactly the embedded pattern.

The appropriate timing as described above is either self-evident as shown in FIG. 6, or it cannot be unambiguously defined because it varies widely depending on the temperature of the chip.

Therefore, a circuit like the one shown in Figure 6C (this is just an example) is provided somewhere on the chip so that the average value of the holding voltages of both the long time constant cell and the short time constant cell is a predetermined logic threshold. Find the time when the voltage crosses and return to normal operation.

That is, in FIG. 6C, when the above-mentioned simultaneous photoelectric command is applied to the leftmost input terminal, C1 and C2 are photoelectrically charged to Vdd, and thereafter gradually discharged.

Here, if C1 is treated as described above and has a short time constant, and C2 is an ordinary capacitor (both are created at the same time as each memory cell), then C2a and C
The combined drain current of 2b is controlled by the average value of the potentials of the capacitors above the spark path.

Here, Re1,2 is for adjusting the apparent grn- of C2at b to obtain a response to the above average value.

However, this does not make much difference even if Re1 = Re2 or both are zero (omitted).

Therefore, if the ID5S (i.e., the scale factor) of the active load Q3 is set appropriately, the average value of the potentials of C1 and -C2 is exactly the logic threshold, since in this case it is made on a silicon substrate by an N-channel silicon gate process. The pinch-off voltage (each transistor is an enhancement type transistor) is around 1.2V, and when it drops to that value, C4 turns on and O is output to the output terminal.

That is, while using the simultaneous photoelectric command as a trigger input,
The circuit of FIG. 6C acts as a variable time (temperature, etc.) timer.

Therefore, if refresh is intentionally prohibited during the period when 1 is generated at the output terminal, then according to the purpose explained earlier, the optimum timing will be determined taking into account all factors including chip temperature and manufacturing variations. , it is possible to move on to a refresh operation to supplement the regressing embedded pattern.

However, the method shown in FIG. If there is a sufficient time constant difference between the short cylindrical cells, the embedded pattern can be safely returned.

Furthermore, instead of performing the regression operation on the entire chip, it is also possible to selectively perform regression on only cells on a certain row that are required, for example, using exactly the same method.

In the meantime, as long as that row is not accessed or refreshed, the rest of the chip will function perfectly normally.
Access as AM is possible.

In addition, in the above explanation of the method for configuring the MOS dynamic REM, physical factors of the semiconductor forming the cell are used to modify the time constant of the hold capacitor or the half-life of carriers, which is the memory cell, according to the pattern to be embedded. Alternatively, as in the case of the bipolar REM described above, carrier pairs may be generated by selective optical excitation.

In that case, as in the case of the above-mentioned bipolar REM, a light-transmitting uneven absorption/hashivation layer (
58, Fig. 5b) is formed in the same way as a general IC, and a light-shielding material layer (not shown) is formed thereon, and this light-shielding layer (aluminum film, etc.) is deposited during vapor deposition. Programming is performed according to the pattern to be embedded using a mask or by a method such as photoetching after uniform vapor deposition or plating over the entire surface.

That is, the cell's holding capacitor, node 52 or inversion layer 5, which is to provide an internal logic zero (no charge)
A light flux is selectively introduced into the vicinity of 1, and cells to which an internal logic 1 (charged) is to be given are completely shielded from light.

According to this configuration, the regression operation starts with all 1s, that is, photoelectricity of all cells, as in the case of the above-mentioned impurity concentration correction method, but immediately after that, there is no need to wait any time and the return operation can be performed via the above-mentioned "program". When an appropriate amount of light is irradiated, the buried pattern is immediately captured as a charge pattern of each cell, and becomes a target for reading and refreshing.

The optical excitation regression type REM having such a configuration is mounted in a light-shielding container together with a light source means such as a light emitting diode, or by covering the container with a light-transmitting lid.

By the way, in the above explanations of each type of REM, we have explained that the base RWM is RAM in each case, but these structural concepts are not necessarily limited to RAM, but also include shift registers, FIFO stacks, etc. It is obvious to those in the same industry and experts that the same applies to

In addition to bulk silicon single crystal, the material of the semiconductor substrate may be an SOS (silicon on sapphire) structure, and it is also obvious that a single or compound semiconductor other than silicon may be used.

In addition, in the light-excitation REM in which holes cut in a light-shielding mask are used as an embedded pattern as described elsewhere, in addition to filling the holes by vapor deposition or photo-etching through a mask, the holes are completed and equipped with a light-transmitting header. The user programs an unprogrammed REM with a uniform light-shielding mask mounted thereon through a translucent header using a laser beam or the like, i.e., the user programs the unprogrammed REM with a mounted light-shielding mask that is uniform over its entire surface. User program pull RE using the method of punching a hole in the mask
It is also possible to configure M.

The 'REM' introduced above can ultimately be implemented in one of the following ways.

(1) The address selection (addressing) mechanism enables the same precept,
Alternatively, in a (monolithic) memory device formed on a single semiconductor substrate configured to hold a pattern of bits or groups of bits that can be accessed as a group, each memory cell has a logical address. It has at most one physical unit storage means (memory cell) for each bit while having a one-to-one correspondence with the physical address, and during normal operation, it An operation of writing or reading a logic value according to a scheduled procedure, and cells that are not selected during the period, or all cells or the logic values held by the cells during a period in which no read or write operation is performed, do not essentially change, However, when an embedded pattern regression command is received chip-wide or only locally on the chip, the memory cells of fmh are filled in for all cells in that area, regardless of the bit pattern they currently contain. The unique bit pattern, which is directly or closely imprinted and embedded in advance, is silent during the normal operation and is not actually involved in read/write operations, so that it can be read out by a normal read procedure. A semiconductor memory device characterized in that it is configured to be activated and reproduced as a bit pattern formed by an actual logical value held in each cell.

(2) In the memory device shown in (1) above, each of the memory cells is constituted by one static flip-flop, and the embedded pattern is a RAM or RWM during normal operation with respect to each of these flip-flops. Intentionally unbalance the inherent parameters of the component transistors (bipolar type or type effect type) or their bias conditions or load conditions to the extent that they do not interfere with the operation of the device. Elements can be defined as physical or property parameters such as the structure, dimensions, and impurity distribution state of the transistor, or the circuit configuration and circuit constants of the flip-flop, or uniform or selective factors for the transistor or the semiconductor material in its vicinity. It is characterized in that it is carried out by applying it by a method such as optical excitation.

The semiconductor memory device. (3) In the memory device shown in (1) above, each of the memory cells is constituted by a charge sample and hold means as a dynamic memory means, and the embedded pattern is formed by a hold held by the charge sample and hold means. The charge extinction time constant of a capacitor is determined by the conductivity or charge transport ability of the main dielectric material forming the capacitor or the material placed closely thereto,
It is characterized by being carried out by modifying the frequency of disappearance and generation of charges, etc. by selectively adding impurities, changing the shape, dimensions, etc., or by nonuniform or selective photoexcitation. , the semiconductor memory device.

In other words, as clarified by the above explanations, the REM or recursive memory according to the present invention does not require new materials or manufacturing processes, but it is a semiconductor IC memory with a completely new operating mode. As such, it enables new highly efficient logic methods for data processing systems in general, and its contribution is significant.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 both show an example of a memory cell circuit in a bipolar type REM according to the present invention. FIG. 3 similarly shows an example of a MOS static type. FIG. 4 again shows an example of the bipolar configuration, particularly the photoexcitation type. FIG. 5a is again of the MOS type, but in this case it is an example of a dynamic structure. Also, the same is a schematic diagram showing a cross section of an example of the actual product. Figure 6a shows one unit of sense amplifier and all-one write logic in the same y'DS dynamic type REM, and Figure 6A shows the principle of cell programming, and Figure 6C shows the regression operation. This is an example of a timer that generates the necessary optimal timing.

Claims (1)

[Claims] 1 formed on a single semiconductor substrate (monolithic) configured to hold a pattern of bits or groups of bits that can be accessed side by side or as a group by an address selection (addressing) mechanism A memory device in which each memory cell has at most one physical unit storage means (memory cell) for each bit, with a one-to-one correspondence between a logical address and a physical address, and in which a memory cell is provided for each bit during normal operation. A logical value is written to or read from a selected cell according to a scheduled procedure based on address information, and cells that are not selected during that time, or all cells that are not read or written, retain their values. does not essentially change the logical value of the bit currently being accommodated for all cells in that area, but when the embedded pattern regression command is accepted chip-wide or only locally on the chip. Irrespective of the pattern, unique bits that are directly or closely imprinted and embedded in individual memory cells in advance, and that are silently ignored during normal operation and do not actually participate in read/write operations. A semiconductor memory device characterized in that the semiconductor memory device is configured such that a pattern is activated and reproduced by a bit pattern formed by an actual logical value held in each cell so that it can be read by a normal read procedure, wherein each memory cell has the following characteristics: Each of the charge sample and hold means is configured as a dynamic memory means, and the buried pattern is configured to adjust the charge extinction time constant of the hold capacitor of the charge sample and hold means to the main dielectric material of the capacitor or to the charge sample and hold means. This is done by modifying the conductivity or charge transport ability of the placed material, or the frequency of charge disappearance/generation, etc., by selectively adding impurities, changing the shape, dimensions, etc., or selectively excitation with light. The semiconductor memory device, characterized in that: