JPS5818690A - Melody performer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a melody performance device that stores data for controlling the performance order of segno, repeat, etc. together with sound data, and thereby controls the performance order and generates a melody. be.

The melody playing device can be used as a watch or clock alarm,
It is used in a variety of places, such as the entertainment function of calculators and the sound function of game machines. However, these only store sound data including scale data and note length data or rest length data, and the performance time is often relatively short due to the storage capacity of the memory, and the performance itself is monotonous. I had a dislike for it.

The present invention is capable of storing and playing the musical score of a song to be played exactly as the musical score, including the symbols that control the playing order, is designed to effectively utilize memory, and allows one song to be played with a small capacity. Alternatively, the present invention provides a melody performance device that can play a plurality of songs and is suitable for use in semiconductors.

Symbols that control the performance order are shown in Figures 1 (a) to (d), for example.
There are some as shown in the figure below, and the numbers indicate the order of performance. In addition, as will be explained in detail later, Fine
...end, D, C, (dakabo)...from the beginning.

D, S, (Dulceini = 1)... From the symbol (g-),
It is.

As a melody performance device, a so-called "semiconductor karaoke" has a replaceable semiconductor memory that stores musical score data of a song, and plays back and performs a song arbitrarily selected from among multiple songs stored in one semiconductor memory. ” device is proposed. Hereinafter, as an embodiment of the present invention, an application to this semiconductor karaoke will be described.

FIG. 2 shows a configuration diagram of this device, which includes a music playback control semiconductor element 1, a cartridge-type music data semiconductor element 2,
Keyboard 3 for specifying the tempo, tone, etc. of song number 2
, an amplifier 4 and a speaker 5. The song playback control semiconductor device 1 is composed of, for example, a one-chip LSI, and the song data semiconductor device 2 is composed of, for example, a cartridge-type ROM (read-only memory, hereinafter simply referred to as melody ROM). Ru.

FIG. 3 shows a more detailed block diagram of the semiconductor device 1 for music playback control.

Cartridge-type melody RO that stores multiple songs
After inserting the M2 into the device and making preparations for normal operation such as turning on the power switch, specify the top address where the desired song is stored by operating the song designation key. When the start key is turned on, the melody ROM 2 is sequentially read out and a melody is emitted. The data structure of the melody R6M2 is allocated to 16 pits as shown in FIG. 4, and the contents thereof will be described later, but the outline of the semiconductor device 1 for music reproduction control shown in FIG. 8 will be explained below.

<General description of the semiconductor device l for music playback control> By turning on the start key, a signal is generated from the input signal generation circuit 11, the gate circuit 12 is turned on, and the output signal of the oscillator/frequency dividing circuit 18 is generated as a subsequent signal. The signal is input to the tempo determining frequency divider circuit 14 and tone generator +5.

When the start key is turned on, the output of the address counter 16, which specifies the address of the melody ROM 2, indicates the start address of the desired song, as described above. The content of the start address of the song in melody ROM 2 is 111 set in the most significant bit (16th bit) F, and the data in this lower bit is not the scale or note length data, but the tempo and rhythm data of the song. Show that something is true. Therefore, at this time, the scale decoder 17. connected to the data output bus of the melody ROM 2. It is not input to the note length decoder 18.

The contents of the first address / are stored in the tempo decoder 19. The data will be input to the rhythm decoder 20, and the tempo and rhythm of the entire song will be determined according to each data.

The tempo decoder 19 determines the shortest note length together with the tempo determining frequency dividing circuit 14 and the minus number circuit 21, and the output signal of the minus number circuit 21 becomes a clock signal for the note length frequency dividing circuit 22 at the next stage. In addition, in this embodiment, the tempo decoder 19 is a programmable decoder that has an addition/subtraction circuit configuration in addition to a latch function for holding, and performs addition/subtraction using a control signal from the input signal generation circuit 11 based on input from an external key.
You can change the tempo arbitrarily.

The rhythm decoder 20 determines the rhythm of the song based on the input data, and the rhythm generator 28 in the next stage generates the rhythm. Rhythm is used as an accompaniment when playing a melody. This rhythm decoder 20 also has a latch function.

After reading the first address, the control section 24 generates a new pulse after a predetermined period of time, inputs it to the address counter 16, and advances the contents of the address counter 16. The contents of melody ROM2 at the next address are the topmost bit)
Since F is %61, the lower bit data represents scale and note length data.

The note length data is input to the note length decoder 18, and in the matching circuit 25, it is found that the data matches the divided output of the note length frequency dividing circuit 22. That is, here, the tempo determination circuit (
Tempo determining frequency dividing circuit 14° tempo decoder 19. -Based on the shortest note length determined by the numerical circuit 21),
A note length corresponding to the note length data is determined. When the frequency divisions match, the note length frequency division circuit 22 is reset by the output signal of the minus number circuit 25, and one pulse is input to the address counter 16 through the control section 24 to advance the address designation by one.

Further, until the frequency divisions match, the tone generator 15 generates a frequency signal of the corresponding scale according to the scale data input to the scale decoder 17. The scale decoder I7 also has an addition/subtraction circuit configuration in this embodiment, and adds/subtracts the binary signal via the input signal generation circuit 11 by operating an external key, making it possible to transpose and transpose the key. The envelope generation circuit 26 is used for various musical instruments. The instrument type is selected and specified via the input signal generation circuit 11 by operating an external key. Then, the second bit AK' read from the melody ROM2
When l' rises, the control unit 2.4 detects this and outputs an envelope signal to apply an envelope to the corresponding scale note. 〇 Frequency signal corresponding to each scale, envelope signal, and rhythm generator The rhythm signal outputted from 23 is mixed in a mixing circuit 27, and is emitted as a melody sound through an external amplifier 4 (see FIG. 2) and a speaker 5.

Data structure of melody ROM2> The melody ROM2 is allocated to 16 bits as shown in FIG.

bit) is for control, A bit (11th bit)
9 to 8 bits are for octave, 7 to 8 bits are for octave,
4 bits are for note length, and 8 to θ bits are for scale. However, depending on the control contents of the F bit to B bit, the lower bits below A are shared with other things.

When the F bit to B bit are all 10', the A pittle 0 bit represents sound data. The code diagram for the note length data (7 to 4 bits) is shown in Figure 5, and the code for the scale data (3 to θ bits) is shown in Figure 6. Note length and scale data are respectively 4-bit binary as shown. - Constructed by sequentially corresponding to codes. In addition, the scale data is '0000
'(code OH) represents rest data, and at this time, 7
The ~4-bit note length data indicates so-called rest length data. Also, the C ~ / scale, including the chromatic part, is '0'.
100' (Code 41) to 1st Stitch 11' (Code FH) are made to correspond sequentially, and this allows the above-mentioned transposition by addition and subtraction of the scale decoder 17.

Modulation can be performed easily. The 9- to 8-bit octave data is combined with the above-mentioned scale data, and the F bit for O control is the one at the start of the song, making it possible to represent a scale of up to 4 octaves.
If 111 is set in a bit, it means that bits 8 to θ are data for tempo, and bits 7 to 4 are data for rhythm.

The E bit is the end code of the song, and if it is set to 1, the operation ends and the playback of the song stops when it is read.

The D bit and c bit are redundant pits. The B pit is used for performance symbols such as Fine (Fine), :ll (, repeat), D, S, (Darseni g), B bit, A, 9.8 pit) (B bit must be 11') Corresponding code shown in Figure 7 is used.

The control unit 24 in FIG. 8 distinguishes between such sound data and control data, and uses various control data to input the contents of the address counter 16 into a group of registers 28 or to input the contents of a group of registers 28 into the address counter 16. or set it. The address counter 16 is presettable and can be set using the register 28 as described above, and the register group 28 has a plurality of registers depending on the purpose.

Example of map of Melody ROM2> FIG. 8 shows a specific map example of the melody ROM 2.

To simplify the explanation, we assume that the address starts from OOH.0 The content of the address OQH is that %1jf is set in the F bit, and the 3rd to θ bits 10th and 1' are the tempo of the song.

Bits 7 to 4 '+000' indicate each data of the rhythm of the song.The contents of the address OIH indicate the note length and scale data, and are G, C (1 octave, with envelope).

The contents of the next address 02H are the same, indicating C (2 octaves, with envelope), but the contents of address 08H are B.
Since %l' stands in the pit, the B pittle 8 bits '+000' indicates the preference (segno) symbol of the performance order. When this is read, the contents of the address counter 16◎ are stored in one of the register groups 28, and the control unit 24
A pulse is generated to advance the address counter 16 and designate the next address. Address 041 is normal sound data, - (2 octaves, with envelope).

When reading address E8H, B pittle 8 bit '1
111' represents the S (dulsegno) symbol, and sets the address stored in the register 28 at address 08H in the address counter 16. Then, the control section 24 generates a pulse to advance the address, and the 0 address E4H, where the performance is repeated from address 04H, is the next address after the repetition, and the sound data J, MI (
0 address FE indicating 2 octaves, with envelope
Since H has 111 set in the E bit and is the end code, the song ends here.

Control of Performance Order> FIG. 9 is a block diagram of the control section 24 and its surroundings. I will now explain in a little more detail the control of the performance order using Fig. 9. The main operations are: 1. Controlling the rising and falling parts of the input clock (output from the matching circuit 25 in Fig. 8). Generate two pulses synchronously.

2. The gate circuit selectively sends out one or two of the above pulses to the next stage address counter. The operations of the register groups are controlled according to the format of each performance order.

It is.

When the input clock is input to the pulse generation circuit 81, two pulses are always generated, and when the B bit is not set to 11' (indicating data that is not a performance format), the gate circuit 32 generates one The contents of the address counter 16 are advanced by one. In response to this, the address of the melody 4ROM 2 advances by one.

By the way, as shown in FIG. 8, when the address counter 16 is 02H, the contents of the melody ROM 2 represent data as a C of p, and when the time of 1/8 note (n) has passed, a clock is generated. The signal is input to the pulse generation circuit 31. At this time as well, two pulses are generated as described above, and the address counter 16 is advanced by one by the pulse (1) synchronized with the rising edge. However, the content of the melody ROM 2 at address 08H has 11# set in the B bit and is data indicating the playing order (8 bits of B pitle, corresponding to the pregnancy symbol), so this is actively coded by the decoder 8B. The contents of the address counter 16 are written into one of the registers 28 specified by the decoded contents. Register designation is performed by a gate circuit 84 connected between the decoder 33 and the register group 28.

At the same time, since the B bit is 1■'', the gate circuit 32 at the next stage of the pulse generation circuit 81 also outputs a second pulse (2) synchronized with the falling edge, and the address counter 16 is further increased by 1. Then, the address immediately becomes 04H, and the content of the melody ROM 2 at that time is read out.The pulse generation circuit 81 generates two pulses for this kind of control. ) The performance order can be controlled without any hindrance to sound generation even if the first order data is stored at a predetermined address position. Such an operation causes the address counter 16 to advance.
As shown in FIG. 8, when the address counter 16 advances to address E8H, the contents of the melody ROM 2 are changed to B.
This is data with Al' in the bit indicating the performance order, and B
The S (Dulsegno) symbol is represented by 8 bits of pittle. This signal is decoded by the decoder 88 and outputs an output signal.0 This signal causes the address counter 16 to read the contents of the register previously designated by the g (seni-1) symbol.
In other words, the address 08H which stores data corresponding to the g (seni-1) symbol is set to zero. B when reading at address 08)1
Since V″l# is set in the bit, the second clock pulse (2) is synchronized with the falling edge of the input clock; it is input to the address counter 16 and the address corresponding to the 8 (Segno) symbol is input. Advance by one. Immediately after specifying the address of this tabe 0.5. (darseni g) symbol, address 04H
Return to , and read the contents of melody ROM2 starting from address 04H again.

However, when the address E8H of the symbol S (Darseni i) is specified for the second time, the gate circuit 34 operates to prohibit setting to the address counter 16,
Since 11' is set in the B bit in the data in the melody ROM 2 at address EIIIH, the next address E4H is designated and the process proceeds.

The above example almost corresponds to the one in Figure 1(d).
There is a Fine symbol in FIGS. 1(e) and 1(d), and when this Fine symbol is read out for the first time, the decoder 38. Due to the action of the gate circuit 84,
This address is written to the designated register in the register group 28. When reading D, S, (Dulsegno) symbols, C, (Dacabo) symbols, etc., the address of the Fine symbol is output to the matching circuit 85. That is, during repeated reading of the melody ROM 2, a match is found in the match circuit 35 with the contents of the address counter 16, and when the addresses match, a match output is output as an end code and the song is stopped.

Also, when the song is repeated from the beginning, as in Figure 1 (a), (b), (c), etc., the 11': (repeat) symbol is omitted in the score, but the melody ROM of this device
2, of course, data corresponding to the 11: (repeat) symbol is stored.

In the case of Figure 1(b) etc., the first II: (IJ Pete)
The address of the symbol (not shown in the score), the address of the "- symbol: When the address of the urN- symbol is first read,
When reading the :l+'' symbol, the address of the first 11= (repeat) symbol is set in the address counter 16, and the address of the r- symbol is set in the matching circuit. 35
Output to. In this way, the address counter 16 advances again from the address of the first II: (') beat) symbol.
``When it matches the address of the symbol, the matching circuit 85 outputs an output.'' However, the output of the matching circuit 35 at this time acts to set the address of the previous symbol in the address counter 16 by the decoder output, etc. , 100-
Jump a part and set the address.

Repeatedly: When jumping to the address of ll'le, the gate circuit 84 prohibits the passage of the decoded output, and
The fact that degrees are not repeated is the same as described above and in the case of the S (Dulceini=1) symbol.

The above configuration can also be easily realized using a micro combinator. As described above, according to the present invention, it is possible to store song data in a small capacity, and a useful melody performance device particularly suitable for semiconductor-based devices (LSI) can be provided.

[Brief explanation of drawings]

Figure 1 is a diagram explaining symbols for controlling the performance order;
FIG. 2 is a diagram showing the device configuration of an embodiment of the present invention, and FIG. 3 is a detailed view of the song playback control section of FIG. 2. Figure 6 is a diagram showing a code example corresponding to 6th M,
Fig. 7 is a diagram showing an example of the code corresponding to the symbols controlling each performance order, Fig. 8 is a diagram showing an example of the map of the ROM section, and Fig. 9 is a diagram showing an example of the map of the ROM section.
This figure is a view of the boot 2 showing the vicinity of the control section in FIG. 8 in more detail. G... Semiconductor element for song playback control, 2... Melody R
OM, 8...Keyboard, 4...Amplifier, 5...
Speaker, 15...Tone generator, 16...
...address counter, 17...scale decoder,
18... Note length decoder, 22... Note length frequency dividing circuit, 24... Control unit, 25... Matching circuit, 28...
...Group of registers, ``a't...Pulse generation circuit, 32...Gate circuit, 88...Decoder, 84...
...gate circuit, 35...matching circuit 0, agent patent attorney Fukushi Ai Hikobo 6 diagrams ￥5 diagrams

Claims (1)

[Claims] l. Means for sequentially storing sound data including scale data and note length data or rest length data, and storing data located at a predetermined position between the sound data and controlling the performance order, and reading the sound data. 1. A melody performance device, comprising: means for generating a melody according to the control data; and means for controlling the reading position of the sound data according to the reading of the control data, and controlling the performance order.