JPS5818248Y2 - variable resistance attenuator - Google Patents
variable resistance attenuatorInfo
- Publication number
- JPS5818248Y2 JPS5818248Y2 JP1977094936U JP9493677U JPS5818248Y2 JP S5818248 Y2 JPS5818248 Y2 JP S5818248Y2 JP 1977094936 U JP1977094936 U JP 1977094936U JP 9493677 U JP9493677 U JP 9493677U JP S5818248 Y2 JPS5818248 Y2 JP S5818248Y2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- variable resistance
- pattern
- substrate
- conductive electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Attenuators (AREA)
Description
【考案の詳細な説明】
本考案は可変抵抗減衰器に関い特に高周波数帯域で使用
されるプリント板実装型の可変抵抗減衰器に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable resistance attenuator, and particularly to a printed board mounted variable resistance attenuator used in a high frequency band.
従来、この種のプリント板実装型の可変抵抗減衰器は、
高周波数帯域に用いる場合、抵抗体及びプリント板への
接続を目的とした導電性電極パターン及びリード端子が
もつインダクタンス成分が可変抵抗減衰器の重要な特性
である周波数特性に多大な悪影響を与え、特に不整合減
衰量特性を劣化させるという欠点があった。Conventionally, this type of printed board mounted variable resistance attenuator was
When used in high frequency bands, the inductance components of conductive electrode patterns and lead terminals intended for connection to resistors and printed circuit boards have a significant negative impact on frequency characteristics, which are important characteristics of variable resistance attenuators. In particular, it has the disadvantage of deteriorating the mismatch attenuation characteristics.
本考案の目的は、かかるインダクタンス成分が与える悪
影響を除去した可変抵抗減衰器を提供することにある。An object of the present invention is to provide a variable resistance attenuator that eliminates the adverse effects of such an inductance component.
本考案による抵抗装置は少くとも抵抗体パターンが表面
に設けられた絶縁基板の裏面に少くとも抵抗体パターン
によるインダクタンスに伴なう電気的影響を小さくする
ように、基板の裏面に導電層を設けたことを特徴とする
。The resistor device according to the present invention is provided with a conductive layer on the back side of an insulating substrate having at least a resistor pattern on its surface so as to reduce the electrical influence caused by inductance due to the resistor pattern. It is characterized by:
あるいは本考案による可変抵抗減衰器は、絶縁基板表面
に被着した抵抗体パターン及び抵抗体パターン端部に接
続した導電性電極パターンに相対して絶縁基板の裏面に
導電性電極パターンを設け、かつ基板表面の電極パター
ンと基板裏面の電極パターンとを電気的接続したことを
特徴とする。Alternatively, the variable resistance attenuator according to the present invention includes a conductive electrode pattern provided on the back surface of the insulating substrate opposite to the resistor pattern adhered to the surface of the insulating substrate and the conductive electrode pattern connected to the end of the resistor pattern, and It is characterized in that the electrode pattern on the front surface of the substrate and the electrode pattern on the back surface of the substrate are electrically connected.
次に本考案を可変抵抗減衰器に用いた実施例を第１図乃
至第６図を参照して詳細に説明する。Next, an embodiment in which the present invention is applied to a variable resistance attenuator will be described in detail with reference to FIGS. 1 to 6.
第１図の回路図の如き、Ｔ型回路網を用いた可変抵抗減
衰器の実際の回路には、第２図に示したように可変抵抗
部の抵抗体Ｒ，、Ｐ、２． Ｒ３の長さを可変すること
により変化するインダクタンス成分Ｉ’ｌ ｔ Ｌ２
＋ Ｉ’３と固定抵抗部の抵抗体Ｒ４のインダクタンス
成分りい更に抵抗値を外部へ取り出すための導電性電極
部のインダクタンス成分Ｌｒ３゜Ｌｒ２．Ｌｒ３、およ
びリード端子部のインダクタンス成分Ｌｌ、 、 ＬＡ
？２ 、 ＩＪ３が存在している。The actual circuit of a variable resistance attenuator using a T-type network as shown in the circuit diagram of FIG. 1 includes resistors R, P, 2, . Inductance component I'l t L2 that changes by varying the length of R3
+ I'3, the inductance component of the resistor R4 of the fixed resistance section, and the inductance component Lr3°Lr2. of the conductive electrode section for extracting the resistance value to the outside. Lr3 and the inductance component of the lead terminal section Ll, , LA
? 2, IJ3 is present.
本考案では、第３図ａに示す如く、絶縁基板１の表面に
窒化クンタル薄膜の抵抗体パターン２１゜２２．２３．
２４を被着し、この抵抗体パターン端部に接続してＮｉ
−０ｒとＡｕの蒸着により、表面電極パターン３１〜３
７を設ける。In the present invention, as shown in FIG. 3a, resistor patterns 21, 22, 23.
24 and connect it to the end of this resistor pattern.
-0r and Au vapor deposition, the surface electrode patterns 31 to 3
7 will be provided.
ここで表面電極パターン３１，３２．３７と３４．３５
゜３６との間で摺動子６を摺動させることにより表面電
極パターン３１と摺動子６に圧接された抵抗体パターン
２１との接点部５１間の抵抗値が第１図に於ける可変抵
抗部Ｒ１に、表面電極パターン３２と摺動子６に圧接さ
れた抵抗体パターン２２との接点部５２間の抵抗値が第
１図に於ける可変抵抗部Ｒ２に、表面電極パターン３６
と摺動子６に圧接された抵抗体２３の接点部５３間の抵
抗値が第１図に於けるＲ３に、抵抗体パターン２４が第
１図のＲ４になるように構成する。Here, surface electrode patterns 31, 32, 37 and 34, 35
By sliding the slider 6 between the slider 6 and the slider 6, the resistance value between the contact portion 51 between the surface electrode pattern 31 and the resistor pattern 21 pressed against the slider 6 can be changed as shown in FIG. The resistance value between the contact portion 52 between the surface electrode pattern 32 and the resistor pattern 22 pressed against the slider 6 in the resistance portion R1 is the same as that in the variable resistance portion R2 in FIG.
The resistance value between the contact portion 53 of the resistor 23 pressed against the slider 6 is R3 in FIG. 1, and the resistance value of the resistor pattern 24 is R4 in FIG.
次に第３図すの如く、この絶縁基板１の裏面に、第３図
ａに示した摺動される抵抗部抵抗体２１および表面電極
３１に対応して重なる如く裏面電極パターン４−２を、
抵抗体２２および表面電極３２とに対応して基板裏面に
裏面電極４−１を、抵抗体２３．２４および表面電極３
３に対応して裏面電極４−３とそれぞれが対応する表面
電極３１．３２．３３とに基板端部に導体を設けるか、
あるいはスルーホール等によって電気的に接続するよう
にして設ける。Next, as shown in FIG. 3, a back electrode pattern 4-2 is formed on the back surface of this insulating substrate 1 so as to correspond to and overlap with the sliding resistor part resistor 21 and front electrode 31 shown in FIG. 3a. ,
A back electrode 4-1 is provided on the back surface of the substrate corresponding to the resistor 22 and the front electrode 32, and a back electrode 4-1 is provided on the back surface of the substrate corresponding to the resistor 22 and the front electrode 32.
3, a conductor is provided at the end of the substrate for the back electrode 4-3 and the corresponding front electrodes 31, 32, 33, or
Alternatively, it is provided so as to be electrically connected by a through hole or the like.
かかる裏面電極パターン４−１〜４−３は基板１を誘電
体として基板表面の抵抗体および電極とで第５図の回路
図に示す如くそれぞれキャパシタンス部の０２．Ｃ１，
Ｃ３ヲ形成する。These back electrode patterns 4-1 to 4-3 use the substrate 1 as a dielectric, and the resistors and electrodes on the surface of the substrate form capacitance portions 02. C1,
Form C3.
ここで裏面電極パターン４と表面電極パターン３１〜３
３を接続した方が、接続しない場合に比ベキャパシタン
ス部Ｃ１Ｃ２，Ｃ３の値は大きくすることができる。Here, the back electrode pattern 4 and the front electrode patterns 31 to 3
3 is connected, the values of the comparative capacitance parts C1C2 and C3 can be made larger than when they are not connected.
本考案による回路図は第５図の示す如き構成となる。The circuit diagram according to the present invention has a configuration as shown in FIG.
高周波数帯域で使用した場合、周波数が高くなるに従っ
て前記インダクタンス酸分Ｌｌ 〜Ｌ４ 、 Ｌｒｌ
〜Ｌｒ３ 、 Ｌ７１〜Ｌ１３は、可変抵抗減衰器のイ
ンピーダンス増加を招き、可変抵抗減衰器の周波数特性
、特に不整合減衰量が劣化する。When used in a high frequency band, the inductance acid content Ll to L4, Lrl increases as the frequency increases.
~Lr3, L71 to L13 cause an increase in the impedance of the variable resistance attenuator, and the frequency characteristics of the variable resistance attenuator, especially the amount of mismatch attenuation, deteriorate.
しかし本考案により前記キャパシタンス部Ｃ１，Ｃ２，
Ｃ３を設けることによって、このインピーダンス増加を
補正することができる。However, according to the present invention, the capacitance parts C1, C2,
By providing C3, this impedance increase can be corrected.
第４図はかかる基板１をリード端子７を配した外装ケー
ス８に実装した切断斜視図である。FIG. 4 is a cutaway perspective view of the board 1 mounted in an exterior case 8 in which lead terminals 7 are arranged.
本考案を使用した可変抵抗減衰器の測定を行なったとこ
ろ第６図の示す如く補正を行なわない従来品に比べ、特
性が大巾に改善できることが確認された。When a variable resistance attenuator using the present invention was measured, as shown in FIG. 6, it was confirmed that the characteristics could be greatly improved compared to the conventional product without correction.
以上、本考案による可変抵抗減衰器の周波数特性は、高
周波数帯域に於いても優れた特性を充分示しうる効果が
太きい。As described above, the frequency characteristics of the variable resistance attenuator according to the present invention are sufficiently effective in showing excellent characteristics even in a high frequency band.
第１図はＴ型可変抵抗減衰器の回路図、第２図は実際的
なＴ型可変抵抗減衰器の回路図、第３図ａ、ｂは、それ
ぞれ本考案実施例の基板表面の平面図及び基板裏面の平
面図、第４図は第３図の実際使用例の分割図、第５図は
第３図の回路図、第６図は第３図の不整合減衰量を示す
周波数特性図である。
図中の符号、１・・・・・・絶縁基板、２１〜２４・・
・・・・抵抗体パターン、３１〜３７・・・・・・表面
電極パターン、４−１〜３・・・・・・裏面電極パター
ン、５１〜５３・・・・・・接点部、６・・・・・・摺
動子、７・・・・・・リード端子、８・・・・・・外装
ケース、Ｒ１−Ｒ３・・・・・・可変抵抗部の抵抗体、
Ｒ４・・・・・・固定抵抗部の抵抗体、Ｌ、−Ｌ４・・
・抵抗体のインダクタンス、Ｌｒ１〜Ｌｒ３・・・・・
・表面電極のインダクタンス、Ｌｒ１〜Ｌｒ３・・・・
・・リード端子のインダクタンス、Ｃ１〜Ｃ３・・・・
・・本考案により構成したキャパシタンス。Figure 1 is a circuit diagram of a T-type variable resistance attenuator, Figure 2 is a circuit diagram of a practical T-type variable resistance attenuator, and Figures 3a and 3b are plan views of the substrate surface of the embodiment of the present invention. and a plan view of the back side of the board, Fig. 4 is a split diagram of the actual usage example of Fig. 3, Fig. 5 is a circuit diagram of Fig. 3, and Fig. 6 is a frequency characteristic diagram showing the mismatch attenuation amount of Fig. 3. It is. Codes in the figure: 1...Insulating substrate, 21-24...
...Resistor pattern, 31-37...Surface electrode pattern, 4-1-3...Back electrode pattern, 51-53...Contact part, 6. ...Slider, 7 ... Lead terminal, 8 ... Exterior case, R1-R3 ... Resistor of variable resistance section,
R4...Resistor of fixed resistance section, L, -L4...
・Resistor inductance, Lr1 to Lr3...
・Inductance of surface electrode, Lr1 to Lr3...
・・Lead terminal inductance, C1 to C3・・・・
...Capacitance configured according to the present invention.
Claims (1)
に接続された導電性電極パターンを絶縁基板表面に有し
、前記抵抗体パターンを電気的に接続する摺動子を備え
た可変抵抗減衰器において、前記基板の裏面に前記抵抗
体パターンおよび導電性電極パターンにほぼ相対応する
形状の複数の導電性電極パターンを設け、かつ前記基板
表面側の導電性電極パターンと前記基板裏面側の導電性
電極パターンとを電気的に接続したことを特徴とする可
変減衰器。A variable resistance attenuator having a plurality of resistor patterns and a conductive electrode pattern connected to the ends of the resistor patterns on the surface of an insulating substrate, and a slider electrically connecting the resistor patterns. , a plurality of conductive electrode patterns having shapes substantially corresponding to the resistor pattern and the conductive electrode pattern are provided on the back side of the substrate, and a conductive electrode pattern on the front side of the substrate and a conductive electrode on the back side of the substrate. A variable attenuator characterized in that it is electrically connected to a pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1977094936U JPS5818248Y2 (en) | 1977-07-15 | 1977-07-15 | variable resistance attenuator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1977094936U JPS5818248Y2 (en) | 1977-07-15 | 1977-07-15 | variable resistance attenuator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5421147U JPS5421147U (en) | 1979-02-10 |
| JPS5818248Y2 true JPS5818248Y2 (en) | 1983-04-13 |
Family
ID=29027406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1977094936U Expired JPS5818248Y2 (en) | 1977-07-15 | 1977-07-15 | variable resistance attenuator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5818248Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10888747B2 (en) | 2008-07-15 | 2021-01-12 | Taylor Made Golf Company, Inc. | Aerodynamic golf club head |
| US8858359B2 (en) | 2008-07-15 | 2014-10-14 | Taylor Made Golf Company, Inc. | High volume aerodynamic golf club head |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51245A (en) * | 1974-06-19 | 1976-01-05 | Matsushita Electric Ind Co Ltd | ATSUTENEETASOCHI |
-
1977
- 1977-07-15 JP JP1977094936U patent/JPS5818248Y2/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51245A (en) * | 1974-06-19 | 1976-01-05 | Matsushita Electric Ind Co Ltd | ATSUTENEETASOCHI |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5421147U (en) | 1979-02-10 |
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