JPS58182328A - Reception frequency controller of synthesizer receiver - Google Patents

Abstract

PURPOSE:To prevent such malfunction that the same frequency dividing ratio is preset to plural number of channels, by providing a function detecting whether or not the frequency dividing ratio of a programmable frequency divider is the same as the preset frequency dividing data. CONSTITUTION:A frequency dividing ratio data to be set from a frequency dividing ratio output section Do of a controller 21 to a programmable frequency divider 132 is applied to an input section Dc1 of a data comparator 28, and the data comparator 28 compares the frequency dividing ratio data of the input sections Dc1, Dc2. A decoder 27 decodes an address signal (BCD code) outputted from an address generator 26 and brings any of corresponding output terminals D1-D6 to L or H level. Thus, any of transistors (TRs) Q1-Q6 is set on, and any of corresponding light emitting diodes DL1-DL6 is driven for illumination. Thus, the user confirms easily whether or not the frequency dividing ratio of the frequency during the reception with the synthesizer receiver is preset to any of the channels 1-6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a reception frequency control device for a synthesizer receiver in which a local oscillator has a phase-locked loop.

[Background technology of the invention]

Recently, synthesized receivers in which a local oscillator for frequency mixing has a phase-locked loop have become widespread.

Such a synthesizer receiver includes, for example, a high frequency amplifier 11, a mixer 12, and a local oscillator J as shown in FIG.
J, intermediate frequency amplifier 14, detector 15, low frequency amplifier 1
6, a speaker 15, etc. As is well known, the local oscillator 13 includes a voltage controlled oscillator 131, a Derodaramar divider 132, and a reference frequency oscillator.
, $1Jt Softener J J 4 , A-/Math filter 135, which has a phase-locked loop (PLL loop) capable of deriving high-frequency signals at predetermined frequency intervals, and is programmable. The frequency divider 132 is a frequency division ratio output section of the controller 2, which constitutes a control device for the reception frequency of a synthesizer receiver, for example, using an IC. A predetermined frequency division ratio is set based on the output of the . The controller 21 has, for example, the functions listed below.

(1) Operate the manual mode switch 8m and set the manual mode terminal τm to high level (hereinafter referred to as H level).
If the low level is temporarily lower than C (referred to as L level), the mode becomes manual channel selection mode. In this manual tuning mode, a desired frequency can be received by operating a group of frequency setting switches (not shown). The block controller 21 calculates a frequency division ratio for the programmable divider taX based on received frequency data input from a frequency setting switch and a frequency setting switch (not shown), and outputs the calculated frequency division ratio from a frequency division ratio output section Do.

(2) Operate the automatic mode switch 5m to switch to automatic mode P.
When the terminal Ta is temporarily set to an H level η≧m level, an automatic channel selection mode is entered. In this automatic channel selection mode, the controller 21 operates the programmable frequency divider 13 in response to the operation of the up (*p) or down (d@wn) switch (not shown).
2, the reception frequency can be raised or lowered by outputting division ratios that are sequentially increased or decreased from the division ratio output section Do. Then, in the state of detecting (receiving) the broadcast signal, the controller 21 retains the current division ratio output section D0 output until the next increase (su) to (d@wn) switch operation. be.

(3) Operate the preset channel selection switch 8p and toss Brisera > t1m child Tp to 1111 level or bL level.
□If you do so, you will enter preset channel selection mode. This channel selection mode can be preset (for example) in the external memory 22 by the operation described later.
It is possible to read out any of the reception frequency division ratio data of any six channels stored in memory by operating the first to sixth channel switches S1 to S8 according to the desired channel. . In this case controller 2
1 supplies address signals designated by channel switches 81 to SaK and, for example, negative logic read signals to the address input section At and read control terminal R of the main circuit 22.

Note that the memory 22 mentioned above is, for example, a RAM (random access memory), and the address input section 1 is the address output section A of the controller 21. The frequency division ratio data input/output section M1 is connected to the data input/output section C of the controller 21.
Connected to 1.

(4) In the controller 21, the frequency data output section r0 is connected to the frequency display 23, so that the received frequency of the synthesizer side receiver can be displayed, and the channel number output section C0 is connected to the channel display 24. The channel number selected in the preset channel selection mode can be displayed.

(5) In the above-mentioned nine-channel mobile channel selection mode or automatic channel selection mode, operate any of the channel switches 81 to S @ and turn on the memory write switch 8W to level the memory write terminal VT-L. Then, the channel number is stored in the register for storing the designated channel inside the controller 21. At the same time, controller 11
#i, address output section. The address signal corresponding to the channel number is derived from the data input/output section C1.
Karame (21) data input/output sections M and K output frequency division ratio data corresponding to the frequency being received by itself. Then, when the write terminal G changes from the m level to the ■ level;
The controller 11 inputs frequency division ratio data to a predetermined storage area 220 designated by an address signal through a data input/output 11iiiM, for example, from a negative logic write control 5wt-m level of ME*qxz to an m level. It is possible to create presets that allow you to memorize. Each input terminal of controller 11 TDI #7a e'rp e
For example, Tv and TI to T are internally pulled up to H level. t each sui, te Sm t Ss
# Sp , p Sv and S! From Bm to Bm are non-mouthed, ri-style sui, and te.

That is, the controller 21 as described above. By adding this preset function to the Melogrammasol divider 1320 stations, it has become extremely easy to perform the tuning operation to receive the desired broadcast signal. In the 1m preset mode (manual or automatic channel selection mode), it is possible to check whether the division ratio of the programmer sol frequency divider 132 for the frequency being received at that time is the already preset frequency division ratio. It's impossible. For this reason,
It often happens that the division ratio for the same reception frequency is preset to a different channel by mistake. This drawback is more likely to occur as the number of receivable broadcasting stations increases, and the function of presetting the division ratio of the programmer sol frequency divider cannot be fully utilized.

[Purpose of the invention]

This invention has been made in view of the above points, and the division ratio of the programmer full frequency divider can be preset to a predetermined channel with respect to the received frequency. The purpose is to

[Summary of the invention]

This invention includes a voltage controlled oscillator, a programmer-norm divider,
In a synthesizer receiver equipped with a reference frequency oscillator, a phase comparator, and a local oscillator in which a phase-locked loop is formed by a rononus filter, the desired frequency can be received by manually or automatically setting the division ratio of the programmable divider. It is possible to preset (memorize) division ratio data of the programmer's division divider corresponding to any frequency desired for reception, and to read out the stored frequency division ratio data with a one-touch operation. A means for setting a predetermined division ratio in a programmer sol frequency divider and making it possible to receive a frequency corresponding to the set division ratio data, and a control device for a programmable frequency divider set manually or automatically. It is characterized by

[Embodiments of the invention]

An embodiment of the present invention will be described in detail below with reference to the drawings.

The same parts as in Figure 1 are given the same reference numerals and their explanation will be omitted.

That is, the controller 21 is, for example, an address output section. is one input part o of the well-known data selector 25.
, 1Km is connected, and it is now possible to output 0 to 50 BCD (B evolution and illegal) codes corresponding to 6 preset channels.
The output section of the data selector 21 is connected to the other input section DIlK of the data selector 25. This address generator 26 has an output part connected to the rcog 2f0 input part, which will be described later, together with the other input part D0 of the data selector, and a drive signal is supplied to the negative logic drive input terminal. Then,
The output section outputs one ICD code of 0 to S and automatically stops operation. The output section of the data selector 250 is connected to the input section of the memory 220. This memory 220 frequency division ratio data output part M
, are connected to the rotor input/output portion c1 of the gondola 2 and one input portion Dc of the Kf”-f1 comparison flhxa.

Further, the frequency division ratio output section D0 of the controller 21 is connected to the other input section DC1 of the data comparator 11 together with the frequency division ratio input section of the programmer's output 14@xsx. The output terminal of this data comparator 21 is connected to the input terminal of a holding circuit 29, which will be described later. The output terminal of this holding circuit 29 is directly connected to one input terminal of an OR circuit 30, which is a control input group for controlling the holding of the BCD code output of the address generator 2C, and is connected via an inverter 31 to the It is connected to the output inhibit terminal of the decoder 27. The OR circuit 30 is configured such that the other input terminal is connected to an output terminal Km which outputs a write signal of the controller 2, and the output terminal is connected to a negative logic write control terminal W of the memory 22. It has become. The midpoint of the connection between the switch 5tlil and the terminal of the controller j1 is one input terminal of the AND circuit 32, the drive terminal of the address generator 2d, the control input terminal of the data selector 2j, and the falling edge of the signal of the holding circuit 29. The AND circuit 31 is connected in common to the reset terminals that are detected and driven.
The other input terminal is connected to the output terminal for outputting the read signal of the controller 11, and the output terminal is connected to the negative logic write control terminal KIN of the above-mentioned memory 22.

The data selector 25 outputs the signal of the input section D□ to the output section when the control input terminal is at the H level, and outputs the signal of the input section D□ to the output section when the control input terminal is at the L level. This is what is output. The holding circuit 29Fi detects the rise of the input terminal level and sets the output terminal level to the t-H level, and is reset when the reset terminal is at the H level.

It will be in a blank state. The data comparator 2S is
I and DC! When the signals match, the output changes from L level to ■Shizakiru. The above decoder 21 is the input it
Corresponding to the O to 50 II CD codes supplied to t, one of the output terminals DI to D is set to H level, and when the output inhibit terminal is set to H level, the output of the output terminals DI to D is set to H level. are prohibited and enter a high impedance state.

t&, channel number output section C of the controller 21
, a% For example, the output terminal C0, or 1iC, is configured like this,
A resistor R whose each output terminal constitutes the channel indicator 24
The transistors Qt
The output terminals DI to D- of the decoder 27 are connected to the paces Q6 to Q6 and the output terminals DI to D- of the decoder 27, respectively. These transistor Q! The emitters and RI of each of Q6 to Q6 are commonly grounded, and the collectors of each of them are connected to corresponding candos of light emitting diodes DLL to DL6 for displaying channel numbers.

Each anode of each of these diodes DL1 to DL4 is
Correspondingly, the resistances R, to R1! After that, they are commonly connected to the power supply VCC.

, 8p is operated to enter the channel selection mode. In this case, since the control input terminal of the data selector 25 is at the H level, when the switches S1 to S8 are operated, the controller 21 sends an address signal to the address input section of the memory 22 via the data selector 25. At the same time, the read control signal is outputted to the read control terminal RK ratio of the memory 22 via the AND circuit 32, and the frequency division ratio data stored in the memory 21 is read out, and the frequency division ratio of the programmer sol frequency divider 1320 is set to a predetermined value. Set. As a result, a desired frequency can be received by the synthesizer receiver.

On the other hand, when the write switch gv is turned on in a state where the division ratio of the programmer sol frequency divider for the received frequency can be reset to a predetermined channel (when the switch is in manual or automatic tuning mode). In this case, the controller 21 stores the specified channel in an internal register, and
The level of the terminal iw falls from the H level to the L level.

As a result, the address generator 2C is driven and the data selector 25 is
6 is supplied to the address input section iK of the memory 22. t memory 221fi, read control terminal is AND circuit 32
The level is changed from H level to L level through the input signal, and the read state is entered.

Accordingly, the memory 22 responds to the address signal output of the address generator 26 and sequentially transfers the preset frequency division ratio data to the data comparator 2 corresponding to each channel.
8 input section. Supply to 2.

On the other hand, the input section DC of the data comparator 28 has a division ratio output section of the controller 210. Frequency division ratio data to be set is supplied to the color 7' logarithmic multiplexer 132.

And the data comparator 28 has each input section DCI P DC
The m frequency division ratio data are compared, and when they match, the output terminal level is set to tL level i-raH level.

By the way, in the holding circuit 29, the reset terminal is preset to fall from the H level to the L level while the switch gv is turned on. Therefore, the holding circuit 29 holds each input portion Dc1 . DCj signals match,
When the output terminal of the data comparator 28 rises from L level to H level, the output terminal rises from L level to H level9,
This state is maintained until the next reset terminal falls. Along with the fin, the control input terminal of the generator 2# is driven to hold the address signal being outputted. Further, the write control terminal W of the output terminal 22 is set to the H level through the OR 1 path 10 at least during the period in which the holding circuit 29 maintains the H level at the output terminal. Then, the decoder 27 outputs an address signal (1ico
code) is decoded, and one of the corresponding output terminals Dl to D- is set from the L level to the level.

This is % from K) Any one of the rungs Ql to q6 is turned on, and the turned-on transistors Ql to Q-
The light emitting diodes 'D&1 to MDL corresponding to are driven and emit light. Therefore, the frequency being received by the receiver has a division ratio of 1! ! The user can determine whether or not it is transmitted to any of the I6 channels.

Then, when the switch fly is turned off, the controller 21 controls the memory 2 through the data selector 25t.
The address input section MLK of No. 2 outputs an address signal corresponding to the channel number stored in the internal register, and also outputs a write signal to the memory 220. At this time, the write signal of the memory 22 is shimmered by the holding circuit 29 and the OR circuit 3o, so the division ratio corresponding to the frequency being received is not preset to any channel. Just by performing Hi's Delise and Toshu,
Preset the same division ratio to multiple channels1
It is possible to prevent erroneous operations such as 9 from occurring.

Furthermore, if the frequency division ratio of the programmable frequency divider 112 corresponding to the frequency being received does not match the frequency division ratio data stored in the message 22, the output terminal of the holding circuit 29 is
Since the level is not the same, when the switch 8w is turned from on to off, the controller 21 is set to a predetermined address.
Channel &C) division ratio can be stored (tb preset). tb, the address signal of the controller 21 is supplied to the address input section 1 of the memory 12 via the data selector 21, and the glance signal from the controller 2 is not masked by the output signal of the holding circuit 29, The glance control terminal is supplied with N1 controller 2
The frequency division ratio data output from the input/output gc of 1 is stored in the memory 22.

In this way, when the frequency division ratio of the programmable frequency divider can be preset, the frequency division ratio of the programmable frequency divider that is desired to be preset is already provided in the pre-device. This allows you to take full advantage of the ratio preset function.

In the above embodiment, the write switch 8v is set to the degrammer fl.
&f A drive switch with a function to compare the division ratio of the frequency divider and the division ratio data stored in the memory! The frequency divider's division ratio is also used as a frequency divider, but it can also be applied to a separate synthesizer receiver, and it can also be applied to a frequency synthesizer type transceiver. It is.

It goes without saying that various other modifications and applications are possible without departing from the gist of the invention.

〔Effect of the invention〕

As detailed above, according to the present invention, the frequency division ratio of the programmable frequency divider for the reception frequency can be pre-provided in a state where it can be delivered to a predetermined channel. be able to.

[Brief explanation of the drawing]

Figure 1 shows the configuration of a conventional synthesizer receiver with 21...
Controller, 22...Memory, xs...Frequency display, 24...Channel display, 25...Data selector, 26...Address generator, 29...
・Holding circuit, 30... OR circuit, 31... Inverter, 32... AND circuit, Sm # Sa t8p,
8v, 8s to S-... switch, R1 to it,...
...Resistance, Ql to Q6...Transistor, DL□ to DL,...Light emitting diode, 132...Programmer sol divider. Applicant's Representative Patent Attorney Takeshi Suzue Figure 1 Figure 2

Claims (1)

[Claims] In a synthesized receiver equipped with a local oscillator in which a phase-locked loop is formed by a voltage-controlled oscillator, a programmable frequency divider, a reference frequency oscillator, a phase comparator, and a low frequency filter, A first means for making it possible to receive a desired frequency by setting the frequency division ratio by yourself or manually; and presetting (memory) the frequency division ratio data of the programmable frequency divider corresponding to the desired frequency for reception. ) is possible, reads out the stored frequency division ratio data with a one-touch operation, sets a predetermined frequency division ratio in the programmer sol frequency divider, and makes it possible to receive the frequency corresponding to the preset frequency division ratio data. and a third means for detecting whether or not the division ratio set in the programmable frequency divider by the first means and the trap division ratio data (stored by the second means) correspond. 1. A reception frequency control device for a synthesizer side receiver, comprising: means.