JPS58182241A - Cutting method for single crystal wafer - Google Patents
Cutting method for single crystal waferInfo
- Publication number
- JPS58182241A JPS58182241A JP57065633A JP6563382A JPS58182241A JP S58182241 A JPS58182241 A JP S58182241A JP 57065633 A JP57065633 A JP 57065633A JP 6563382 A JP6563382 A JP 6563382A JP S58182241 A JPS58182241 A JP S58182241A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- blade
- wafer
- cutting
- edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Abstract
Description
【発明の詳細な説明】
本発明は準結晶ウェハのダイシングによる切断方法に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for cutting a quasicrystalline wafer by dicing.
表面弾性波素子に使用される材料として、タンタル酸リ
チウム（ＬｉＴａＯ３）、ニオブ酸リチウム（ＬｉＮｂ
Ｏ５）などの単結晶基板が多くつかわれている。これら
の基板は、非常に、脆い性質を有しているので、その敗
り扱いには慎重な景する。熱的な応力だけでなく、機械
的に欠損しやすいためＫ、ウェハ状の基板からチップと
して分割する場合Ｋ。Lithium tantalate (LiTaO3), lithium niobate (LiNb) are used as materials for surface acoustic wave devices.
Single crystal substrates such as O5) are often used. These substrates are extremely fragile, so care must be taken when handling them. K because it is easily damaged not only by thermal stress but also mechanically, and K when dividing a wafer-shaped substrate into chips.
ダイヤモンドなどの砥粒により形成された薄し・刃を高
遠屓で回転させて切断する、ダイシングと呼ばれる切断
方法においても、刃の性質、送り速度などを適切に選定
しても、チッピングと呼＆ｆれる欠けを生じ易い。これ
らの欠けは、チップの破断の原因になり、素子製造上大
きな問題となる。Even in a cutting method called dicing, in which cutting is performed by rotating a thinning blade formed of abrasive grains such as diamond at a high distance, the process is called chipping, even if the properties of the blade, feed rate, etc. are appropriately selected. It is easy to cause chipping. These chips cause chip breakage, which poses a major problem in device manufacturing.
第１！！！１（＋１）は従来の方法で切断されたチップ
の斜視−で、第１図（−は、この欠けの模様を示す、第
１図（ａ）Ｋ示すチップｌの稜部分の拡大断面図で、山
と谷の間の＾低差は栃μｌｉ４ある。1st! ! ! 1 (+1) is a perspective view of a chip cut by the conventional method, and FIG. , the difference in height between the peak and the valley is Tochiμli4.
本発明の目的は、したがって、チップの破断の原因とな
るような欠けを生じない。単結晶ウェノ・のダイシング
による切断方法を提供することである。The object of the invention is therefore to avoid chipping that would cause chip breakage. An object of the present invention is to provide a method for cutting single crystal wafer by dicing.
上記目的を達成するために、本発明による冒頭に述べた
種類の切断方法は、先端に傾斜を有する刃を用いて切断
しようとする準結晶ウェノ・表ｍＫ浅い溝を形成する１
１１１の工程と、上記第１の工程で使用した刃よりも薄
い刃を用いて上記浅い溝の底ｔｈｌ領域におい℃上記単
結晶ウニノ・を完全ＫｖＪ断する第２の工程とからなる
ことを安上とする。In order to achieve the above object, the cutting method of the type mentioned at the beginning according to the present invention uses a blade with a beveled tip to form a shallow groove in the quasicrystalline material to be cut.
111, and a second step of completely cutting off the KvJ of the single crystal Unino® at the bottom thl region of the shallow groove using a blade thinner than the blade used in the first step. Above.
以下に一面を参照しながら、実施的な用いて本発明を一
層絆しく説明するけれども、それらは例示に過ぎず、本
発明の枠を越えることなしＫいろいろな変形や改良があ
り得ることは勿論である。The present invention will be explained below in a more detailed manner through practical use, but these are merely examples and do not go beyond the scope of the present invention.Of course, various modifications and improvements may be made. It is.
先端が１２０°の角度を持った刃を用いて、まず、第２
１Ｍ（ａ）に示すように１ウエハ２の表面から加〜切μ
准の深さの逆梯形の溝をつける。溝の縁３と３′の間の
間隔は約２００μｒａで、溝のｌｌｌ１４．４’はウェ
ハ２の表面とは約ガの角度をなす。このとき、溝つけは
極めて低いウェハ送り速度で行なう。つぎに、繭に使用
した刃よりも小さな厚さの刃を用いて、總２図Ｔｂ）
Ｋ示すように、上記逆梯形の溝の底面領域においてウェ
ハ２を完全に切断して、複数のチップＩＫ分割する。Using a blade with a 120° tip, first cut the second blade.
As shown in 1M(a), cutting μ from the surface of 1 wafer 2
Grooves in an inverted trapezoidal shape with an associate depth. The spacing between the edges 3 and 3' of the grooves is about 200 .mu.ra, and the grooves 14.4' form an angle of about 14.4 with the surface of the wafer 2. At this time, grooving is performed at an extremely low wafer feeding speed. Next, using a blade with a smaller thickness than the blade used for the cocoon, (Figure 2 Tb)
As shown in K, the wafer 2 is completely cut in the bottom region of the inverted trapezoidal groove to divide it into a plurality of chips IK.
以上の順序にしたがって切断すれば、＃！１の工程の切
断では切込みが深く、かつ溝の側面４，４′は傾斜して
いるから、稜部分の欠けは極めて小さく、山と谷の間の
＾低差は通常２乃至３μｊｌＩＩＫ遇ぎない。第２の工
程で生じる稜の欠け＆ま溝の側面の所で阻止されるから
、クランク＆ま溝の底面領域の縁５，５′から外圧向っ
て進行することし家な（・。If you cut according to the above order, #! In the cutting step 1, the cut is deep and the side surfaces 4, 4' of the groove are inclined, so the chipping at the edge is extremely small, and the height difference between the peak and valley is usually only 2 to 3 μjlIIK. Since it is stopped at the side surface of the groove and groove in the ridge that occurs in the second step, it is impossible for the external pressure to proceed from the edges 5, 5' of the bottom area of the crank and groove.
第３図は本発明の方法によって切断されたチップｌの角
部分の斜視図である。FIG. 3 is a perspective view of a corner portion of a chip I cut by the method of the present invention.
以上説明した通り、本発明によれば、ダイシングによる
欠けが少ないから、チップの歩留り力１向上し、それか
ら製造される素子の信頼性力１よくなるという利点が得
られる。As explained above, according to the present invention, since there are fewer chips due to dicing, the yield of chips is improved by 1, and the reliability of devices manufactured from the chip is improved by 1.
第１図（ａ）は従来の方法で９１ｉ＃ｒされたチップの
斜視図、菖ｘｌＶ（ｂｌはｇ１図（ａ）にボすチップの
稜部分の拡大断面図、第２Ｎ（ａ）は不発＃！ＡＫよる
方法の第１の工程後のウニノ１の断面図、第２図（ｂ）
は本発明による方法の第２の工程後の分割されたチップ
のｌＩｒ面図、第３図は第２図（四のチップの角部分の
斜視図であるー。
１・・・チップ、２・・・ウニノー、３，３′・・・溝
の縁、４゜４１・・・溝の側面、５．５′・・・溝の底
面領域の縁。Fig. 1(a) is a perspective view of a chip processed by the conventional method to 91i#r, iris xlV (bl is an enlarged sectional view of the edge of the chip shown in g1(a), and No. 2N(a) is an unexploded #! Cross-sectional view of UNINO 1 after the first step of the AK method, FIG. 2(b)
3 is a perspective view of the corner portion of the chip shown in FIG. 2 (4). 1...chip, 2... ...Unino, 3,3'...Edge of the groove, 4゜41...Surface side of the groove, 5.5'...Edge of the bottom area of the groove.
Claims (1)
結晶ウェハ表面に浅い溝を形成する第１の工程と、上記
第１の工程で使用した刃よりも薄い刃を用いて上記浅い
溝の底面領域において上記準結晶ウェハな完全に切断す
る第２の工程とからなることを特徴とする、単結晶ウェ
ハのダイシングによる切断方法。A first step of forming a shallow groove on the surface of the quasicrystalline wafer to be cut using a blade with a tip inclined at 14iK, and forming a shallow groove on the bottom surface of the shallow groove using a blade thinner than the blade used in the first step. and a second step of completely slicing the quasi-crystalline wafer in the region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57065633A JPS58182241A (en) | 1982-04-19 | 1982-04-19 | Cutting method for single crystal wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57065633A JPS58182241A (en) | 1982-04-19 | 1982-04-19 | Cutting method for single crystal wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58182241A true JPS58182241A (en) | 1983-10-25 |
Family
ID=13292615
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57065633A Pending JPS58182241A (en) | 1982-04-19 | 1982-04-19 | Cutting method for single crystal wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58182241A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63246208A (en) * | 1987-04-01 | 1988-10-13 | 住友電気工業株式会社 | Dicing method of semiconductor wafer |
| JPH02305207A (en) * | 1989-05-19 | 1990-12-18 | Sanyo Electric Co Ltd | Manufacture of surface acoustic wave element |
| FR2870637A1 (en) * | 2004-05-18 | 2005-11-25 | Temex Sa Sa | Crystalline structure component e.g. surface acoustic wave component, for e.g. strain gauge, has two plane sides whose circumference have plane bevels, where angles between planes of bevels and sides lie between forty five and sixty degrees |
| US6996882B2 (en) | 1999-06-14 | 2006-02-14 | Matsushita Electric Industrial Co., Ltd. | Method for producing a surface acoustic wave element |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4946681A (en) * | 1972-09-07 | 1974-05-04 | ||
| JPS5410682A (en) * | 1977-06-25 | 1979-01-26 | Nec Corp | Production of semiconductor elements |
| JPS5412563A (en) * | 1977-06-29 | 1979-01-30 | Toshiba Corp | Fabricating method of semiconductor crystals |
| JPS5549599B2 (en) * | 1975-11-27 | 1980-12-12 |
-
1982
- 1982-04-19 JP JP57065633A patent/JPS58182241A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4946681A (en) * | 1972-09-07 | 1974-05-04 | ||
| JPS5549599B2 (en) * | 1975-11-27 | 1980-12-12 | ||
| JPS5410682A (en) * | 1977-06-25 | 1979-01-26 | Nec Corp | Production of semiconductor elements |
| JPS5412563A (en) * | 1977-06-29 | 1979-01-30 | Toshiba Corp | Fabricating method of semiconductor crystals |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63246208A (en) * | 1987-04-01 | 1988-10-13 | 住友電気工業株式会社 | Dicing method of semiconductor wafer |
| JPH02305207A (en) * | 1989-05-19 | 1990-12-18 | Sanyo Electric Co Ltd | Manufacture of surface acoustic wave element |
| JPH06103820B2 (en) * | 1989-05-19 | 1994-12-14 | 三洋電機株式会社 | Method for manufacturing surface acoustic wave element |
| US6996882B2 (en) | 1999-06-14 | 2006-02-14 | Matsushita Electric Industrial Co., Ltd. | Method for producing a surface acoustic wave element |
| FR2870637A1 (en) * | 2004-05-18 | 2005-11-25 | Temex Sa Sa | Crystalline structure component e.g. surface acoustic wave component, for e.g. strain gauge, has two plane sides whose circumference have plane bevels, where angles between planes of bevels and sides lie between forty five and sixty degrees |
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