JPS58179161A - Operating method for switching regulator and circuit thereof - Google Patents

Operating method for switching regulator and circuit thereof

Info

Publication number
JPS58179161A
JPS58179161A JP57061933A JP6193382A JPS58179161A JP S58179161 A JPS58179161 A JP S58179161A JP 57061933 A JP57061933 A JP 57061933A JP 6193382 A JP6193382 A JP 6193382A JP S58179161 A JPS58179161 A JP S58179161A
Authority
JP
Japan
Prior art keywords
switching
circuit
current
transistor
switching regulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57061933A
Other languages
Japanese (ja)
Inventor
Aiji Matsumoto
愛治 松本
Noboru Kato
昇 加藤
Akira Kamata
彰 鎌田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FDK Corp
Original Assignee
FDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by FDK Corp filed Critical FDK Corp
Priority to JP57061933A priority Critical patent/JPS58179161A/en
Publication of JPS58179161A publication Critical patent/JPS58179161A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/22Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33571Half-bridge at primary side of an isolation transformer

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

PURPOSE:To reduce the size and weight of a switching regulator and to enhance the reliability by operating switching elements in parallel with drive signals of different timing and equal frequency in a time division manner. CONSTITUTION:The cathode sides of rectifying diodes D1-D4 in the output circuit of the first and second converters 1, 2 are commonly connected, and an output is produced through a sole choke coil L. Switching transistors Q1-Q4 are operated completely with drive signals of different timing and equal frequency. In other words, when the transistor Q1 is ON, the current is rectified by the diode D1, when the transistor Q2 is ON, the current is rectified by the diode D2, when the transistor Q2 is ON, the current is rectified by the diode D3, and when the transistor Q4 is ON, the current is rectified by the diode D4, smoothed by a choke coil L and a capacitor C, thereby obtaining a direct current.

Description

【発明の詳細な説明】 本発明は、複チャンネル型スイッチングレギコレータの
改良に関し、更に詳しくは、主スイツチング部を時分割
パラレル運転する方法及びその方法の実施に好適な出力
整流・平滑化回路を備えたスイッチングレギュレータに
関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in multi-channel switching regulators, and more particularly, to a method for time-division parallel operation of the main switching section and an output rectification/smoothing circuit suitable for implementing the method. The present invention relates to a switching regulator equipped with a switching regulator.

大出力のスイッチングレギュレータを構成する一方法と
して、複数のコンバータ回路を並設して、これを並列運
転することによって出力電流を大きくとれるようにした
ものが知られている。
One known method for configuring a high-output switching regulator is to arrange a plurality of converter circuits in parallel and operate them in parallel to obtain a large output current.

ハーフ・ブリッジ型スイッチング部を有する2チヤンネ
ル構成の場合を例にとって説明すると、従来のこの種の
スイッチングレギュレータは、第1図に示すように構成
されていた。第1のコンバータ回路1は、2個のコンデ
ンサ01゜C2,2個のスイッチングトランジスタQl
Taking as an example a two-channel configuration having a half-bridge type switching section, a conventional switching regulator of this type was configured as shown in FIG. The first converter circuit 1 includes two capacitors 01°C2 and two switching transistors Ql.
.

C2及びトランスT1とその二次側に接続される整流ダ
イオード()1 、 [)2 、チョークコイルL1と
からなる。同様に、第2のコンバータ回路2も、2個の
コンデンサC3、C4,2個のスイッチングトランジス
タQ3 、C4反でトランスT2と、その二次側に接続
される整流ダイオード[)3 、 [)4 、チョーク
コイルL2とからなる。各コンバータ回路は直流入力を
交流に変換して変圧し、整流するもので、入出力とも共
通に接続される。
It consists of C2, a transformer T1, rectifier diodes ()1, [)2 connected to the secondary side thereof, and a choke coil L1. Similarly, the second converter circuit 2 also includes two capacitors C3 and C4, two switching transistors Q3 and C4, a transformer T2, and rectifier diodes [)3 and [)4 connected to the secondary side thereof. , and a choke coil L2. Each converter circuit converts DC input into AC, transforms it, and rectifies it, and is commonly connected to input and output.

かかるスイッチングレギュレータは、第2に示す動作タ
イミングチャートから明らかなように、第1のコンバー
タ回路1と第2のコンバータ回路2とでそれぞれ対応す
るスイッチングトランジスタを同一タンミングでオン・
オフさせるよう制御していtこ。従って、各スイッチン
グトランジスタのオン・オフ動作の周波数をfとすると
、2[なるシステムクロックで駆動されることになる。
As is clear from the second operation timing chart, such a switching regulator turns on and off corresponding switching transistors in the first converter circuit 1 and the second converter circuit 2 at the same timing.
I am controlling it to turn it off. Therefore, if the frequency of the on/off operation of each switching transistor is f, it will be driven with a system clock of 2[.

ところが、このような従来の運転方法だと、出力回路の
インピーダンスのばらつき(例えCJ1整流ダイオード
の順方向電圧降下の差異など)があるため、電流がアン
バランスになり、一方のスイッチング部が過負荷状態と
なりがちである。そこでやむを得ず、各コンバータ回路
の最終出力部にそれぞれインピーダンスの大きなチョー
クコイルを挿入して見掛は上のインピーダンスをそろえ
、回路的バランスをとることによって電流のアンバラン
スを抑えていたため、チャンネル数と同数のチョークコ
イルが不可欠であった。
However, with this conventional operation method, due to variations in the impedance of the output circuit (for example, differences in the forward voltage drop of the CJ1 rectifier diode), the current becomes unbalanced and one switching section is overloaded. It tends to become a state. Therefore, we had no choice but to insert choke coils with high impedance into the final output section of each converter circuit to make the impedances appear to be the same, and by balancing the circuit, we were able to suppress the current imbalance. A choke coil was essential.

また、上記のような従来のスイッチングレギュレータは
、低入力電圧のため各トランジスタが最大幅で動作して
いるときに、クロックの遅れやスイッチングトランジス
タの遅れ時間があると、同一コンバータ回路における複
数のトランジスタが同時にオンすることが生じてしまう
虞があるため、クロックパルスにかなり大きなデッドタ
イムを設けてやる必要があるため定電圧開始点を低くし
にくいといった欠点もあつ1こ 。
In addition, in conventional switching regulators as described above, when each transistor is operating at its maximum width due to the low input voltage, if there is a clock delay or delay time of the switching transistor, multiple transistors in the same converter circuit One disadvantage is that it is difficult to set the constant voltage starting point low because there is a risk that the clock pulses may turn on at the same time, so it is necessary to provide a fairly large dead time for the clock pulse.

本発明の目的は、上記のような従来技術の欠点を解消し
、小型軽量であって信頼性の高い高出力スイッチングレ
ギュレータの運転方法及びその回路を提供することにあ
る。
An object of the present invention is to eliminate the drawbacks of the prior art as described above, and to provide a method of operating a high-output switching regulator that is small, lightweight, and highly reliable, and a circuit thereof.

以下、本発明について詳しく説明する。本発明方法を実
施するのに必要なスイッチングレギュレータ回路は、第
1図に示す従来のものと同様のものでもよいが、第3図
に示すような回路の方が好ましい。この回路が従来のも
のと顕茗に相違する点は、出力回路の部分である。第3
図では、各整流ダイオードD1〜D4のカソード側を共
通に結線して単一のチョークコイルしを介して取出され
るようになっており、チャンネル数が増えてもチョーク
コイルが唯一個で済むように簡略化されている。その他
の回路部分は第1図に示すものと同じであるから、対応
す5− る部分に同一符号を付し、それらについての記載は省略
する。
The present invention will be explained in detail below. The switching regulator circuit required to carry out the method of the invention may be similar to the conventional one shown in FIG. 1, but a circuit as shown in FIG. 3 is preferred. The major difference between this circuit and the conventional circuit is the output circuit. Third
In the figure, the cathodes of each rectifier diode D1 to D4 are connected in common and taken out through a single choke coil, so that even if the number of channels increases, only one choke coil is required. It has been simplified to . Since the other circuit parts are the same as those shown in FIG. 1, corresponding parts are given the same reference numerals and their description will be omitted.

本発明では、第4図に示すように、4fなる周波数のク
ロックパルスを用い、各スイッチングトランジスタ01
〜Q4を、それぞれ完全にタイミングの異なる同一周波
数(「)の駆動信号51〜S4で動作させる。トランジ
スタQ1のオン時を整流ダイオードD1で、同様に、C
2のオン時をD2で、C3のオン時をD3で、C4のオ
ン時をD4でそれぞれ整流し、チョークコイルLとコン
デンサCで平滑化し、直流を得るのである。この時、チ
ョークコイルしは4fなる周波数で動作することになる
In the present invention, as shown in FIG. 4, each switching transistor 01 uses a clock pulse with a frequency of 4f.
-Q4 are operated with drive signals 51-S4 of the same frequency (") with completely different timings.When the transistor Q1 is on, the rectifier diode D1 is operated, and in the same way, C
When C3 is on, it is rectified by D2, when C3 is on, it is rectified by D4, and when C4 is on, it is rectified by D4, smoothed by choke coil L and capacitor C, and DC is obtained. At this time, the choke coil operates at a frequency of 4f.

上記実施例はハーフブリッジ型スイッチング部を有する
場合の例であるが、プッシュプル型やフルブリッジ型の
スイッチング部を有するものについても同様に本発明方
法を適用できるし、上記同様の出力回路を組込むことが
できる。な113、各スイッチング素子を、それぞれタ
イミングの異なる同一周波数の駆動信号で駆動すると6
一 は言っても、フルブリッジ型の場合には、トランスに通
電できるように、ブリッジの対辺に位置するトランジス
タ対は同じタイミングでオンしていなければならないこ
とは言うまでもない。
Although the above embodiment is an example of a case having a half-bridge type switching section, the method of the present invention can be similarly applied to a device having a push-pull type or full-bridge type switching section, and an output circuit similar to the above can be incorporated. be able to. 113, if each switching element is driven by a drive signal of the same frequency with different timing, 6
Needless to say, in the case of a full-bridge type, a pair of transistors located on opposite sides of the bridge must be turned on at the same timing so that the transformer can be energized.

次に、本発明が従来技術と顕著に相違する点について、
両者を月比しながら説明し、本発明の特徴を明らかにす
ることとする。本発明の第1の特徴は、チャンネル数が
多くなっても出力チョークコイルは唯一個で済むという
ことである。従来の通常の並列運転の場合には、コンバ
ータ回路のバランスをとるため、1回路につき1個のチ
ョークコイルが必要になるから、nチャンネル並列運転
の場合には必ずn個のチョークコイルが必要であった。
Next, regarding the points in which the present invention is significantly different from the prior art,
The features of the present invention will be explained by comparing the two. The first feature of the present invention is that even if the number of channels increases, only one output choke coil is required. In the case of conventional parallel operation, one choke coil is required for each circuit to balance the converter circuit, so in the case of n-channel parallel operation, n choke coils are always required. there were.

これに対し、本発明に係る時分割パラレル運転の場合に
は、負荷電流とチョークコイルのインダクタンスとパル
ス幅とトランスの巻数比のみで各トランジスタのコレク
タ電流が決定されるため、1個のチョークコイルで回路
間のアンバランスが生じない。
On the other hand, in the case of time-division parallel operation according to the present invention, the collector current of each transistor is determined only by the load current, the inductance of the choke coil, the pulse width, and the turns ratio of the transformer. There is no imbalance between the circuits.

第2番目の特徴は、出力チョークコイルを小型にできる
ことである。従来の通常の並列運転の場合、チョークコ
イルは主回路の2倍の周波数で動作するが、本発明によ
れば4倍の周波数で動作する。従って、臨界インダクタ
ンスは半分で済むため小型化しうるのである。第3番目
の特徴は、トランスも小型化しうろことである。
The second feature is that the output choke coil can be made smaller. In conventional parallel operation, the choke coil operates at twice the frequency of the main circuit, but according to the present invention, it operates at four times the frequency. Therefore, the critical inductance can be reduced by half, allowing for miniaturization. The third feature is that the transformer is also smaller.

従来の通常の並列運転の場合も本発明の時分割並列運転
の場合も、2チヤンネルの場合には各トランスが扱うパ
ワーは負荷に供給されるエネルギーの半分であり、電流
も半分になるが、本発明の時分割並列運転の場合、パル
ス幅が従来技術の半分であるから、動作磁束密度が半分
とむり、同一断面積のコアの場合、半分の巻数でよいし
、また同一巻数にした場合にはコア断面積は半分でよい
。第4番目の特徴は、クロックのデッドタイムが最小で
同時オンしないことである。従来のコンバータ回路では
、入力が低重し、パルス幅が最大となった時でも2個の
スイッチングトランジスタが同時にオンしないように必
ずデッドタイムが設けられていた。このデッドタイムは
素子の特性のばらつきや経年変化等を考慮しである程度
の余裕をもって設定されていた。しかし、本発明の時分
割方式では、第4図から明らかなように、コンバータ回
路において2個のスイッチングトランジスタがオンする
時間的ずれは必ずパルス幅相当分以上とれるのでクロッ
クにてデッドタイムの必要がなく、それ故、定電圧開始
点を低くとることができる。
In both the conventional normal parallel operation and the time-sharing parallel operation of the present invention, in the case of two channels, the power handled by each transformer is half of the energy supplied to the load, and the current is also half. In the case of the time-sharing parallel operation of the present invention, since the pulse width is half that of the conventional technology, the operating magnetic flux density is half, and if the core has the same cross-sectional area, half the number of turns is sufficient, or if the number of turns is the same. The core cross-sectional area can be halved. The fourth feature is that the dead time of the clocks is minimal and the clocks are not turned on simultaneously. In conventional converter circuits, a dead time is always provided to prevent the two switching transistors from turning on at the same time even when the input is low and the pulse width is maximum. This dead time has been set with a certain degree of margin in consideration of variations in characteristics of the elements, changes over time, and the like. However, in the time division method of the present invention, as is clear from FIG. 4, the time lag between turning on the two switching transistors in the converter circuit is always equal to or more than the pulse width, so there is no need for dead time in the clock. Therefore, the constant voltage starting point can be set low.

このことは、何等かの原因で瞬時的にライン電圧が下が
った場合でも定電圧特性が保証されるし、入力が切れた
ときホールド時間を長くとれることを意味し、かかる電
源を用いている機器の信頼性を向上させることができる
This means that constant voltage characteristics are guaranteed even if the line voltage drops momentarily for some reason, and that a long hold time can be taken when the input is cut off, which means that equipment using such a power supply reliability can be improved.

本発明の上記のように構成されているため、小型軽量化
が可能であり、トランスやチョークコイルの損失を低く
抑えうるし、定電圧開始点を低くでき、信頼性の高いス
イッチングレギュレータを得ることができるというすぐ
れた効果を奏しうるちのである。
Since the present invention is configured as described above, it is possible to reduce the size and weight, suppress the loss of transformers and choke coils, and lower the constant voltage starting point, making it possible to obtain a highly reliable switching regulator. This is because it has an excellent effect.

9−9-

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来技術の一例を示4回路図、第2図はその動
作波形図、第3図は本発明の一実施例を示す回路図、第
4図はその動作波形図である。 1・・・第1のコンバータ回路、2・・・第2のコンバ
ータ回路、01〜Q4・・・スイッチングトランジスタ
、TI 、T2・・・トランス、D1〜D4・・・整流
ダイオード、L、Ll 、L2・・・チョークコイル。 特許出願人   富士電気化学株式会社代  理  人
       尾  股  行  雄同       
   茂  見     棚間          荒
  木  友之助10−
FIG. 1 is a circuit diagram showing an example of the prior art, FIG. 2 is an operating waveform diagram thereof, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4 is an operating waveform diagram thereof. DESCRIPTION OF SYMBOLS 1... First converter circuit, 2... Second converter circuit, 01-Q4... Switching transistor, TI, T2... Transformer, D1-D4... Rectifier diode, L, Ll, L2...Choke coil. Patent Applicant: Fuji Electrochemical Co., Ltd. Agent: Yudo Omata
Shigemi Tanama Araki Tomonosuke 10-

Claims (1)

【特許請求の範囲】 1、スイッチング素子とトランスと、該トランスの二次
側に接続される整流部とを備え、直流入力を交流に変換
して変圧し整流するコンバータ回路を複数個並設し、入
出力を共通にして運転する方法において、前記各スイッ
チング素子を、それぞれタンミングの異なる同一周波数
の駆動信号により時分割パラレル運転することを特徴と
するスイッチングレギュレータの運転方法。 2、スイッチング素子とトランスと、該トランスの二次
側に接続される整流部とを備え、直流入力を交流に変換
して変圧し整流するコンバータ回路を複数個並設し、入
出力を共通にして運転するスイッチングレギュレータに
おいて、前記各コンバータ回路の整流部は整流ダイオー
ドからなり、各整流ダイオードからの出力を共通に接続
して、単一のチョークコイルを介して取出すようにし、
前記各スイッチング素子を時分割パラレル運転すること
を特徴とするスイッチングレギュレータ回路。
[Claims] 1. A converter circuit comprising a switching element, a transformer, and a rectifier connected to the secondary side of the transformer, and a plurality of converter circuits arranged in parallel to convert DC input into AC, transform it, and rectify it. . A method for operating a switching regulator, characterized in that each of the switching elements is operated in time-division parallel fashion using drive signals of the same frequency with different timings. 2.Equipped with a switching element, a transformer, and a rectifier connected to the secondary side of the transformer, multiple converter circuits are installed in parallel to convert DC input into AC, transform and rectify, and share input and output. In the switching regulator, the rectifying section of each of the converter circuits is composed of a rectifying diode, and the output from each rectifying diode is connected in common and taken out via a single choke coil,
A switching regulator circuit characterized in that each of the switching elements is time-divisionally operated in parallel.
JP57061933A 1982-04-14 1982-04-14 Operating method for switching regulator and circuit thereof Pending JPS58179161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57061933A JPS58179161A (en) 1982-04-14 1982-04-14 Operating method for switching regulator and circuit thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57061933A JPS58179161A (en) 1982-04-14 1982-04-14 Operating method for switching regulator and circuit thereof

Publications (1)

Publication Number Publication Date
JPS58179161A true JPS58179161A (en) 1983-10-20

Family

ID=13185466

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57061933A Pending JPS58179161A (en) 1982-04-14 1982-04-14 Operating method for switching regulator and circuit thereof

Country Status (1)

Country Link
JP (1) JPS58179161A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62203555A (en) * 1986-02-28 1987-09-08 Yokogawa Medical Syst Ltd Dc power circuit
JPH08168259A (en) * 1994-12-09 1996-06-25 Chiyoda:Kk Inverter rectifier
WO2017149906A1 (en) * 2016-03-02 2017-09-08 株式会社電菱 Switching power supply circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS518517A (en) * 1974-07-11 1976-01-23 Nippon Telegraph & Telephone CHOKURYUANTEIKA SOCHI

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS518517A (en) * 1974-07-11 1976-01-23 Nippon Telegraph & Telephone CHOKURYUANTEIKA SOCHI

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62203555A (en) * 1986-02-28 1987-09-08 Yokogawa Medical Syst Ltd Dc power circuit
JPH08168259A (en) * 1994-12-09 1996-06-25 Chiyoda:Kk Inverter rectifier
WO2017149906A1 (en) * 2016-03-02 2017-09-08 株式会社電菱 Switching power supply circuit

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