JPS58179019A - Hysteresis circuit - Google Patents

Abstract

PURPOSE:To exclude the effect of power supply drift out of the input/output voltage transmission characteristics, by providing transistors to which the output signal of a gate circuit is supplied in parallel to the input transistor circuit of the gate circuit. CONSTITUTION:When the voltage supplied to a terminal 1 is set at a low level, transistors TR11 and 12 and turned off. Then a joint P3 of both TRs has a high impedance, and therefore the voltage V'OUT is set at a high level. This voltage V'OUT varies in accordance with increment of the input voltage Vin. When the output voltage VOUT exceeds the voltage V'OUT, the characteristics of the V'OUT change to those obtained when a TR15 is turned on from those obtained when the TR15 is turned off. When the TR15 is on, the positive feedback is applied to the input side via an inverter 14 and the TR15. Thus the TR11 is kept off and TR12 kept on respectively. The input voltage does not depend on the power supply voltage since the working of the TR15 does not depend on the power supply voltage and the circuit has no constant current source 13.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hysteresis circuit, and particularly to a hysteresis circuit suitable for use in an input circuit of MO8IC (which does not include a high frequency component as an input signal).

This type O hysteresis circuit is used for noise prevention in the input circuit of general KWDBIC.
Something like the one shown in the figure has been proposed.

That is, in the figure, (1) is an input terminal to which an input signal is supplied, and this input terminal (1) is connected to each of the Fi drive elements, for example, N-channel enhancement type field effect transnosters (2) and (3). - Connected to Mizuko,
Source terminal Fi ground terminal GNDK of transistor (3)
and the source terminal is connected to the source terminal of the transistor (2), and the drain terminal of the transistor (2) is connected to the source terminal of a load element, for example an N-channel depletion type field effect transistor (4).

Further, the source terminal and f-) terminal of the transistor (4) are interconnected, and the drain terminal is connected to the power supply terminal vnoK*. These transistors (2), (3) and (4
) constitutes a folding inverter circuit. Also,
An N-channel enhancement type field effect transistor (5) is provided, the drain terminal of which is connected to the power supply terminal vD.
D, the source terminal is connected to the connection point of the source terminal of transistor (2) and the drain terminal of transistor (3), and the dirt terminal is connected to the connection point of the source terminal of transistor (4) and the drain terminal of transistor (2). Point P1
An output terminal (6) is led out from this connection point P1.

Input voltage v at a higher level (vH) than the current input terminal (1)
When 1n is supplied to the f-) terminals of transistors (2) and (3), these transistors (2) and (3) turn on, creating a low impedance between the connection point PI and the ground terminal GNDO. The potential of the connection point P1 is approximately the ground terminal GND
As a result, the output leakage (6) receives a low-level output voltage V corresponding to the GND level, which is substantially the inverted level of #'i. U, is output.

On the other hand, when the input voltage vin at a lower level (v5) than the input terminal (1) is supplied to the f-) terminals of the transistors (2) and (3), these transistors (2) and (3)
is turned off, and the impedance between the connection point P1 and the ground terminal GNDO becomes high, so that the output terminal (6) K is substantially inverted from the low level and outputs a high level output voltage V roughly equivalent to the vDD level. U? is output.

Also, a low level input voltage vim is applied to this input terminal (1).
is being applied, and when the potential at the connection point P1 exceeds the threshold voltage Vth of the transistor (5), the transistor (5) turns on and positive feedback is applied, and the connection point P
, the potential v1 of , increases, and the transistor (2) is kept completely off. FIG. 2 shows the pressure transmission characteristics of the person shown in FIG. 1.

By the way, in the case of the conventional circuit shown in FIG. 1, the input voltage, especially the high-level input voltage, depends on the power supply voltage, as can be seen from the following equation.

vL=vth+W〒+β2-') −(
1) However, in the above equations (1) and (2), vL is the low level input voltage and vH is the high level input voltage % vth
is the threshold voltage of the enhancement type field effect transistor, ■D,, #'i, the drain current when the bias potential of the star is zero, β
1. β2 vibration β, Fi transistors (3), (
2) and (5) current capacity, vDDFi power supply terminal “D
It is level D.

As can be seen from equation (2) above, the high-level input voltage depends on the power supply voltage, so the conventional circuit shown in Figure 1 has the disadvantage that the input/output voltage transfer characteristics are adversely affected by power supply drift, etc. Ta.

In view of these points, the present invention provides a hysteresis circuit that can eliminate the dependence of input voltage on the power supply.

Embodiments of the present invention will be described in detail below with reference to FIGS. 3 to 5.

FIG. 3 shows a first embodiment of the present invention. In the same figure, portions corresponding to those in FIG.

In Fig. 3, an N-channel enhancement type field effect transistor α for current sinking and an N-channel enhancement type field effect transistor (6) for input/output inversion are provided, and each of the transistors (b) and (6) is The terminal is connected to the input terminal (1), the source terminal of the transistor (11) is connected to the ground terminal GND, and the drain terminal is interconnected to the source terminal of the transistor (6). 6) is designed so that the former channel width is larger than the latter channel width, thereby allowing a large hysteresis width.

In addition, the drain terminal of the transistor θa is connected to a constant current transistor, for example, an N-channel depletion type transistor αJ.
is connected to the power supply quadrupole vDD via the source terminal and drain terminal of the transistor α1, and the y-to terminal and the source terminal of the transistor α1 are interconnected. Drain terminal of transistor (6) and source of transistor (to).

The connection point P1 of the terminal is connected to the output terminal (6)K via the inverter ←4, and is also connected to the r-t terminal of the control N-channel enhancement type field effect transistor (c), and the transistor (t) The source terminal of is connected to the ground terminal GND, and the drain terminal of the transistor α
Connection point P4 K between the drain terminal of the power and the source terminal of the transistor (6)! #Continued.

Fig. 4 shows the input/output voltage transfer characteristics of Fig. 3. In this figure, the horizontal axis is the input voltage vll11% applied to the input terminal (1), and the vertical axis is the voltage vOWT at the Fi connection point Ps.
', song #a is the characteristic when the transistor (g) is off, the curve is the characteristic when the transistor (g) is on, song -a
, d is the output voltage V obtained at the output terminal (6). U.

It is a characteristic of

Next, the operation of the circuit shown in FIG. 3 will be explained with reference to the 41st metal.

Now, when the input voltage ratio vln supplied to the input terminal (1) is at a low level, both the transistors (11) and O) are turned off, and there is a cylindrical impedance between the connection point P3 and the ground terminal GND, and the connection point P3 'Acid ratio V. LI? ' is still a valid character. And the voltage V at this connection point P. As shown in FIG. 4, LIT' changes along curve 1, which is the characteristic when the transistor (G) is turned off, as the input voltage VIn increases. This V. As UT' changes, the output voltage also changes
The output voltage V varies along 1g. The voltage V at the point when U exceeds the voltage -. The change in UT' follows the curve that is the characteristic when transistor 0→ is turned on, and then changes (descends) along the curve bK.

On the other hand, when the input voltage v111 supplied to the input terminal (1) is still at the level, the transistors α and (6) are turned on,
Voltage V at connection point P3. As shown in FIG. 4, UT' changes along a curve that is the characteristic when the transistor (2) is on. This V. Output voltage V as ut' changes. I
JT - Vary along the curve 11d, the output voltage V. . At the time f when , becomes lower than the voltage vottt', the change in the voltage voυte' now jumps towards the curve a;
It changes (rises) along the

In addition, when the transistor (to) is on, it applies positive feedback to the connection point P4 via the inverter Q4 and the transistor aυ, turns off the transistor 0, and turns off the transistor (
2) works to keep it on.

Note that the power supply dependence on the input voltage at this time is given by the following equation.

However, in the above equations (3) and (4), vL is the low level input voltage, vH is the high level input voltage, vth is the threshold voltage of the enhancement mode field effect transistor, and IDl is the zero bias potential of the depletion mode field effect transistor. drain current, βI.

The current capacity of the transistors β2 and βSFi (1, (6) and α→), vDD#i is the level of the power supply terminal VDD.

In this way, in this embodiment, the control transistor α→ is not connected to the power supply vDD, and moreover, the transistor (4
) by using a constant current type, as can be seen from equations (3) and (4) above, the
Although the .9 ram of D comes into play, in this case it can be almost ignored in practical terms, so the input voltage does not substantially depend on the power supply voltage, and as a result, the input/output voltage transfer characteristics are free from power supply drift. There will be no adverse effects such as

FIG. 5 shows a second embodiment of the present invention, in which parts corresponding to those in FIG. 3 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In this embodiment, an N-channel degradation field effect transistor aQ is used in place of the transistor αC in FIG. 3, the dart terminal of this transistor (b) is connected to the connection point P4, and the input terminal (1) (
Connect only to the f-) terminal of 6). The rest of the structure is the same as that shown in FIG. 3.

With this configuration, substantially the same effects as those of the above embodiment can be obtained in this embodiment. In addition, in this embodiment, the third
Since the degradation type transistor A4 is used instead of the enhancement type transistor OL shown in the figure, it is disadvantageous if you want to widen the hysteresis width (
In the case of a performance-type trannostar, a coefficient twice the threshold voltage Vth of the transistor is effective in converting the input voltage, and conversely, it is effective when considering the variation in the overall grossness. In addition, in FIG. 5, the input voltage may also be supplied to the transistor OQ.

As described above, according to the present invention, the dependence of the low-level and high-level input voltages on the power supply voltage is reduced, so that it is possible to prevent the adverse effects of power supply drift on the input/output voltage transfer characteristics in the hysteresis circuit. It is extremely useful for use in MO8IC input circuits used as noise countermeasures.

Note that the conductivity types of the transistors in the above embodiments are merely examples, and the present invention is not limited thereto.

Further, in the above embodiment, the case where the output signal is taken out from the output side of the inverter 04 has been explained, but it may be taken out from the input j1 or the input side of the inverter θ◆.

[Brief explanation of drawings]

FIG. 1 is a connection diagram showing an example of a conventional circuit, FIG. 2 is a diagram for explaining the operation of FIG. 1, FIG. 3 is a connection diagram showing an embodiment of the present invention, and FIG. FIG. 3 is a diagram for explaining the operation, and FIG. 5 is a connection diagram showing another embodiment of the present invention. (1υ, (6), (c) UN channel enhancement type field effect transistor, 0.α*i!N channel depletion type field effect transistor, a◆ is an inverter. Figure 1 Figure 3 Figure 4 Vin-1 and Figure 5

Claims (1)

[Claims] First and second field effect transistors are connected to both ends of the power source via a constant current source, and a third field effect transistor is arranged in parallel with the second field effect transistor,
An input signal is supplied to at least one of the first and second field effect transistors, and an output signal is taken from the output side of the first field effect transistor via an inverting means, and an output signal is output. The above third field effect transition IO
A steresis circuit characterized by supplying power to a control electrode.