JPS58178559A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device of high speed operation by forming an amorphous or polycrystalline Si island on an insulator, emitting an energy beam, and forming source and drain by a low temperature treatment in the island. CONSTITUTION:Polysilicon is superposed on an SiO2 film 22 on an Si substrate 21, B is implanted, and a P type island 23 is formed by a selective oxidation method. The substrate is heated to 350 deg.C, the overall surface is scanned by an Ar laser beam 24 to form a single crystal P type Si island 25, wet oxidized to etch the SiO2 around the island, and a gate oxidized film 26 is formed. Then, polysilicon 27 is superposed by a CVD method, are implanted with As ions 28, heat treated, and N type source and drain 29, 30 are formed in the island 25. The film 27 is selectively removed, and a gate electrode 31, and a polycrystalline layers 32, 33 to be a part or electrode of the source and drain are formed. In this manner, a high performance FET can be obtained by the heat treatment of low temperature and short time by the utilization of polycrystal capable of high speed diffusion and the formation of the source and drain from the side face of the island, and the operating speed becomes approx. twice of the conventional one. The substrate may be sapphire.

Description

Detailed Description of the Invention The present invention involves irradiating an energy beam onto a semiconductor film such as amorphous or polycrystalline silicon (Si) formed in an island shape on an insulating film, and then attaching a field effect element such as zvfO8 thereto. MO in the single-crystal Si formed on the platform to be formed or on the insulating film.
The present invention relates to the element structure and manufacturing method of a platform that forms eight elements. SOI Seiko (Si On In5ula)
tor) is expected to form a relatively small related element. Which one is crystal 1, insulated, and single crystal S! SOS that makes gold grow (5ilicon on
5anhair) There is also a method of forming a film with no crystalline structure on the amorphous film-F.

In these cases, it is not recommended to heat treat high τ products! JR
This is disadvantageous in terms of spreading of the object and miniaturization of the cords formed. For this reason, it is extremely undesirable to increase the heat treatment exceeding 1ooOC by /J11.

Therefore, in the case of the second case (Sion amorphous chiku1nsulato
r) A method is used in which only the surface layer is melted using an energy beam (laser or deuteron beam). In this case, a method is used in which a polycrystalline film is formed on the entire surface of the insulating l film and then crystallized by beam irradiation. It is not possible to form large crystal grains.

Therefore, it is practiced to melt and grow crystals by beam irradiation while leaving only the portions of polycrystalline silicon necessary for element formation in the form of islands. In this case, if the size of the island is a long island of several ton m x 1 m, and especially a small width of several μm, it is possible to obtain perfect single-crystal silicon. h7B
, 34 (12) 831 (1979), J.F.
, reported by Gibbons et al. However, the smaller the island shape, the better the performance of a completely single-crystal V, making it impossible to make a reasonably priced MOS transistor. However, if the surface area becomes smaller, there will be MOS in this part)
It becomes difficult to create transistors. i.e. 5v
iO5) Because the source, drain, and gate must be formed on the transistor platform, an island with a width of number/j m is required.
It has the disadvantage that it is difficult to make everything on the top of the tube due to the formation of the strands, and there is a problem in good cord formation.

Yet another problem is that if it is not possible to form a device with an SOI or SO8 structure, deep diffusion must be created in the source and drain in order to improve the device speed. This will be explained using Figure 1.

1 is an insulating substrate, -2 is an oxide film on the substrate 1, 3 is a silicon capacitor on the substrate 1, 4 and 5 are MOS transistor source and drain caps, 6 is a gate oxide film, and 7 is a gate base. The poles, 8, 9, and 10 are the 1st layer wires, and the 11 is the entrance oxide film. In the structure shown in m1 diagram a, the source and drain heads are mounted 4 and 6.
is formed shallower than the island region 3, and the junction area between the source, drain and the island head is large (a 1% continuous transistor, which is a feature of the SOI structure, cannot be formed).

Therefore, it is necessary to form the source and drain heads 4 and 6 on the island "head 3" so as to reach the substrate 1 as shown in FIG. In this case, heat treatment of 10oOC or more is required, but such heat treatment of high l crystals is not preferable for ICs that have many minute elements and are used during daylight hours.Also, only substrates with good heat resistance of 1 grade should be used for the substrate 1. Can not.

In the present invention, after forming a semi-quadruple island head on an insulator, this island region is irradiated with an energy beam to perform annealing, and a high-speed probe V (with a suitable source and drain structure) is further formed in the island region. This paper presents the structure of a semiconductor device that can be formed by low-temperature heat treatment and its manufacturing method.

Hereinafter, embodiments of the present invention will be explained along the lines of FIGS. 1. Figure 2 d is based on revision 21, 11
Forming an insulating group 22 made of an oxide film with a thickness of about 1 m to reduce no.
CVD (chemical vanour)
Polycrystalline Sl(
After depositing 0.5571m of silicon) film, 10”
A P-type polycrystalline St island dowel head 3 with a width of 5 l1m and a length of 40 μm is formed by introducing boron of atoms/ctrl and using a selective oxidation method, and a continuous wave Ar laser beam 24 is applied over the entire surface. irradiation to form a film-like material, preferably a P-type island 26 of monocrystalline silicon. Under these conditions, the entire substrate is heated to 350C, and the beam 24 focused to tL of about 36 μm is heated to 100 g.
/ All over the substrate 21 at a speed of 1 and 5 tops of 10 μm...]
was scanned.

After that, an oxide film (S102) for the gate was applied at 500A.
For example, 5iQ2+4 around the island area is formed by the wet d-curing method 860C to a thickness of
After forming a gate oxide film 26 on the island region, a polycrystalline silicon pattern 27 was deposited by 4,500 people using a low pressure CVL method. As ions 28 were introduced into the film 27 at a rate of 4 x 1015 tons/cm using an ion bombardment method with an acceleration energy of 100 to θV.
A heat treatment of 30 min was applied. As a result, impurities are diffused into the island region 26 from the polycrystalline Si film 27 on the side surfaces of the island region 26, and the n-type source and train regions 29.
During this process, n-type impurities are diffused from the polycrystalline Si film 27 which has a large impurity diffusion coefficient and is in contact with the entire side surface of the island region 25. Since the diffusion only needs to be extremely shallow, the north and drain regions 29 and 30 having a structure suitable for high speed can be formed in the island region 25 by heat treatment at a low temperature and in a short time. It should be noted that the heat treatment temperature may be as low as about 70°C if p (IJn) is used, for example.

Next, Si%27 is selectively removed, and the goo 1m pole 31.
polycrystalline region 3 that becomes part of the source, drain, or
2.33 is formed (2nd jdd).

As mentioned above, the method VC shown in FIG.
As mentioned above, the advantage of polycrystalline S1 is that it has a diffusion coefficient of one to two orders of magnitude larger than that of single-crystalline Si, allowing for high-speed diffusion, and the source and drain regions formed from the secondary surface of island region 1 allow for low-temperature, short-time diffusion. High-performance MOS) transistors can be easily formed by heat treatment. M thus formed
o2) The continuous layer of U/JISTA is twice that of SO8 MOS transistor using ordinary crystal.

Note that Vt(1
-value'paper pressure) control impurity ions may be implanted.

Further, in the present invention, single crystal Si may be used for the substrate 21, and the substrate 21. When a sapphire substrate is used instead of the oxidized film 22, low-temperature heat treatment is possible, so that doping of At from the sapphire substrate and lateral impurity diffusion in the north and drain regions can be suppressed.

As described above, the present invention greatly contributes to the formation of high-speed, high-performance field effect transistors, etc.

[Brief explanation of the drawing]

FIGS. 1a and 1b are conventional analytical views of an SOI structure, and FIGS. 2a to 2d are views showing the manufacturing process of a 5-shi08 IC according to an embodiment of the present invention. 21... Substrate, 22... Insulating film, 23...
・Polycrystalline Si island region, 24..., Arshi ~ the beam, 26... Island region, 26... Gate 1
Wave formation, 27... Polycrystalline Si film, 29, 30
...North. Train area, 32, 33 + 1 @ 1 North, Drano City - 9゜ Agent's name For patent attorney Toshio Nakao Haka 1 person 1
figure

Claims (1)

[Scope of Claims] (1) A semiconductor Mi region which is selectively formed on the insulator and serves as the top of the channel of the field effect transistor, and a polycrystalline semiconductor formed on the sides of the island region. What is claimed is: 1. A semiconductor device comprising source and drain regions of the transistor. (2) The semiconductor device according to claim 1, wherein part of the source and drain regions are formed within an island region. (3) The semiconductor device 1d according to claim 1, wherein the polycrystalline semiconductor is in contact with an insulator. (4) A step of selectively forming an amorphous or polycrystalline semiconductor island head region on an insulator, and irradiating the semiconductor island chain plate with energy beam 11: to cut off the 6d semiconductor island head region. a step of forming a gate insulating film of a field effect element on the semiconductor island region; and a step of forming a gate insulating film of a field effect element on the semiconductor island region; A method for manufacturing a semiconductor device that includes four steps to form direct, source, and drain overlapping structures. (6) Semiconductor device Ir according to #♂F claim 4, characterized in that impurities are spread from the polycrystalline semiconductor film into the island region 1ull to form source and drain regions.
A method for producing t.