JPS58176764A - Parallel processing system - Google Patents

Abstract

PURPOSE:To even the efficiency of plural processor units, by scattering the arbiters of the highest priority of each arbiter priority chain to the arrangement of the processor units. CONSTITUTION:When the using requests of the system bus are delivered simultaneously from the CPUs of processor units PU1, PU2, PU4 and PU5, the use of a system bus B1 is permitted first to the PU1 since the highest priority is given to the PU1. For a system bus B2, however, the PU3 having the highest priority has no request. Then an output signal line A3-2 of the corresponding arbiter is set at L, and a signal H is delivered to a signal line A4-2 from the arbiter of the PU4. Thus the use of the B2 is inhibited for the subsequent PU5, PU6, PU1 and PU2. Then a bus switch BS4-2 is turned on to permit the use of the B2. While the PU5 can use a bus B3 since it has the highest priority of the B3.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a parallel processing system in which n processor units are coupled to one system bus via a series switch.

Traditional computer systems have a system bus.

For example, there are systems that are composed of a plurality of buses classified by speed, such as a high-speed bus, a medium-speed bus, and a low-speed bus, and connect these system buses to a processor (CPU). In this computer system, each processor is assigned to either a high-speed bus, a medium-speed bus, or a low-speed bus, so for example, if the high-speed path is occupied by another processor, the high-speed path will not be allocated. Other processors cannot use the high-speed path, nor can they communicate via other medium-speed buses or low-speed buses, and the processors have to wait (WAIT). Therefore, despite having multiple buses, the system had the drawback of poor total processing capacity and poor performance.

Second, when one bus goes down, the processor connected to that bus becomes unusable, causing the system itself to immediately go down. In addition, in parallel processing systems, there are cases where it is desired to distribute the load depending on the purpose of the system. In such a case, since processing will be distributed to each processor unit, it is desirable that the efficiency of each processor unit be equalized.

One object of the present invention is to provide a parallel processing system in which the above-mentioned drawbacks of the conventional system are overcome and the system bus can be used by any processor unit, and the efficiency of each processor unit is made uniform.

In order to achieve the above object, the parallel processing system of the present invention includes a CPU in each processor unit.

The arbiter of the processor unit is provided with one arbiter that controls on/off of bus switches in a predetermined order, and the arbiter of the processor unit is connected in series corresponding to the system bus, and determines usage priority for each system bus. arbiter priority chains of columns are formed, and the highest priority arbiters of each arbiter priority chain are arranged to be distributed with respect to the arrangement of the processor units, and the highest priority arbiters of each arbiter priority chain are arranged to be distributed with respect to the arrangement of the processor units, and the The configuration is such that each processor unit can use a free system bus.

The present invention will be explained in detail below with reference to an embodiment shown in one drawing.

FIG. 1 is a block diagram of a parallel processing system showing one embodiment of the present invention. In the same figure, PUl, Pu2...
Pu6 is connected to the processor units Bi, B2 and B to the system bus, and CM is connected to the system buses B1, B2 and B3, and is a shared memory that can be accessed simultaneously from any of the system buses B1, B2 and B3.

The controller unit PUi is the bus switch B51-1.
Through the system bus B I K, bus switch Bs1
-2 to system bus B2 via bus switch B51.
-'5 to the system bus Ba.

The processor unit) Pu2 connects to the system bus B1 via the bus switch B52-1, to the system bus B2 via the bus switch B52-2, and to the system bus B2 via the bus switch B52-2.
3 to the system bus B3.

The processor units RJ3, Pu4, Pu5, and Pu6 are also connected to the system buses B1, B2, and B3, respectively, in the same manner as the processor units) PU1 and Pu2. .

dl, d2...d6 are each processor unit P1
・B2... Data information and address information of B6, al-1, al-2, al-3, B2-1, B2-
2・a 2-3 ,・・・・・・・・・+a6-1・B
6-2 and B6-3 are bus switches B51-i, respectively.
・B51-2・BS 13 + BS 2-1・B
S2-2・B52-6. .......

This is an on/off control signal for BS 6-1, BS 6-2, and BS 6-3.

Figure 2 shows processor unit PUI/Pu2...
FIG. 6 is a block diagram showing the internal configuration of BI6. As shown in the figure, PUi is one CPU113
It is equipped with arbiters AB1-1, ABI-2, and AB1-3. Also, processor units) Pu2 is one C
PU2, 3 arbiters AB2'-1・AB2-2・A
B2-3 and other processor units PU3 and
Pu4...Pu6 Processor unit P[J
It has a circuit similar to l.Pu2.

Each arbiter A B i-1, A B 1-2, ABl-
5+ AB 2-1 ・ AB2-2 ・ AB2-
3. ......, AB/, -i ・A B 6-
2.AB6-3 is the 2 input terminal of BPRN and RQ.

When an L signal is applied to the ANS terminal, an H signal is output to the BPRO terminal, and after a while, the ANS terminal r is applied to the ANS terminal r.
It is designed to output a signal.

In processor unit PU1, system bus use request signal (hereinafter referred to as request signal) RQT is sent from CPU1.
l is the RQ terminal of arbiter A B 1-1 and gate G 1
-1 to one end of the input of arbiter AB1-1, and B of arbiter AB1-1.
The PRO terminal output is also applied to the input terminal of the gate 1-Gl-1. The output of the gate circuit G1-1 is applied to the RQ terminal of the arbiter AB1-2 and one end of the input of the gate circuit G1-2, and the BPRO terminal output of the arbiter AB1-2 is also applied to the other input terminal of the gate circuit G1-2. It can be added. Furthermore, the output of the gate circuit G1-2 is applied to the RQ terminal of the arbiter AB1-3. Furthermore, arbiter AB1-1・AB1-2・ABl
The L signal of each ANS terminal of -3 is connected to each bus switch B S
1-1 - Output to turn on B51-2 and B51-3. Regarding the connection configuration of the above CPU, arbiter, and gate circuits, see Processor Units) PU2 and PU3.
...Also in PU6.

It has exactly the same connection configuration as processor unit PU1.

The BPRN terminal of arbiter AB1-1 is connected to ground,
The BPRO terminal of arbiter A B 1-1 is the signal line A1-
1 to the BPRN terminal of the arbiter AB2-1, and the BPRO terminal of the arbiter AB2-1 is connected to the signal line A2-
Similarly, the BPRO terminal of the arbiter is sequentially connected to the BPRN terminal of the arbiter of the next stage processor unit. -1・
...Ar6-1 are connected in series. These arbiters AB1-i, Ar2-1...A B6-1 are connected in series to form an arbiter priority chain that determines the usage priority of system bus B1.
1, the highest priority is given to the processor unit PU1, and the priority becomes lower as the processor units are located on the right side.

Also, arbiter A B 1-2・Ar2-2...A
B&-2 are connected in series to form an arbiter priority chain that determines the priority of use of system bus B2.

In this arbiter priority chain, the BPRN terminal of arbiter AB-2 is connected to ground, and the BPRO terminal of arbiter AB3-2 is connected to arbiter AB4 via signal line A3-2.
-2 is connected to the BPRN terminal of arbiter AB4-2.
The PRO terminal is connected to the arbiter AB5- via the signal line A4-2.
Arbiter A B
6-2., ^B1-2, Ar2-2 are connected in series in sequence. In other words, regarding the system bus B2, the highest priority is given to the processor unit PU3, and the following processor units PU4, PU5, PU
Priorities are given in the order of 6.PUl.PU2.

Similarly, arbiter AB1-6・Ar2-3...Ar
6-3 are connected in series to form an arbiter priority chain that determines the usage priority of system node B3.

This arbiter priority chain is B of arbiter AB5-3.
PRN terminal is connected to ground and arbiter 5-30BPR
I;) terminal connects to arbiter A B via signal line A3-5
Arbiter AB6-3 is connected to the BPRN terminal of AB6-3.
BPRO terminal is connected to arbiter AB via signal line A6-3.
It is connected to the BPRN terminal of I-3, and similarly connected in series with arbiters A B 2-3, Ar3-3, and Ar1-3. In other words, regarding the system unit B6, the highest priority is given to the processor unit PU5 (hereinafter referred to as processor unit PU6), PU6, PUI, PU2.
-Priority is given in the order of PU3 and PU4. The priority order of each processor unit for each system bus is shown in FIG.

In the parallel processing system connected and configured as described above, if the request signal RQTI for system bus use is output from the CPU 1 of the processor unit PU1, an L signal is applied to the RQ terminal of the arbiter A B 1-1. However, since the L signal is applied to the BPRN terminal of arbiter AB1-1, arbiter AB1-1
derives an H signal to the BPRO terminal. And the following arbiter AB2-1 ・Ar5-1...A B 6
After sequentially setting each BPRN terminal of arbiter B1-1 to an H signal and prohibiting the use of system hash B1 by subsequent processor units, the L signal a1-
Outputs 1. In this case u K open arbiter B 1-
1 (7) BPRN terminal, BPRO end 4'-, arbiter A
FIG. 4 shows the signal waveforms at the BPRN terminal and BPRO terminal of B2-1, AB 3-i, and Ar1-1, and the signal waveform at the ANS terminal of arbiter AB1-i. According to the figure, the BPRO terminal of arbiter A B 1-1 becomes an H signal, and then the arbiters AB2-1, Ar3-1, A
The ANS terminal of the arbiter AB1-1 becomes an L signal at the timing after each BPRO terminal of r1-1, . . . becomes an H signal.

The ANS terminal of arbiter AB1-1 becomes an L signal, and this L
The signal is output as signal a1-1 and the bus switch B S
1-1 is turned on. When bus switch B 5IL1 is turned on, the processor unit PUI
1, data information/address information d1 is sent. In this way, when a request to use the system bus B1 is issued in the processor unit PU1, the system bus B1 can be used unconditionally, and the processor unit PU1 is given the highest priority for using the system bus B1.

For example, if CPU4 of processor unit PU4 issues a request to use the system bus, signal line A3-
If 1 is an L signal (in other words, processor unit) PUi
, If PO2/PO2 is not using system bus B1, BPRO is activated at BP of arbiter A B 4-i.
When the H signal is output to the terminal, the signal prohibits the use of the system bus B1 of the processor unit from now on, and after a certain period of time, the ANS
Output the L signal from the terminal and turn on the bus switch B54-1 to connect the processor unit PU4 to the system bus B1.
join to.

However, if any one of the processor units PU1, PO2, Yen] is using the system bus B1 and the signal line A3-1 is an H signal, the arbiter A
B The 4-1 BPRN terminal is H, the RQ terminal is L, and B
The PRO terminal is connected to system bus B by the subsequent processor.
1. An H signal that prohibits use is derived.

Since the L signal is not output to the ANS terminal, the bus switch B
54-1 is not turned on, and therefore system bus B1 cannot be used.

For example, processor units l-PUI, PO2,
If a request to use the system bus is granted from CPUs 1, 2, 4, and 5 of PO4 and PO5 at the same time, first the processor unit)PUl is given the highest priority, so the system bus B'1 is used by the processor unit)PUl. given to. In other words, an H signal is output to the BPRO terminal of arbiter AB1-1 and the subsequent processor unit FU2.P
O2...Prohibits use of system bus B1 of PH1 and outputs an L signal to the ANS terminal of arbiter AB1-1. In the processor unit PO4, the system bus B1 is occupied by the processor unit PU1.

Permission to use system bus B1 is not granted. However, permission to use the system bus B2 is granted. In other words, since PO2 (the processor unit with the highest priority) is not issuing a request signal, the signal line A3-2 is an L signal, and the signal is sent from the CPU 4 to the arbiter A B via the gate G4-1.
When an L signal is applied to the RQ terminal of 4-2, arbiter A
Outputs an H signal to the BPRO terminal of B4-2, and then outputs an H signal to the BPRO terminal of B4-2, and then outputs the H signal to the BPRO terminal of B4-2, and then outputs the H signal to the BPRO terminal of
The use of system bus B2 of arbiter AB4-2 is prohibited, and after a while an L signal (B4-2
) is output, and the bus switch BS4-2 is turned on. In addition, in the processor unit PU5, the signal line A4-
Since 1 and A4-2 are H signals, system buses B1 and B2 cannot be used, but since the BPRN terminal of arbiter A B 5-3 is always an L signal, system bus B3 is given the highest priority. Therefore, C.P.
Arbiter AB from U5 via gates G5-1 and G5-2
When the L signal of RQT5 is applied to the RQ terminal of 5-3, the arbiter A outputs the H signal to the BPRO terminal of 5-3, and the subsequent processor units) PH1, PUl...
The use of system bus B6 is prohibited. After a while, an L signal (A5-3) is output to the ANS terminal of the arbiter AB5-3, and the processor unit PU5
is given permission to use system bus B3. On the other hand, the processor unit PU2 receives request signals from other processor units with higher priority for each system bus, and receives signals from the signal lines A1, -1, A1-2, and A1-5.
Since both become H signals, system buses B1 and B2
・Use of B3 is not allowed. Instead, wait until one of the system buses becomes free.

If processor unit RJ2/PO2/PO4/P
If use requests are issued from O5 at the same time, according to the priority order shown in FIG. 6, processor unit PU2 is allowed to use system bus B1, and processor unit PU3 is allowed to use system bus B2.

Processor unit PU5 is allowed to use system path 13°, but processor unit PU4
will wait until one of the system paths becomes free.

According to this embodiment, for each processor unit, at least one of the system paths is given first or second priority, so the degree to which each processor unit can use the system bus is averaged.

Although the above embodiment has been described with reference to six processor units and six system paths, it goes without saying that the present invention is not limited to these numbers.

As described above, according to the parallel processing system of the present invention, each processor unit is equipped with one arbiter that controls on/off the bus switches in a predetermined order in addition to the CPU.
These arbiters are connected in series corresponding to the system paths to form an arbiter priority chain that determines system bus usage priority, and each processor unit selects a vacant system path according to the priority according to this arbiter priority chain. So you can use it.

One of the i system paths can be efficiently used by n processors without causing contention. Since contention can still be avoided and the waiting time of each processor can be reduced, the processing power of the entire system can be improved. Furthermore, since the highest priority arbiter of each arbiter priority chain is distributed so as to be distributed with respect to the arrangement of processor units, the time saved for each processor can be averaged, and the processing time during load distribution processing can be equalized by +1. Therefore, the entire system can be operated efficiently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a parallel processing system showing an embodiment of the present invention, FIG. 2 is a block diagram showing the internal configuration of a processor unit which is a main part of the parallel processing system shown in FIG. 1, and FIG. FIG. 3 is a diagram showing priorities for each system bus of each processor unit. FIG. 4 is a diagram showing the operation timing signal waveform of the arbiter shown in FIG. 2. PUi ・PU2...PU6: Processor unit. B1/B2/B3: System path, B51-4
・B11-2・B51-3. BS 2-1・B52-
2・B52-3・・・・・・・・・・B56-1
・B56-2・B56-5: Bus switch. CM: Shared memory, 1, 2...6: CPU
. ABl-1・ABl-2・AB i-3, AB2-1
・AB2-3.・・・・・・・・・, AB5-j j
AB5-2・AB5-31...: Arbiter,
G1-1・G1-2, G2-1・G2-
2,...G5-1・G5-2,...two-gate circuit. Patent Applicant Tateishi Electric Co., Ltd. Agent Patent Attorney Shigeru Nakamura Nobuaki, Figure 3 Salt Figure 4

Claims (1)

[Claims] (1) A parallel processing system in which n processor units are each coupled to one system bus via a bus switch. Each of the processor units is equipped with a CPU and i arbiters that control on/off of the bus switches in a predetermined order, and the arbiters of the processor units are connected in series in correspondence with the system bus to control the system bus. An i-column arbiter priority chain is formed that determines usage priority for each bus, and the highest priority arbiter of each arbiter priority chain is arranged so as to be distributed with respect to the arrangement of the processor units, and the arbiter A parallel processing system characterized in that each of the processor units is configured to be able to use a vacant system bus according to the priority order of a priority chain.