JPS58173251U - 集積回路 - Google Patents

集積回路

Info

Publication number
JPS58173251U
JPS58173251U JP1982070459U JP7045982U JPS58173251U JP S58173251 U JPS58173251 U JP S58173251U JP 1982070459 U JP1982070459 U JP 1982070459U JP 7045982 U JP7045982 U JP 7045982U JP S58173251 U JPS58173251 U JP S58173251U
Authority
JP
Japan
Prior art keywords
power supply
terminals
chip
integrated circuit
ground
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982070459U
Other languages
English (en)
Inventor
純 小池
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP1982070459U priority Critical patent/JPS58173251U/ja
Publication of JPS58173251U publication Critical patent/JPS58173251U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は、ＩＣチップをケースに組み込んだ状態を概略
的な立体図で示したものであり、１・・・・・・２点ボ
ンディング、２・・・・・・ＧＮＤ端子、または電源端
子、３・・・・・・ボンディング線（ボンディングワイ
ヤ）、４・・・・・・チップ、５・・・・・・ケースで
ある。 第２図はチップレイアウトのＧＮＤ端子端子法たは電源
端子廻りΩ部分図を示したものであり、２・・・・・・
ＧＮＤ端子または電源端子、６・・・・・・ＧＮＤ線ま
たは電源ラインである。 第３図は、本考案の一実施例の１チツプマイクロコンピ
ユータのレイアウトの概要をＧＮＤに関係した部分につ
いて示したものであり、２・・・・・・ＧＮＤ端子、６
・・・・・・ＧＮＤ線、７・・・・・・電源端子、８・
・・・・・ＡＬＵ、９・・・・・・命令デコーダ、１０
・・・・・・内蔵ＲＯＭ、１１・・・・・・内蔵ＲＡＭ
である。

Claims (1)

    【実用新案登録請求の範囲】
  1. 集積回路チップ上、複数個の接地端子、あるいは複数個
    の電源端子を持ち、接地端子各々、あるいは電源端子名
    々がチップ上、電気的に分離され、かつ前記複数個の接
    地端子、あるいは、前記複数個の電源端−子に、各々同
    一接地レベルあるいは電源レベルを印加し、かつ該複数
    個の接地端子あるいは、複数個の電源端子は、チップ外
    の１個の電極に接続されていることを特徴とした集積回
    路。
JP1982070459U 1982-05-14 1982-05-14 集積回路 Pending JPS58173251U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982070459U JPS58173251U (ja) 1982-05-14 1982-05-14 集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982070459U JPS58173251U (ja) 1982-05-14 1982-05-14 集積回路

Publications (1)

Publication Number Publication Date
JPS58173251U true JPS58173251U (ja) 1983-11-19

Family

ID=30080130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982070459U Pending JPS58173251U (ja) 1982-05-14 1982-05-14 集積回路

Country Status (1)

Country Link
JP (1) JPS58173251U (ja)

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