JPS58171856A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the collector resistance of a transistor and thus change it into high dv/dt strength by a method wherein a low resistance layer of resistivity lower than that of the single crystal Si region in an inductor isolation substrate and of the same conductivity type, and a transistor is formed in this low resistance layer. CONSTITUTION:The n<+> low resistance layer 34 is formed in the n type single crystal Si region 33 which is insulation-isolated by an oxide film 32 for inductor isolation and supported by a polycrystalline Si 31, and an n<++> collector layer 37, an n<++> emitter layer 36, and a p-base layer 35 are formed. Further, a stabilization film 38 is laminated on the sufaces thereof, and accordingly an n-p-n transistor is constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device using a dielectric isolation substrate, and more particularly to a semiconductor integrated circuit device including a transistor that achieves a high 4V/dt withstand capability.

In order to prevent dv/di misfiring (or rate effect) in a thyristor, inserting a resistor between its gate (G) and cathode (K), called a short emitter, is already known.

However, with this method, it is known that when the resistance is reduced in an attempt to improve the dν/dt withstand capability, the gate sensitivity decreases and the holding current increases, which is a major problem in semiconductor integrated circuits including thyristors. It is a book.

Thyristor dv to solve the above problems
An example of the /dt protection 11 circuit is shown in Fig. II1.

#11 On the right in the diagram, thyristor 1 is a p emitter.

It consists of four layers: n base, p base, and n emitter. And between G (gate) and K (cathode) ~
High resistance of 10 Ω 3. and a collector, p pace,
An npn transistor 2 consisting of three layers of n emitters is connected.

A capacitor 4 is provided between the base B of the mirror transistor 20 and the anode A of the thyristor, and a diode 5 is provided on the opposite side between the base B and the emitter E of the transistor 2. Note that numeral 1 represents the anode of the thyristor 1, and C represents the collector of the transistor 2.

In this circuit, when a forward voltage is suddenly applied to the anode A of the thyristor I, the central pn junction J is charged, and this charging current flows into the third pn junction J.

, the thyristor l turns on (rate effect).

However, due to the presence of resistor 3, this charging voltage is l1lW
II will be done. Therefore, the thyristor l will not turn on until the charging current becomes large and the voltage across the resistor 3 reaches the built-in voltage of the thyristor 1. When the rise of the forward voltage becomes further distant, the charging current in the capacitor 4 flows to the base of the transistor 2, and the transistor 2 is driven to an on-state lIK.

In this way, by lowering the impedance of transistor 2 to its saturation resistance, the resistance of thyristor L appears to be smaller than the G- resistance of thyristor L. remains off.

However, if the collector resistance of the transistor 2 in the on state is large, the resistance between the G- terminal of the thyristor 1 also becomes apparently large. Therefore, at this time, the thyristor I is turned on, and the insect dv/dt tolerance cannot be obtained.

In a typical integrated circuit, the thyristor and transistor discussed are formed on the same St substrate.

FIG. 2 shows a cross-sectional view of the circuit element shown in FIG. 1 in which a thyristor and a transistor are formed within a single crystal island on the same dielectric insulating substrate.

In FIG. 2, lO is a dielectric wire substrate, in which a single crystal silicon region (island) 11, 12 is insulated and supported on polycrystalline silicon 15 via dielectrics 13, 14 such as StO. It is something.

Both regions 11 and 12 have n11 conductivity, and acceptor and donor impurities are selectively diffused from the upper main surface, thereby forming a thyristor and a transistor as shown.

A surface stabilizing film 16 such as SIO is provided on the upper main surface of the substrate 10, and through openings provided therein,
Wiring lines 17 to 23 formed by Aj and the like are in ohmic contact. In addition, 24.21! is single crystal silicon region 1
This is a highly impurity region for ohmic contacts No. 1 and No. 12.

like this! In the structure, the single crystal silicon region 11-, in which the thyristor is formed, ie, the starting substrate +1. In order to achieve high voltage resistance, high resistance is required8. In this case, the single-crystal silicon region 12 forming the transistor also becomes a block resistance because the starting substrate is usually the same, and this becomes the collector resistance as it is. Therefore, in a large current region, this causes a decrease in the current leakage increase rate hFE of the transistor, resulting in a poor dv/dt tolerance.

FIG. 4 shows this state, and the dotted line in the figure indicates the collector voltage [(horizontal axis) vs. current amplification factor (vertical axis) I? of the transistor fabricated according to the conventional example. An example of monosexuality is shown. From this, it can be seen that as the collector current becomes redder, the current amplification factor hFE decreases.

As a method of compensating for such drawbacks, a method can be considered in which a low-resistance layer is partially formed (for example, by epitaxial growth) as necessary, and the transistor described above is formed.

However, when trying to adopt the epitaxial growth method, for example, it is necessary to heat the entire substrate to a high temperature, and in particular, selective epitaxial growth requires more complicated equipment and processes, resulting in higher costs, which is industrially disadvantageous. It is.

As described above, integrated circuit devices using conventional technology require a silicon layer with high resistivity in order to achieve high breakdown voltage, and high d
In order to achieve v/d t , a silicon layer with a low resistivity is required, and there has been no solution to the problem of having to form silicon layers with contradictory resistivities on the same substrate.

An object of the present invention is to improve resistivity as a means for achieving high withstand voltage and high dv/dt withstand capability in a semiconductor integrated circuit device in which a high withstand voltage circuit element and a low withstand voltage circuit element are integrated on the same substrate. An object of the present invention is to provide a semiconductor integrated circuit device having a transistor with low collector resistance when a high silicon substrate is used.

The 41I mold of the present invention which achieves the above object is provided with a low resistance layer of the same conductivity type, which has a resistivity lower than that of the single crystal silicon region in the base cast electric isolation substrate on which the transistor is formed. , to form a transistor within this low resistance layer.

An embodiment of the present invention will be described below with reference to the drawings.

, 1 FIG. 3 shows a cross-sectional structure of an npn transistor according to the present invention. Note that illustration of the thyristor and the protection circuit is omitted.

npn) transistor is formed by forming an n+ low resistance layer 34 in an n-type single crystal silicon region 33 isolated by 810.32 and supported by polycrystalline silicon 31, and forming an n++ collector layer in the layer 34. 37, an n++ emitter layer 36 and a p paste layer 35 are formed, and a stabilized phlegm 38 is further laminated on these surfaces.

The solid line in FIG. 4 shows the relationship between the collector current (Ia) and the current amplification factor (hFE) of the transistor in FIG. tv
For example, in the case of the integrated circuit implemented by the inventors, the performance of the npn transistor necessary to improve the /dt withstand capacity is as follows:
The current amplification factor hFE is 10 or more.

In the conventional example, as is clear from FIG. 4, in this current range lζ, the current amplification factor hFE significantly decreases due to the influence of the collector resistance. In comparison, according to the present invention, the decrease is small and a current amplification factor hFE of 10 or more is obtained.

The conventional device used for the measurements in FIG. 4 only lacks the n+ low resistance layer 34 in FIG. 3, and the other structures and manufacturing processes are the same as those in the embodiment of the present invention.

FIGS. 5(1) to 5(6) are explanatory diagrams of the method for manufacturing a semiconductor integrated circuit device of the present invention.

) First, n-type single crystal silicon 33 with plane orientation (100)
is subjected to high temperature heat treatment to form an oxide film 39. Next, an opening 39A is partially formed by photoetching.

(2) Using the # coated film 39 as a protective mask, 8 V-shaped grooves 4G1 are formed using an alkaline etchant.

+3) The oxide film 39 is removed and a new oxide film 32 of the KIII electronics branch is formed. □ (4) A polycrystalline silicon layer 31 that will serve as a support for the electric body and substrate is formed thereon. Next, the single crystal silicon 33 is removed down to the A- plane by polishing, etching, etc., thereby completing a dielectric isolation substrate in which each single crystal region is electrically isolated.

(5) Ion implantation 42 from the single bond 6 yen of the dielectric isolation substrate
Then, an n-medium low resistance layer 344 is formed. The impurity in this case is phosphorus (P), and unnecessary portions are protected by a resist 41.

Here, the impurity concentration of the n medium low resistance layer 34 is higher than that of the single crystal silicon region (substrate) 33, but it is important that it is not too high. This is because if the p base of an npn transistor forms a junction in a high impurity concentration area of the low resistance layer, the subsequent n emitter diffusion will thin the actual p base layer, making punch-through more likely to occur. This is because the emitter collector breakdown voltage decreases.

Therefore, this impurity concentration control requires high precision.

Therefore, the present inventors decided to form the n+ low resistance layer by ion implantation, and found the optimum value through experiments with different implantation amounts.

(6) Finally, a thick oxide film 38 is formed to ensure high breakdown voltage of the thyristor. This process (J,
St is oxidized by heat treatment at high temperature and for a long time in a steam atmosphere or an oxygen atmosphere.

This treatment lowers the surface concentration of the n-medium low resistance layer formed in the previous step 1 (5) and promotes diffusion, which will be formed later.
This is achieved by making the resistance under the p-base of the npn transistor sufficiently small.

Next, high-voltage and low-voltage circuit elements such as thyristors, transistors, and diodes are formed by diffusing impurities such as boron (B) and phosphorus (P) to complete the integrated circuit. However, illustration is omitted in FIG. 5.

In FIG. 3, in order to determine the conditions for forming the n medium low resistance layer 34, the inventors conducted an experiment by changing the ion implantation amount at 14 points.

FIG. 6 shows the ion implantation amount (horizontal axis), the sheet resistance of the -low resistance layer, the collector voltage 111c set to 10 mA, and Vc
Shows the current increase, peak, and emitter collector breakdown voltage BVzco when the voltage is 0.5 . The Δ mark is data based on the conventional example, that is, when the n medium low resistance layer 34 is ρ.

In FIG. 6, the emitter-collector breakdown voltage was previously shown on an overscale scale, and the other current amplification factors, sheet resistance of the n low resistance layer, and ion implantation amount were not shown on a logarithmic scale.

As can be seen from FIG. 6, as the amount of ion implantation increases, the sheet resistance of the n medium low resistance layer 34 decreases, and the current amplification factor hFE becomes insignificant. However, if the sheet resistance drops too much, the withstand voltage will drop extremely. Therefore, as described above, impurity concentration control requires high precision.

According to the data shown in FIG. 6, the withstand voltage becomes IV or less after 3×10 brocade ion implantation. Therefore, it cannot be used in integrated circuits that require a withstand voltage of 5 or more. However, d
v/dt capacity bag - npt used in the circuit> Since the operating voltage of a transistor is approximately O, S V,
A pigeon coop in which 3×10” or more ions are implanted to form an n soil layer and increase the current amplification factor is also usable.

As described above, the current amplification factor of an npn transistor equipped with an n+ low resistance layer formed by ion implantation is 2 or more in the large current region compared to the conventional example, and an integrated circuit using this dv/dt tolerance is also 200 V
/us@degrees improved to over 2000 v/u1.

Next, the planar structure of the npn transistor according to the present invention was studied.

Figure 97.8 shows the planar pattern of an npn) transistor. ζ In the straw diagram, the transistor is p-base 51.
n++ emitter 52. n++ collector 53. and respective contact openings 54-56. As is clear from the comparison between FIGS. 7 and 8, both have a structure in which an n++ formation region 53 connected to the collector electrode surrounds the p base,
There are structural differences where this is not the case.

FIG. 9 shows the relationship between the collector current and current amplification factor of the transistor. In the figure, the solid line represents the characteristics due to the structure in Figure 7, and the dashed line represents the characteristics due to structure #C in Figure 8.

The same tendency as in Fig. 4 can be seen here as well; in an npn (npn) transistor with a -low resistance region, a higher current amplification factor is obtained when the n++ collector is formed in a p-based IILM structure. can get.

As is clear from the above explanation, (1) according to the present invention, the collector resistance of the NPN transistor used in the integrated circuit (NPN) transistor used in the withstand voltage protection circuit is reduced, and the current amplification factor in the large current region is more than twice that of the conventional one. Nidedai, that's not good w/
d with a 410 times improvement in tolerance.

Note that although the example above has been described in which an oxide film for dielectric isolation is formed on the entire boundary between polycrystalline silicon and single crystal regions, this is not always necessary;
At part or all of the boundary, the polycrystalline silicon and the single crystal region may be directly aligned.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of a thyristor dv/dt withstand capacity maintenance circuit, Fig. 2 is a cross-sectional view of a thyristor and an npn transistor formed on the same monoelectric substrate, and Fig. 3 is a cross-sectional view of a thyristor and an npn transistor according to the present invention. 1115WA11) to (6) are cross-sectional views of the manufacturing process of the semiconductor integrated circuit device of the present invention, and FIG. 6 is a cross-sectional view of the npn transistor. Figures 7 and 8 are diagrams showing the relationship between the ion implantation amount and other characteristics of the npn transistor according to the present invention.
n) Diagram showing the planar structure of the transistor, Fig. 9 is the 7th
FIG. 11 is a diagram showing the relationship between collector current and current amplification factor in the cases of FIGS. 31... Polycrystalline silicon, 32... Haze electrical isolation oxide film, 33... N-type single crystal silicon region, 34...
-Low resistance layer, s Toru base layer, 36...n++ engineering ivy layer, 37, , , ++ collector layer, 38...
Stabilizing membrane proxy valve 1 Michihito Hiraki Diagram 1: A#2 Diagram O 3I23 24g5 Collector electric hole (mA) 5 Diagram 6 Koii iZN included 1 (47cm 勺 ion J1 included - I) 1/C 17th figure 28th figure 9th figure [Lid (mA)

Claims (2)

[Claims] (1) A semiconductor integrated circuit device in which a plurality of single-crystal silicon regions are formed on a dielectric isolation substrate insulated from each other and supported by polycrystalline silicon, wherein at least one of the single-crystal silicon regions is A first semiconductor region having a high impurity concentration is formed in the single crystal silicon region with the same conductive lid, and a second semiconductor region having an opposite conductive layer is formed in the first semiconductor region, A third semiconductor region with a high impurity concentration is formed in the second semiconductor region with the same conductive lid as the first semiconductor region, and
In the semiconductor region, a fourth semiconductor region with high impurity concentration is formed with the same conductive lid as the first semiconductor region at a position opposite to at least the opening in the outline of the second semiconductor region, Said 1st. Second. A semiconductor integrated circuit device characterized in that the third and fourth semiconductor regions constitute transistors. (2) A patented integrated circuit device characterized in that the sheet resistance of the first semiconductor region directly below the second semiconductor region is 2.07 or less.