JPS58170848U - Electronic component package - Google Patents

Electronic component package

Info

Publication number
JPS58170848U
JPS58170848U JP6835182U JP6835182U JPS58170848U JP S58170848 U JPS58170848 U JP S58170848U JP 6835182 U JP6835182 U JP 6835182U JP 6835182 U JP6835182 U JP 6835182U JP S58170848 U JPS58170848 U JP S58170848U
Authority
JP
Japan
Prior art keywords
chip
electronic component
component package
package
ground
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6835182U
Other languages
Japanese (ja)
Inventor
五十嵐 丈美
清之 小桧山
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP6835182U priority Critical patent/JPS58170848U/en
Publication of JPS58170848U publication Critical patent/JPS58170848U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の電子部品パッケージを示す平面、図ミ第
2図はその中央横断面図、第3図は本考案によ゛る電子
部品パッケージを示す平面図、第4図はその中央横断面
図である。 2・・・・・・チップ、3・・・・・・外部リード線、
36・・・・・・     ′グランド線、35・・・
・・・信号線、4,7・・・・・・連結線、6・・・・
・・グランド層、8・・曲モールド、9・・曲挿入  
    □端子、11・・・・・・電子部品パッケージ
FIG. 1 is a plan view showing a conventional electronic component package, FIG. 2 is a cross-sectional view of the center of the package, FIG. It is a front view. 2... Chip, 3... External lead wire,
36...' Ground wire, 35...
...Signal line, 4,7...Connection line, 6...
...Ground layer, 8..Song mold, 9..Song insertion
□Terminal, 11...Electronic component package.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板に回路素子を作り込んで素子間配線をしたチップの
周辺のポンディングパッドと外部リード線とを連結線で
接続して上記チップを封入してなる電子部品パッケージ
において、該チップの下方又は上方の近傍に上記外部リ
ード線の端末部までのびるグランド層を埋め込み、上記
チップのグランドパッドをグランド線に接続すると共に
上記グランド層にも接続したことを特徴とする電子部品
In an electronic component package in which the chip is encapsulated by connecting bonding pads around the chip with circuit elements built on a substrate and interconnections between the chips and external lead wires using connection wires, the chip is enclosed in a package that is located below or above the chip. An electronic component characterized in that a ground layer extending to the end of the external lead wire is embedded near the terminal, and the ground pad of the chip is connected to the ground line and also connected to the ground layer.
JP6835182U 1982-05-11 1982-05-11 Electronic component package Pending JPS58170848U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6835182U JPS58170848U (en) 1982-05-11 1982-05-11 Electronic component package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6835182U JPS58170848U (en) 1982-05-11 1982-05-11 Electronic component package

Publications (1)

Publication Number Publication Date
JPS58170848U true JPS58170848U (en) 1983-11-15

Family

ID=30078135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6835182U Pending JPS58170848U (en) 1982-05-11 1982-05-11 Electronic component package

Country Status (1)

Country Link
JP (1) JPS58170848U (en)

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