JPS58169642A - Error correction coding system - Google Patents

Abstract

PURPOSE:To reduce substantially the effect of a transmission error, by providing a digital data having a high degree of importance at the position where the probability is small for incapability of error correction. CONSTITUTION:Respective high-order and low-order 8 bits are supplied through input terminals I0-I5 for continuous two samples among audio PCM signal series. These input signals are delayed by delaying units 1-14, and the error correction code series are delivered. Then data having a high degree of importance is allotted to the channel of a terminal part where the amount of delay is decreased or increased among the channels of plural digital data incorporated in the error correction code series.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction encoding method using cross interleaving.

For example, an audio PCM signal sequence is converted into a predetermined number of numbers (
A redundant code for error correction is added to each word), an interleaving operation is performed to give each of the predetermined number of PCM data and the error correction code a mutual delay, and an error detection code is further added. Recording and playback has not been carried out. As one such interleaving, a predetermined number of PCs in the first arrangement state
A first redundancy code for error correction is added to the M words, and a second redundancy code is added to the predetermined number of PCM words and the first redundancy code in the first arrangement state after the interleaving operation.
Rita suin and taleave which add redundant code have been proposed. Four-switch interleaving improves error correction capability compared to simple interleaving because each word of PCM data is included in two sequences that generate a first redundancy code and a second redundancy code, respectively. Gade kill. The feedback type interleave returns the second redundant code to the first arrangement state so that the sequence that generates the first redundant code also includes the second redundant code, Furthermore, error correction ability is improved.

In this error correction encoding method using four-scan interleap, it has been found that the probability that error correction becomes impossible differs between words with different delay amounts in units of II several words. Therefore.

In this invention, words with higher importance are assigned to words with a lower probability that error correction will become impossible.

As an example, for lIl word digital data, l
Considering the case of feedback type cross-interleaving that adds boond parity, the parity sequence can be expressed as shown in FIG.

In FIG. 7, black circles indicate the code symbols l whamd, and white circles are added to S, ~8. is paying attention to. Further, in FIG. 1, the t word in the vertical direction is a series of parity codes Q on one side, and the word t in the diagonal direction is a series of parity codes P on the other side.

If the transmission system is random and the decoder repeats Q decoding using parity code Q and P decoding using parity code P multiple times, then e
When the parallelogram l-boads containing each of 81 to S are simultaneously erroneous, this error word cannot be corrected. For example, if the l boods of Be * s, e 8@'+ s, ' become error words at the same time, w (8o
Since two words each of T s, ) (8・/ , s :) are included in the Q sequence, they cannot be corrected using parity Q, and e(8e*8゜′) (8t
Since each two words of *8t') are included in the P sequence, they cannot be corrected using parity P.

Therefore, error correction becomes impossible. For each word of 8. to SI, the probability that error correction becomes impossible can be determined by counting the number of parallelograms that include each word.

Assuming that the probability imposed by l word is P8, the probability that error correction becomes impossible for each word between 8° and 8° is as shown below.

Pa =/()P6 Pl =/'iPH'p,
=/ aps4 ps =/ 4Pa4P4 =
/ 4! P, p, = / 6 p8
4 Of course! There are cases where more than one word is simultaneously erroneous and errors cannot be corrected, but the probability of this (P♂ or less) is ignored. Further, the same tendency exists not only in the case of 4I words but also in the case of N word coparity in general.

In the error correction coding method proposed earlier.

As mentioned above, it does not take into consideration that the probability of error correction being impossible varies depending on the data channel.

Therefore, S, , S1 or S, t where this probability is small
In many cases, parity data is assigned to the word position of S. However, PCM data is more important than parity for error correction.

Therefore, in the present invention, highly important digital data is placed in a position where the probability that error correction becomes impossible is small. For example, when audio PCM data of l samples of 16 bits is recorded and played back by dividing it into upper l bits and lower l bits, the data of the upper l bits is the most important. The importance decreases in order. Therefore, the data of the upper l bits are converted to 8° and 8° in FIG. and the data of the lower l bits is 8. and S, and the parity peQ is 8, and 8. It will be done as follows.

An embodiment of this invention will be described below.

This example is for l words of digital data.

This is a feedback type glue-four interleap in which parity codes are added as the seventh and third redundant codes.

FIG. 1 shows the configuration of the encoder in this embodiment, and shows the input terminal structure. The upper 1 bits and the lower 1 bits of each of two consecutive samples of the audio PCM signal sequence are supplied from . W.~W3 indicates a PCM data sequence, and the PCM data sequence W, in which the upper l bit of / sample is l bood, is output through the delay unit 1 of jd (d (block) is the unit delay amount). O
It is retrieved at 0. Further, a PCM data string W in which the lower l bits of l samples are /7-code is d.

The signals are taken out to the output terminal O1 via a delay unit 2t3-4 having a delay amount of Cl, D (D is a unit delay amount). Similarly, J d * (1m (4!D-d)
A delay unit 5.6.7 is inserted between input terminal 11 and output terminal 0 to which a PCM data sequence with the upper l bits as 7 words is supplied, 3d, cod, (tD-cod). Delay amount nits 8, 9, and 10 are inserted.

And check the input end. e If e I. e Data with a delay of J(1) is converted to (m
od, -2) to form the first parity Q. This parity q is taken out to the output terminal 0 via the 3D delay unit 11.

Also, e Oe 6m -2de Jds da (1, jd
PCM data series and parity q given delay amount of
A second parity P is formed from each word of the series. This parity P is a lit unit of tdecoD) 12
．． The signal is taken out to the output terminal 0 through 13, and the delayed signal is fed back to generate parity Q.

When the six words of the sequence that generates the first parity Q are shown in vertically matching positions, as shown by white circles in FIG. 3, the sequence that generates the second parity P (indicated by black circles) is It will be located in the direction. This FIG. 3 corresponds to the above-mentioned FIG. 1.

Furthermore, a total of 6 words of ≠ words of PCM data and 2 words of parity data appearing at the outputs of the delay units 4, 7.10, and 11.13 are supplied to the CRC code generation circuit 14, and a CRC code for error detection is generated. is formed and taken out to the output terminal O6.

In reality, the delay unit is constituted by a RAM, and a predetermined delay is caused by address control of this RAM, starting from output terminal 0.O1*O! ...0. Digital data is generated in series in this order, and this serial data is supplied to the CRC code generation circuit 14. Then, a synchronizing signal and the like are added, and the data is recorded and reproduced by, for example, a rotary head type recorder.

The t word supplied to this CRC code generation circuit 14 is as shown by the broken line with respect to the position where the Q sequence is generated.
0. D, koD, 3D, keD, 3D delayed.

Figure 2 shows the configuration of a decoder corresponding to the encoder shown in Figure 2, in which 6 words of digital data appearing at the output terminal of the encoder are supplied to the input terminals indicated by ~I, and ~I. C'RC from the input terminal indicated by ,
It is supplied together with the code to the CRC checker 15 and error detection is performed.

The result of this error detection is added to every 79th code of the digital data as l-bit error and l-inter as shown by broken lines.

Error correction cancels the delay given by the encoder and converts the 6 words included in the common parity generation sequence into P
This is done by feeding a decoder or a Q decoder. That is, Do 2De jD# (4'D-(1), d
, (j, D-, 2d), delay units 16, 17.1B, 19°2G, 21.2 having respective delay amounts of d.
2 and the 7 words from the input terminal Che are supplied to the Q decoder 23.

Error correction is performed using parity Q. If there is an l word error among these 6 words, the other 3 words excluding the error word indicated by the error pointer (mod
, j) to obtain the correct word.

On the other hand, delay units 16.17.1B, 19°21,
By delay unit 24.25.26.

jaw (I)+ja) e (-2D+ a)
* j De (da Da), (jp-ja) delayed six words are supplied to the P decoder 2T, thereby performing error correction using parity P.

Furthermore.

By way of delay units 28, 29, and 30.

The error-corrected PCM data is output to output terminal 0. .

The PC'M data is taken out to the output terminal O1, and the PC'M data is taken out to the output terminal O1.

FIG. 3 shows another embodiment in which the present invention is applied to a non-feedback type Coos interleap. In the non-feedback type, only the sequence that generates one parity Q includes the other parity P. Even in the case of the non-feedback type, the probability that error correction will not be possible differs depending on the position of the word, just as in the feedback type.
* When assigning parity PtQ to s, Shinzaru 8. .

88 * There is a high probability that error correction will be impossible at the s4 position. In other words, similar to the above, 8. The probability that an error cannot be corrected for each word of ~S is calculated as shown below.

P o = / OP 6 P @ = / □
P B'p, =/jp, P, =/dap, 4P
4=/JPII P@=10PB' As shown in FIG. 3, the input terminal check. PCM data in which the upper l bits of each of the two samples of PCM data constitute l words is supplied to each of the and.

PCM data in which the lower t bits of the PCM data are L words is supplied to the input terminals I@ and I, respectively. This input end check. Parity P is formed from l words of PCM data supplied to e ''1 * 4 t II and by a delay unit.

Parity Q is formed from l words of PCM data delayed by 0, d, Jcl, da d, jd and l words of parity P. Furthermore, due to the delayed style knit.

For input, 0. The l word given a delay of D, koD, 3D, 4ID, and tD is CR (1” code generation circuit 1
4 to form a CRC code.

These cross-interleaved PCM data, parity, and CRC code are taken out to output terminals O.~0.

Further, the decoder corresponding to the encoder shown in FIG. 3 is composed of a CRC checker, a delay unit for canceling the delay given by the encoder, a P decoder and a Q decoder (although not shown in the figure). .

As can be understood from the description of the embodiments above, according to the present invention, each word is selected from among a plurality of digital data channels included in two error correction code generation sequences, the delay amount being small or large. Focusing on the fact that the probability that errors cannot be corrected is small for the end channel where
By allocating PCM data (upper side when splitting into upper side and lower side), the effects of transmission errors can be substantially reduced.

Note that the error correction code is not limited to parity, and other codes such as Reed-Solomon code and adjacent code may be used.

[Brief explanation of the drawing]

FIG. 7 is a route diagram used to explain the error correction of the feedback type Coos interleap, FIG. 1 is a splitter diagram showing the configuration of an encoder in an embodiment of the present invention, and FIG. Figures 1 and 2 are block diagrams showing the configuration of a decoder in an embodiment of the present invention,
FIG. 3 is a block diagram showing the configuration of an encoder in another embodiment of the invention. II e II * I4 e II """ Input terminal, o...0... Output terminal, d, D...
・Unit delay amount. 14...CRC code generation circuit, 15...
...CRC checker #23...Q decoder, 27
...P decoder. Agent Masatomo Sugiura Figure 2 Figure 4 0

Claims (1)

[Claims] Different delay amounts are applied to multiple words of digital data to obtain a first array state, and a first length code for error correction is added to the multiple words in this first array state. Different delay amounts are given to the plurality of words in the 7th arrangement state and the 7th redundant code to obtain a second arrangement state, and an error is detected for the plurality of words in the second arrangement state and the 1st redundant code. In an error correction encoding method characterized by adding a second redundant code for correction,
An error characterized in that digital data of high importance is assigned to a position with a low probability of becoming uncorrectable among a plurality of words included in a common generation sequence of the first or second redundant code. Correction encoding method.