JPS58166117U - signal output circuit - Google Patents
signal output circuitInfo
- Publication number
- JPS58166117U JPS58166117U JP3478483U JP3478483U JPS58166117U JP S58166117 U JPS58166117 U JP S58166117U JP 3478483 U JP3478483 U JP 3478483U JP 3478483 U JP3478483 U JP 3478483U JP S58166117 U JPS58166117 U JP S58166117U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- outputs
- control signal
- response
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案の一実施例による信号出力回路を具備し
た電圧供給装置の回路図で、4:計算機、5 :D/A
変換器、48:FET、 U5. U2.演算増幅器で
ある。
第2A図、2B図、2C図および2B図は第1図に示し
た装置の説明図である。FIG. 1 is a circuit diagram of a voltage supply device equipped with a signal output circuit according to an embodiment of the present invention, in which 4: computer, 5: D/A
Converter, 48: FET, U5. U2. It is an operational amplifier. 2A, 2B, 2C and 2B are explanatory diagrams of the apparatus shown in FIG. 1.
Claims (1)
路と、直列接続された複数の抵抗器を介して前記アナロ
グ信号に接続された第1入力端子、バイアス手段に接続
された第2入力端子、および信号出力端子に接続された
出力端子を有する演算増幅器と、前記第1入力端子と出
力端子との間に接続された抵抗器と、前記複数の抵抗器
のうち少なくとも1つと並列に接続されたスイッチと、
前記レンジ制御信号に応答して第1、第2制御信号を出
力する制御回路とから成り、前記スイッチは前記第1、
第2制御信号に応答して各々一定時間後間、瞬時に開と
なることを特徴とする信号出力回路。 ・a signal source circuit that outputs a range control signal and an analog signal; a first input terminal connected to the analog signal via a plurality of series-connected resistors; a second input terminal connected to bias means; and a signal source circuit that outputs a range control signal and an analog signal. an operational amplifier having an output terminal connected to an output terminal; a resistor connected between the first input terminal and the output terminal; and a switch connected in parallel with at least one of the plurality of resistors. ,
a control circuit that outputs first and second control signals in response to the range control signal, and the switch includes a control circuit that outputs first and second control signals in response to the range control signal;
A signal output circuit characterized in that it opens instantaneously after a predetermined period of time in response to the second control signal.・
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3478483U JPS58166117U (en) | 1983-03-10 | 1983-03-10 | signal output circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3478483U JPS58166117U (en) | 1983-03-10 | 1983-03-10 | signal output circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58166117U true JPS58166117U (en) | 1983-11-05 |
JPS613139Y2 JPS613139Y2 (en) | 1986-01-31 |
Family
ID=30046276
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3478483U Granted JPS58166117U (en) | 1983-03-10 | 1983-03-10 | signal output circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58166117U (en) |
-
1983
- 1983-03-10 JP JP3478483U patent/JPS58166117U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS613139Y2 (en) | 1986-01-31 |
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