JPS6021124U - switch control circuit - Google Patents

switch control circuit

Info

Publication number
JPS6021124U
JPS6021124U JP11287683U JP11287683U JPS6021124U JP S6021124 U JPS6021124 U JP S6021124U JP 11287683 U JP11287683 U JP 11287683U JP 11287683 U JP11287683 U JP 11287683U JP S6021124 U JPS6021124 U JP S6021124U
Authority
JP
Japan
Prior art keywords
buffer amplifier
switch
input terminal
control circuit
switch control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11287683U
Other languages
Japanese (ja)
Inventor
文男 濱田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP11287683U priority Critical patent/JPS6021124U/en
Publication of JPS6021124U publication Critical patent/JPS6021124U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、従来方式によるスイッチ制御回路の一例を示
すブロック図である。第２図は、本考案によるスイッチ
制御回路の一実施例を示すブロック図である。第３図は
、本考案によるスイッチ制御回路の他の一実施例を示す
ブロック図である。 １・・・スイッチ、２，３．４・・・端子、５・・・バ
ッファ増幅器、６・・・抵抗器、７，８・・・ＮＯＴ回
路、９・・・積分器。FIG. 1 is a block diagram showing an example of a conventional switch control circuit. FIG. 2 is a block diagram showing an embodiment of the switch control circuit according to the present invention. FIG. 3 is a block diagram showing another embodiment of the switch control circuit according to the present invention. 1... Switch, 2, 3. 4... Terminal, 5... Buffer amplifier, 6... Resistor, 7, 8... NOT circuit, 9... Integrator.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] スイッチを駆動するためのバッファ増幅器と、入力端子
が前記バッファ増幅器の出力端子に接続されていて出力
信号に遅延時間を与えるための積分回路と、一端が前記
積分回路の出力端子に接続され、他端が前記バッファ増
幅器の入力端子に接続されていて帰還に使用するための
抵抗器とを具、備し、通常時には前記バッファ増幅器の
出力電圧により遅延なくスイッチを制御し、前記バッフ
ァ増幅器の入力端子を開放した場合には前記抵抗器を介
して供給される前記積分回路の出力電圧により前記スイ
ッチを保持して制御するように構成したことを特徴とす
るスイッチ制御回路。a buffer amplifier for driving the switch; an integrating circuit having an input terminal connected to the output terminal of the buffer amplifier and providing a delay time to the output signal; one end connected to the output terminal of the integrating circuit; and a resistor whose end is connected to the input terminal of the buffer amplifier and used for feedback, and normally the switch is controlled without delay by the output voltage of the buffer amplifier, and the input terminal of the buffer amplifier is connected to the input terminal of the buffer amplifier. 2. A switch control circuit characterized in that when the switch is opened, the switch is held and controlled by the output voltage of the integrating circuit supplied via the resistor.
JP11287683U 1983-07-19 1983-07-19 switch control circuit Pending JPS6021124U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11287683U JPS6021124U (en) 1983-07-19 1983-07-19 switch control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11287683U JPS6021124U (en) 1983-07-19 1983-07-19 switch control circuit

Publications (1)

Publication Number Publication Date
JPS6021124U true JPS6021124U (en) 1985-02-14

Family

ID=30261507

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11287683U Pending JPS6021124U (en) 1983-07-19 1983-07-19 switch control circuit

Country Status (1)

Country Link
JP (1) JPS6021124U (en)

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