JPS58164100A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the reliability of semiconductor memories, by installing an impedance element to be used for selecting standby memory cells between a decoder for selecting cells and standby memory cells and switching a faulty memory cell to a standby memory cell by lowering the impedance of the impedance element. CONSTITUTION:When, for example, a trouble occurs in a memory cell to be connected to a driving line W3, the impedance of a high-resistance polysilicone P3 is lowered by laser anneal. Then an output line R3 and a point B1 are connected with each other and a standby memory cell is selected through a driving line D1. Therefore, the reliability of the semiconductor memory is improved with a simple measure.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory capable of switching to a spare memory cell when a regular memory cell is defective.

[Technical background of the invention]

Recently, in semiconductor memory, a regular memory cell circuit and a spare memory cell circuit are formed, and if there is a defective bit in the regular memory cell circuit during manufacturing, this defective pit part is used as a spare memory cell circuit. The number of devices with redundancy functions that can be used in place of cell circuits is increasing. This is because even if a normal memory cell circuit has just one defective cell, the memory as a whole is defective, and such a memory is discarded as a defective product. In other words, as memory capacity increases, the probability of defective memory cells occurring increases, and if memory cells with defects were discarded, the cost of the product would become extremely high. Put it away. Therefore, a method has been adopted in which a spare memory cell circuit is formed in order to achieve an overall yield of 1, and when a part of the regular memory cell circuit is defective, this is switched and used.

FIG. 1 is a block diagram of a semiconductor memory in which the spare memory cell circuit 1 is formed. In the figure, 1 is an address buffer to which an address signal is applied, and the output from this address buffer 1 is applied to a regular address decoder 2 and a spare address decoder 3 in parallel. The decoded output of the regular address decoder 2 is given to the regular memory cell circuit 4, and one row line in the regular memory cell circuit 4 is selected by this decoded output, and then connected to this selected row line. Data is stored in and continues to be retrieved from memory cells.

Further, the r-code operation of the regular address decoder 2 is controlled by the output from the spare address decoder 3. The decoded output of the spare address decoder 3 is given to the spare memory cell circuit 5, a memory cell in the spare memory cell circuit 5 is selected by this decoded output, and data is then stored in the selected memory cell. , the data is read out. .

On the other hand, depending on the configuration of the spare address decoder 3, there may be a defective bit in the regular memory cell circuit 4, and when replacing this defective part with a memory cell in the spare memory cell circuit 5, the memory cell Sterilization can also be performed using an exchange side (company) signal output from the exchange control signal generator 6, in which information for exchange is stored in the nonvolatile memory element in advance. In other words, in a semiconductor memory having such a configuration, if there is no defective bit in the regular memory cell circuit 4, the exchange control signal is not output, and only the regular address decoder 2 operates to detect the defective bit in the regular memory cell circuit 4. A memory cell is accessed. On the other hand, if there is a defective bit in the normal memory inert circuit 4, the spare address decoder 3 is prepared in advance so that the decode output corresponding to the row or column address including the defective bit is sent to the memory address decoder 3.
is programmed, and the exchange control signal generator 6
The non-volatile storage element is programmed so that an exchange control signal of 11 lB or 0 lB is obtained.
Keep 1. Therefore, when the address buffer 1 obtains an output corresponding to the row l or column address containing the defective bit of the normal memory cell circuit 4, the spare address decoder 3 selects the memory cell in the spare memory cell circuit 5. Ru.

Furthermore, the r code operation of the regular address decoder 2 is stopped by the decoded output of the spare address decoder 3 at this time, and the regular memory cell circuit 4 is not accessed. Due to this operation, the regular memory cell circuit 4
The defective part inside is replaced with a spare memory cell circuit 5.

Fig. 2 fa), (bl is the exchange control signal generating section 6
FIG. 2 is a circuit diagram showing a conventional configuration. In the circuit shown in FIG. 2(a), a fuse element F made of polysilicon or the like, which is a type of non-volatile memory element, is inserted between the power supply VD application point and the output terminal Out.
An enhancement mode MOS transistor QE for programming is inserted between the output terminal Out and the ground point, and a depletion mode MOS transistor QE is inserted between the output terminal Out and the ground point.
S) Insert transistor QD and MOS transistor QB
The program signal P is given to the f-to, and the MO
The dirt of the S transistor QD is connected to the ground point. In addition, the circuit shown in Figure 2 (bl) has a two-step connection for programming between the electric wire vD application point and the output terminal Out.
Insert a transistor (MOS) transistor QE in the depletion mode P between the voltage application point and the output terminal Out.
A fuse element F is inserted between the output terminal and the ground point, and a program signal P is applied to the r-to of the MOS transistor QB, and the f- of the MOS transistor QD is applied to the f-
) is connected to the output terminal Our.

In the circuit of Fig. 2(a), when the fuse element F is not blown, the level of the output terminal Out is MOS (MOS).
1 depending on the resistance ratio between transistor QD and fuse element F.
It is kept at 1 lb.

On the other hand, if a program signal P of 11 levels is applied to the date of transistor QB (MOS), then this transistor QB
is turned on, a large current flows through fuse element F, and fuse element F is blown out by the Joule heat generated at this time. When fuse element F is blown, signal P becomes 1 again.
0 level, the transistor QE is cut off, and the output terminal Out becomes "Off" via the transistor QD.
discharged to the level. When the level of the signal at the output terminal Out, that is, the exchange control signal, is, for example, 11 levels, the decoding operation of the spare address decoder 3 is stopped, and the decoding operation is performed at, for example, the IQ level.

In the circuit of Figure 2(b), contrary to the circuit of Figure 2(a), when the fuse element F is not blown, the output terminal O
The level of ut is kept at 0 levels by the resistance ratio of the MOS transistor QD and the fuse element F. Then, when a program signal P of 11 levels is applied to the dart of the transistor Qw, the fuse element F blows out in the same way as above. After that, the output terminal Out is woken up to the "al" level via the transformer QD. In this case, the level of the signal at the output terminal Out, that is, the exchange control signal, is, for example, I
At the QI level, the decoding operation of the spare address decoder 3 is stopped, and the decoding operation is performed at, for example, 11 lvl.

FIG. 3 shows an example of the configuration of one decoding circuit of the spare address decoder 3 when the exchange control signal generating section 6 is not used. This circuit includes a depletion mode transistor QLD for load and the address buffer 1.
Each address signal AOm80m' output from
1 + AI...Multiple enhancement mode transistors QDR for driving with A'' as dart input
and a plurality of fuse elements F'B inserted between the transistor QLD and the transistor QLD.

In such a decoding circuit, one of the memory cells of the regular memory cell circuit 4, for example, address A. =A
If the ＼ corresponding to I=...A n = O is defective, each fuse element FB is programmed to obtain a decoded output corresponding to this address, that is, AO* '1 @...An The fuse element FB connected to the transistor QDR whose dart input is blown out. People for this. =A, =...=A
If n = O, the spare memory cell at that address is the one to be accessed.

[Problems with background technology]

By the way, in the spare address decoder shown in FIG. 3, in the case of a defective address, it was necessary to blow out the program, that is, the fuse element FB, by the number of addresses input in order to select a spare memory cell. . These fuse elements are blown out by Joule heat generated by a laser or the electric current as described above, but this method of fusing reduces reliability due to the amount of fused material on the peripheral circuits, or the fusing itself. It goes without saying that the fewer the fuse element blowouts, the better, as there are failures and reliability problems at the blowout points. However, with recent advances in microfabrication technology for integrated circuits, memory capacity has increased, and the number of address inputs has also increased accordingly. For this reason, the number of wires to be cut when using spare memory cells (
The number of fuse elements has also increased as memory capacity has increased.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and is a semiconductor device that allows a regular memory cell to be replaced with a spare memory cell by simply changing the impedance value of one impedance element, no matter how the memory capacity increases. It attempts to provide memory.

[Summary of the invention]

In order to achieve the object of the invention, an impedance resistor for selecting a spare memory cell is provided between a cell selection decoder and a spare memory cell, and an impedance element selected for selecting a spare memory cell is provided. It lowers the impedance and switches defective memory cells to spare memory cells.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Fourth
In the figure, 11 is the address input person. , Ao.

Output lines R1 to R based on A1 s A1 m...
i is a decoder that selects one of the output lines R1 to Ri
are connected to the input terminals of the buffer circuits Bu1 to Bui.

The output ends of the buffer circuits Bu1 to Bui are connected to the drive lines W1 to W.
i is connected to the memory cell via i. Output line R1~R
i is high resistance polysilicon P.

It is commonly connected to the input terminal of the buffer B"If m B" lff1 via ~PI, and the output line R1~Ri is connected to the buffer B' tt via high resistance polysilicon Q, ~Qi.
*Commonly connected to the input terminal of B”tt. Drive line W1~
Wl is connected to the tt source ■S (ground) via enhancement type MO8 transistors (N channel) T, 1 to T11, and drive lines W1 to Wl are connected to transistors T□ to T
t, to the power supply VS. transistor T
The darts of It to T11 are commonly connected to the output terminals of the buffer circuits Bu, , and the darts of the transistors T11 to Ti are commonly connected to the output terminals of the buffer circuits Bu, .

The output end of the buffer circuit Bu,t is connected to the drive line DI of the spare memory cell, and the output end of the buffer circuit Bu11 is connected to the drive line DI of the spare memory cell. Buffer circuit Bu1. , Butt's input end B1 is the fifth
The buffer circuit B ull @ B'! is connected to the drain end of the depression type transistor 12 shown in the figure. ! The input end B of is connected to the drain end of a transistor formed similarly to transistor 12 of FIG.

In FIG. 4, decoder 1 is an address. , Ao, A1, A, . . . , one of the output lines R8 to R1 is set to 11 levels. This is transmitted to the buffer circuit, and the drive lines W, ~Wi
Rapidly photoelectrically charge one of them to make it 11 rubels. The transistors shown in FIG. , B, the driving line connected to the point, ,
llD, and transistor TZ 1 * T1 t~'
r,t,'rt.

The gate will be kept at 10 lv. For this reason, W, ~w
Memory cells on selected drive lines of i are selectively driven.

Here, it is assumed that there is a defect in the memory cell connected to the drive line W, for example. At this time, high resistance polysilicon P,
is annealed using, for example, a radish method to reduce the impedance (resistance). In this way, the output HRs
and 38 points are connected. Now, when the output line Bs is set to 11 levels by the decoder 7'11, this is transmitted to the B1 point, which becomes 111 (the transistor 12 is connected to this m1 level).
It is set to a high resistance value that does not affect the w level. ), transistors TI2-Ti, are turned on, drive lines W1-Wi become 101, and a spare memory cell is selected via the drive lines W1-Wi. That is, a spare memory cell is selected by laser annealing the high resistance polysilicon P at one location to make it low resistance.

If there is a defective memory cell other than the memory cell connected to the drive line W, high resistance polysilico yQ,
It is sufficient to lower the resistance of one of the corresponding Qi. As described above, although FIG. 4 shows an example with two spare memory cells, this can be implemented in the same way with any number of spare memory cells.

Figure 6 shows B1 or 3 transistors instead of the transistors in Figure 5.
This shows an example in which high-resistance polysilicon 13 is connected to eight points, and when the spare memory cell is not used, the resistance is lowered to keep B or BtA at the v8 level. This transistor 12 and high-resistance polysilicon 13 do not need to be particularly provided. This is because in an integrated circuit, the BIsBt point is always maintained at the m0w level due to leakage current of the PN junction.

FIG. 7 shows the buffer circuit side comprising P-channel type transistors 21-24 and N-channel type transistors 25-28 suitable for the CM08 integrated circuit according to the present invention. Here, transistor T1! ~Ti! Transistors 22.26 to which signal A is input to the dart terminal are used instead of transistors T11 to Tl, and transistors 23.27 are used instead of transistors T11 to Tl. Signals A and B are respectively B as shown in FIG.
This is the output of the inverter to which the IsBf point is input. From here on
In a buffer circuit such as the one shown in FIG. Hail in-phase signals,
A memory cell is selected by the decoder 11.

On the other hand, when a memory cell is defective, if the address where the defective cell is located is input, for example, point B1 becomes Ill and signal A becomes 101. At this time, the transistor 26 is off and the transistor 22 is on, so the drive line W is 10" and no memory cell is selected. On the other hand, since the 81st point is 11", the buffer for the spare memory cell shown in Figure 89 is Due to the circuit, the drive line D! becomes 11@, and the spare memory cell is selected.

The tenth factor is a circuit suitable for the 0M08 circuit that maintains the B1° and B2 points at the ■S level when there are no defective memory cells.

This circuit connects transistors 31-4 to capacitors 41-4.
3. It consists of a high-resistance polysilicon 44 and resistors 45 to 47, and when the illumination is turned on, the 0 point increases by 1 to 1 level.

On the other hand, point ■ has a high resistance polysilicon 44, so the resistance is 10 lB. 0 points become Ill, and "l s
81 points remain at vs level. If there is a defective memory cell, the high resistance polysilicon is reduced in resistance by laser annealing. Therefore, when the illumination is turned on, the ■ point ■ point becomes the VD level, and the 0 point becomes the ■8 level. On the other hand, since the 0 point is at the VD level, the transistor 38 is also turned on. Here, if the resistance ratio of the low-resistance polysilicon 44 and the transistor 38 is set appropriately, the 0 point is 11@
The level will remain the same. Here, 0 points is IQI, so
Transistors 31 and 37 are both turned on, and the 0.0 point is inverted to 1° and 0, respectively. Therefore, transistor 38 is off, 0 point is 111.0 point is WQI
As a result, the transistor 40 is turned off, and when a defective address signal is input to the r gouda 1 node, the voltage at points B1 and B1 becomes 11 levels.

Figures 11 and 12 show other embodiments of means for selecting spare memory cells. In FIG. 11, a transistor 50 is used in place of the high resistance polysilicon shown in FIG. This further includes a high resistance polysilicon 51 and a depletion type transistor 52, and when there is a defective memory cell, by lowering the resistance of the high resistance polysilicon 51, the transistor 5o is turned on and the impedance value of this transistor is changed. This is to connect the output line R8 and point B1.

In FIG. 12, a spare memory cell is selected by, for example, cutting the 0 point with a laser or the like and turning on the transistor 50.

Figures @13 and @14 are examples of buffer circuits using N-channel E/D (enhancement/depression) type integrated circuits. The buffer circuit in FIG. 13 consists of transistors 1 to 66, and transistors 63 and 64 of this circuit.
f-) Signal A of transistor 6'1.6 of FIG.
It is obtained from an inverter circuit consisting of 8. If this buffer circuit is used in the @4 diagram Bus...Bui,
Transistors TI Rm..., T+ are not required.

〔Effect of the invention〕

As explained above, according to the present invention, it is only necessary to lower the impedance of the impedance element provided between the decoder and the spare memory cell. It is possible to provide a semiconductor memory that can be selected and has improved reliability.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a semiconductor memory having a spare memory cell, FIGS. 2 and 3 are partial detailed circuit diagrams of the same WIT configuration, and FIG. 84 is a circuit configuration diagram of an embodiment of the present invention. 5
6 is a circuit diagram of a modified example of the circuit, and FIGS. 7 to 14 are circuit diagrams showing specific examples of the circuit of FIG. 4. 1 No. Decoder, P, ~Pi, Q1~Qi. 50... Impedance element, TI, ~Ti,...
Transistor for cell non-selection.

Claims (1)

[Claims] a memory cell, a decoder for selecting the memory cell, a spare memory cell serving as a spare for the memory cell, and a memory cell provided between the spare memory cell and the decoder to select the spare memory cell by the output of the decoder. 1. A semiconductor memory comprising: an impedance element for selection; and an impedance value of the impedance element selected for selecting a spare memory cell is changed. ′