JPS58175196A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory where a defective memory cell is switched to a stand-by memory cell even if the memory capacity is increased, by disconnecting two wiring layers merely when one memory cell is defective. CONSTITUTION:Memory cells are tested in the state where output lines R1, R2, R3-R6 are connected to driving lines W1, W2, W3-W6 respectively. If a memory cell connected to the driving line W3 is defective, wiring layers are cut at a point (a) of a wiring B and a point (b) of a wiring C by, for example, laser. Output lines R1, R2, R3-R7 are connected to driving lines W1, W2, W4-WR respectively. That is, driving lines W4-W6 after cut points (a) and (b) are so switched that they are selected by different address data successively, and the output line R6 is connected so as to select the stand-by memory cell. Two points are cut merely to switch the defective memory cell to the stnad-by memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory capable of switching to a spare memory cell when a regular memory cell is defective.

[Technical background of the invention]

Recently, in semiconductor memory, a regular memory cell circuit and a spare memory cell circuit are formed, and if there is a defective bit in the regular memory cell circuit during manufacturing, this defective bit part is used as a spare memory cell circuit. The number of devices with redundancy functions that can be used in place of cell circuits is increasing. This is because even if a normal memory cell circuit has a defective cell of only 1 bit, the memory as a whole is defective, and such a memory is discarded as a defective product. In other words, as memory capacity increases, the probability of defective memory cells occurring increases, and if defective memory is discarded, the cost of the product becomes extremely high. Therefore, in order to improve the yield of the entire secondary process, a method has been developed in which a spare memory cell circuit is formed and used as a replacement when a part of the regular memory cell circuit is defective. .

FIG. 1 is a block diagram of a semiconductor memory in which the spare memory cell circuit described above is formed. In the figure, 1 is an address buffer to which an address signal is given, and the output from this address buffer 1 is given in parallel to a regular address decoder 2 and a spare address decoder 3.・The decoded output of the regular address decoder 2 is a regular one. This decode output selects one row line in the regular memory cell circuit 4, and then data is stored in the memory cell connected to the selected row line. data is read.

Further, the decoding operation of the regular address decoder 2 is controlled by the output from the spare address decoder 3. The decoded output of the spare address decoder 3 is given to the spare memory cell circuit 5, a memory cell in the spare memory cell circuit 5 is selected by this decoded output, and data is then stored in the selected memory cell. Depending on the configuration of O from which data is read, there may be a defective focus in the normal memory upper circuit 4, and when replacing this defective part with a memory cell in the spare memory cell circuit 5, the memory cell It is also possible to perform control using an exchange control signal output from an exchange control signal generator 6 in which information for exchange is written in advance in a nonvolatile memory element. In other words, in a semiconductor memory having such a configuration, if there is no defective focus in the regular memory cell circuit 4, the replacement control signal is not output, and only the regular address decoder 2 operates to detect the defective focus in the regular memory cell circuit 4. A memory cell is accessed. on the other hand,
If there is a defective focus in the regular memory circuit 4, the spare address decoder 3 is used in advance so that a decode output corresponding to the row or column address containing the defective pit can be obtained.
is programmed, and the exchange control signal generator 6
The non-volatile memory has been programmed so that both signals from 1 level or 0 level can be obtained, so now address buffer 1 contains the row or column address containing the defective focus of the normal memory cell 84. When an output corresponding to is obtained, a memory cell in the spare memory cell circuit 5 is selected by the spare address decoder 3. Furthermore, a spare address decoder 3 at this time
The decoding operation of the regular address decoder 2 is stopped by the decoding output of the regular address decoder 2, and the regular memory cell circuit 4 is not accessed. Furthermore, by such an operation, the defective part in the regular memory cell circuit wIJ is converted into the spare memory cell circuit BS. It is something that is exchanged.

FIGS. 2(a) and 2(b) show the exchange control signal generating section 6.
FIG. 2 is a circuit diagram showing a conventional configuration. In the circuit shown in FIG. 2(a), a fuse element F made of polysilicon or the like, which is a type of non-volatile memory element, is inserted between the power supply VD application point and the output terminal Out. Insert an enhancement mode MOS (MOS) resistor QB for programming between the ground point and the output terminal Out.
Insert a degreasing mode MOS) Kunster QD between the ground point and the M(,Is) transistor Q,
The program signal P is applied to the gate of MO.
S) The gate of transistor QD is connected to the ground point. In addition, the circuit shown in FIG. 2(b) has an MO8 transistor/transistor QB in enhancement mode for programming inserted between the power supply VL) application point and the output terminal Out, and similarly the power supply VD application point and the output terminal Out. Insert a depression mode MOS) Kunjista QD between the
A fuse element F is inserted between the output terminal and the ground point, and a program signal P is applied to the gate of the MOS transistor QE, and the gate of the MOS transistor QD is connected to the output terminal Out. be.

In the circuit of Fig. 2 (a), when the fuse element F is not blown, the level of the output terminal Out is MOS)
Depending on the resistance ratio between transistor QD and fuse element F,
On the other hand, when a 1 level program signal P is applied to the MOS transistor Q, #-), this transistor turns on and the fuse element F
A large current flows through the fuse element F, and the Joule heat generated at this time melts the fuse element F. When fuse element F is blown, signal P becomes "0" level again, transistor Qz is cut off, and this time transistor QD is cut off.
The output signal Out is discharged to the "0" level through the output terminal. When the level of the queen output signal (Jut signal, Rp, or the exchange control signal) is, for example, 1 level, the decoding operation of the spare address decoder 3 is stopped, and when it is, for example, 0 level, the decoding operation is performed.

@ In the circuit of Figure 2 (b), contrary to the circuit of Figure 2 (a), when the fuse element F is not blown, the output point O
The level of ut is maintained at 0 level by the resistance ratio between the MOS transistor QD and the fuse element F.

Then, when a program signal P of level 1 is applied to the gate of the transistor QFi, the fuse element F is blown out in the same way as above, and then the output Kameko Out is transmitted through the transistor QD to the level of the signal at the terminal Out, that is, the exchange control signal, to the decoder 3. The decoding operation is stopped, and the decoding operation is performed, for example, when the level is 1.

FIG. 3 shows a configuration example of one decoding circuit of the spare address decoder 3 when the exchange control signal generating section 6 is not used. Each address signal output from decoder 1 “o + A(l*
AH*AI... Consisting of a plurality of fuse elements FB inserted between a plurality of enhancement mode transistors QDR and transistors QLJ for driving, which have a gate input of AH*AI.

In such a decoding circuit, five of the memory cells of the regular memory cell circuit 4, for example, address A, =A
, =...An=Q If the corresponding one is defective, program each fuse element FB, that is, Ao -A, so that a decoded output corresponding to this address can be obtained.
The fuse element F connected to the transistor QDR whose gate input is t-... is blown out. Therefore, when 'o = A+ = . . . = An = Q, the spare memory cell is accessed.

[Problems with background technology]

By the way, in the spare address decoder shown in FIG. 3, in order to select a spare memory cell in the case of a defective address, the program is programmed as many times as there are input addresses.
That is, it was necessary to blow out the fuse element FB. These fuse elements are blown out by Joule heat generated by a laser or an electric current as described above, but according to such a blowing method, fused materials adhere to the peripheral circuits. There are problems such as low reliability due to this, failure of the fuse itself, and reliability problems at the fuse element, so it goes without saying that the fewer the fuse elements are blown, the better. However, with recent advances in microfabrication technology for integrated circuits, memory capacity has increased, and the number of address inputs has also increased accordingly. For this reason, the number of wires (the number of fuse elements) that need to be cut when using a spare memory cell has increased as the memory capacity has increased.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and no matter how much the memory capacity increases, if one memory cell is defective, it is simply necessary to cut the wiring layer at two locations. The present invention aims to provide a semiconductor memory that can be switched to a spare memory cell.

[Summary of the invention]

In the present invention, when there is a defective memory cell among the regular memory cells and a spare memory cell is used, some memory cells of the regular memory cells selected by the decoder when the spare memory cells are not used are set to different addresses. , select a spare memory cell, and
This prevents defective memory cells from being selected.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Fourth
11 in the figure is address input 10.薊、a1゜町... Based on the output line kL1. This is a decoder that selects R, . The output line is divided into two branches, one is the enhancement mode (MOS) Fungistar B□, and the other is connected to the memory cell MX via the drive line 1.

. . , and the other is connected to the memory cells M, , Mt, . Degata Line 9~
You can think of birds in the same way.

The output line R- is branched into two; one is connected to the memory cell via the enhancement mode MO8) transistor Bus drive 4+i Ws, and the other is connected to the memory cell via the enhancement mode transistor C@, and the drive line WR. Connected to memory cells. One end of the gate drive lsB of the transistors 81 to B is a plain mode MOS.
It is connected to the power supply VDK via a transistor 21, and connected to the S potential terminal (ground) via a depletion mode MO8 transistor 22. Transistor C1-
One end of the gate drive line C of C@ is connected to the vS potential end via the depletion mode MO8) transistor 23, and the other end is connected to the depletion mode MO8) transistor 2.
The drive line C is connected to the power supply Vl) through the enhancement mode MO8) transistor 25.
The gate of transistor 25 is connected to the potential
i! Connected to J and B. Drive lines W2-W are enhancement mode MO8) transistors D1゜E1-D spring;
connected to the -cVs potential through R6, and the transistor D
The gates of transistors E1 to D6 are connected to wiring B, and transistors E1 to D6 are connected to wiring B.
The gate of E. is connected to the interconnection NjC.

The drive line WR is connected to the VS potential via the transistor D, and the gate of the transistor D is connected to the wiring B.

In the circuit shown in FIG. 4, the wiring B is maintained at approximately the power supply VD (5V) level by appropriately setting the conduction resistance of the depletion type transistors 21 and 22. Therefore, transistors B1 to B- are turned on. - 10,000, the transistor 25 whose gate is the wiring 4IB is turned on, the wiring @C becomes approximately at the vs potential (OV) level, and the transistors C8~
C6 is in an off state. At this time, the wiring 11WR to the spare memory cell connected to the transistor C is brought to the VS potential level by the transistor yD, and the spare memory cell is in a non-selected state. In other words, the output is Ganban, →
Drive 1 width → 〃 roar tp ) Lg → 〃 W1 〃 R6 → 〃 W.

It will be connected to.

In this state, test the memory cells.

Suppose that in this test, for example, a defect is found in a memory cell connected to the drive II W s. At this time, the wiring N& layer is cut by, for example, a laser at point 2 of the wiring B and point @ of the wiring @C. By cutting the point ■ above, the benefit of distribution @B is /
Between point i;/star 21 and point ■, the power supply is at VD level, and -
The potential level between the point (2) and the transistor 220 is vStS due to the discharge by the transistor 22. Therefore, transistors 81-B are turned off. On the other hand, the voltage between the transistor 23 and the point @ of the wiring C remains at ■S potential, but the voltage between the point @ and the transistor 24 is charged by the transistor 24 because the transistor 25 is turned off, and therefore the voltage reaches the "Ct source VD level". Become.

Therefore, transistors C3 to Ce are turned on. That is, in the state where @ is disconnected at the above point, transistors 81 to B1. C, ~C1 are turned on, and output line R1→drive line W.

, R2 → W snow ＃　　　R1→　〃W4 ,, R5 → W.

# Fan, → // Connected to WR. In other words, the drive N below ◎ at the cutting point
W4 to W are sequentially switched to be selected by different address data, and the output line R1 is connected to K5 to select a spare memory cell. On the other hand, in the case of a defective driver In Is W m, both transistors Ds and E are turned on, and the transistor is always kept at the ■S potential, so that it will not be selected by mistake.

Note that as shown in FIG. 4, the high resistance R1 causes the drive lines W1 to W
, when it is selected, lowers it to the V8 potential.
1 level, and if there is a defective memory cell, the transistors D, E, -D, will become 0 level due to high resistance.

E and D are no longer particularly necessary.

As described above, according to this embodiment, it is possible to switch to a spare memory cell by simply disconnecting at two locations, regardless of the number of address inputs.

Although FIG. 4 shows an example in which one line has a spare memory cell area only for WR, FIG. 5 shows an example in which there are two spare memory cell areas to deal with two defective memory cells. In the wJs diagram, two switching circuits in Figure 4 are used, and the added switching circuit corresponds to the original switching circuit, so is it on the corresponding side? rK
The same reference numerals are used, only the subscripts are different, and the explanation of the structure will be omitted.

If the circuit shown in FIG. 5 is considered in the same way as the case of FIG.
is on, transistor C, engineering ~ Cal I C1! ~C
? Since t is off, the output line R,-→ drive w, W sl R→ 〃W1,, R6→ 〃W・ is connected to the drive line WR1, for the spare memory cell.
WR2 is at zero level (VS level) when the transistor )tt@Dll is turned on. It is assumed that the memory cells are tested in this state and a defective memory cell is found in the drive 41 Wa, We. At this time wiring BI
H*C6! First, cut the @ at the point.

If you do it like this Ratio, → W.

Connected to R2→Wl R1→W4 R1→W・Band → WRl. Next, since Queen W cannot be used, point 6 of wiring B@1 @ CII is cut.

As a result, it becomes connected to R1→Wl h −+ Wl R1→ W4, → WRl 几, → WRl, and the lower memory cells are sequentially selected instead of the drive lines W, , W. Become.

By having two spare memory cell areas in the top 5', it can be seen that even if there are two defects in the memory cell area, it can be done by cutting four wires. Another embodiment of the invention suitable for the @MO8 configuration is shown. Here, transistors 21'-24' correspond to transistors 21-24 shown in FIG. 6th
Since the circuit shown in the figure has a complementary MO8 configuration, the current consumption in the steady state is zero. If there are no defective memory cells now, the distribution@B will be at the “L” level and will be inno (-
The output of the transistor 11 becomes '0'' level, and the output of the transistor 22
' is cut off and the distribution 4IB is "1" (power supply Vl)
level). In addition, since the transistor 24' is also off, the wiring C becomes 0'' (VS potential).On the other hand, if there is a defective memory cell, the wirings B and C are cut off midway.If the power is turned on in this state, Since the wiring B is cut off, the drain side of the transistor 22' is 0.
It's Noma\. At this time, the output of the inverter 11)t
1, the transistor 22' is turned on and the drain side of the transistor 22' becomes stable at "0".

On the other hand, at this time, the gate of the transistor 24' is O, so the transistor 24' is turned on, and the transistor 24'
The drain of is charged to the "1" level.

This is because the wiring C is cut in the middle.

Note that the present invention is not limited to the embodiments, and can be applied in many ways. For example, in the embodiment shown in FIG. 4, the gates of the transistors B, . completely VL)
It can be used up to a certain level, and the transmission characteristics are also improved.

〔Effect of the invention〕

As described above, according to the present invention, the number of wires to be cut to select a spare memory cell can be reduced compared to the conventional method, and a semiconductor memory suitable for a highly reliable large-scale memory can be provided.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a semiconductor memory having a spare memory cell, FIGS. 2 and 3 are circuit configuration diagrams of similar examples,
The fifth factor, FIG. 6, is a circuit diagram of another embodiment of the present invention. 11... Decoder, 21-25... Transistor,
B,~H@,C,~C,,D,~DWe"1~E,...
・Transistor, M1*M! ...Memory cell, B, C...wiring. Applicant's agent Patent attorney Takehiko Suzue Figure 5 Figure 6

Claims (1)

[Claims] A memory cell, a decoder that selects this memory cell, a spare memory cell that is a spare for the memory cell, and a defective memory cell among the memory cells, and when the spare memory cell is used, this spare memory cell is used. A first means for switching some of the memory cells selected by the decoder to a different address when not in use, and a second means for inhibiting output of the defective memory cell when the spare memory cell is used.
A semiconductor memory characterized by comprising means.