JPH10112198A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory which can perform simultaneously writing plural data in a fuse writing system selecting a fuse using a main memory cell decoder. SOLUTION: Plural fuse cells are simultaneously written using a main memory cell decoder and an external input signal (I/O input signal) as a means at the time of writing a fuse cell simultaneously. This device is provided with main memory cell decoders 30-33 selecting some one pair of fuse cell, writing voltage load transistors 21, 25 selected by the main memory cell decoder, selecting transistors 22-28 selecting individual fuse using an external input signal 10-In, and fuse cells 11-16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a circuit for writing data to a fuse using a decoder for selecting a main memory cell.

[0002]

2. Description of the Related Art When mass-producing a product in a semiconductor memory device, a certain parameter may deviate from an intended design due to manufacturing variations or the like. A typical example is a defect of a memory cell. In such a case,
A redundant cell is provided in advance, and a defective cell is replaced with a redundant memory cell to repair a defect of the memory cell. Incidentally, as this kind of conventional semiconductor memory device, for example,
Reference is made to the descriptions in JP-A-344398, JP-A-6-111596 and the like. For example, Japanese Patent Laying-Open No. 4-344398 proposes a configuration that simplifies the circuit configuration of a redundant circuit and simplifies the address setting operation of a defective memory cell.

As means for replacing a defective cell with a redundant cell, address information of the defective cell is written in a fuse provided in the semiconductor memory device, and the address information written in the fuse and the input address are written. Are matched with each other, the redundant memory cell is accessed.

In recent years, the capacity of memory cell arrays has been increasing, and the system of redundant memory cells has been increasing. Accordingly, the number of address information of defective cells has increased, and the ratio of fuses for storing the address information to the chip area has also increased.

Therefore, recently, measures have been taken to reduce the chip area by sharing the fuse writing decoder with the main memory cell decoder. Hereinafter, a fuse data writing circuit in a nonvolatile semiconductor memory device (hereinafter, referred to as a “flash memory”) that can be electrically written and erased collectively will be described as an example.

FIG. 9 shows an example of the configuration of a conventional fuse data writing circuit.

Referring to FIG. 9, address signals TAi,
A decoder circuit for inputting and decoding BAi to select word lines WL0 and WL1, a word line WL0 and WL1 as gate inputs, a source connected to a fuse write voltage terminal VPPW, and a fuse cell 11 on the drain side. , 12 connected to one end FI0, FI1
Type enhancement transistors 21 and 22 and fuse circuits 11 and 12 for outputting output signals FO0 and FO1
And is provided. This decoder circuit includes, for example, address input signals TA0, TA1,.
, BA1,... BAi as inputs,
33 and an inverter 3 for inverting the outputs of the NAND circuits 32 and 33 and outputting the inverted outputs to the gates of the N-type transistors 21 and 22
0 and 31. This fuse circuit (FU
SE0, FUSE1) 11 and 12 use circuits as shown in FIG.

FIG. 10 shows the FUSE circuit 1 shown in FIG.
FIG. 3 is a diagram illustrating an example of a circuit configuration of Nos. 1 and 12. Referring to FIG. 10, a P-type enhancement MOS transistor 1 having a source connected to a power supply and a gate connected to a ground level is provided.
01, an N-type depletion MOS transistor 102 having a drain connected to the drain of the P-type enhancement MOS transistor 101, a gate connected to the ground level, and a source connected to the electrode FO, and a drain (or source) connected to the electrode FO. Then, the source (or drain), which is the other terminal, is connected to the electrode FI, the N-type enhancement MOS transistor 104 whose gate is connected to the terminal FW, the drain is connected to the electrode FO, and the gate is connected to the electrode VP. , And a flash memory cell 103 whose source is connected to the ground level.

Next, the operation of the conventional circuit shown in FIGS. 9 and 10 will be described with reference to a time chart of FIG.
A data writing method will be described.

First, a word line WL0 is selected using an address signal ai (corresponding to TAi and BAi in FIG. 9) for selecting a fuse cell to which data is to be written. At this time, a high voltage is output at the word line level, and the inverters 30 and 31 in FIG. 9 use a level shifter to output a high voltage.

Referring to FIG. 12, first, word line WL0
(In FIG. 9, the transistor 21 is turned on).

Next, a high write voltage is applied to a fuse common power supply VPPW supplied with a voltage from an external power supply. As the high voltage for writing, a voltage of about 6 V is usually applied.

Then, the electrode FI0 (N-type transistor 2)
(1 source potential), a high voltage for writing is output. At this time, as shown in FIG. 12, since a high voltage is applied to the terminal FW (see FIG. 10), the N-type transistor 104 is turned on, and the terminal FO (see FIG. 10)
Also, a high voltage for writing is applied.

Since a high voltage is applied to the terminal FI0 (FI in FIG. 10), the N-type depression M
The gate level of the OS transistor 102 automatically falls below the threshold, and the current path in the power supply direction is cut off.

On the other hand, while data is being written to the fuse cell, a high voltage is output to the electrode VP in FIG. As this VP, a voltage of about 12 V is normally applied. At this time, the flash memory cell 103, which is a fuse cell, enters the same write mode as a normal memory cell, and hot electrons generated below the gate jump into the floating gate to raise the threshold value of the flash memory 103.

With the above processing operation, the fuse circuit FUSE
Data is written to 0 (11 in FIG. 1).

The next fuse circuit FUSE1 (1 in FIG. 9)
When writing data to 2), the address signal ai is changed so that the word line WL1 is selected, and thereafter, the above procedure is repeated as if data was written to the fuse circuit FUSE0.

On the other hand, for reading the fuse data, a voltage is applied to the drain of the flash memory cell 103 by the P-type enhancement MOS transistor 101 which is a load transistor. At this time, the terminal FW is at the “L” level, the N-type transistor 104 is turned off, and is separated from the terminal FI. When the flash memory cell 103 is a written fuse cell, the flash memory cell 103 is not turned on and the terminal FO is set to “H”.
The level is output. On the other hand, if data has not been written, the flash memory cell 103 is turned on, and the “L” level is output to the terminal FO.

FIG. 11 is a diagram showing a configuration of a fuse circuit when a polysilicon (polycrystalline silicon) type fuse is used. Referring to FIG. 11, a resistor 105 connected between the power supply and the terminal FO, a resistor 106 connected between the terminal FO and the ground voltage power supply, and a drain (or source) connected to the electrode FO; An N-type enhancement 107 in which the source (or drain) as the other terminal is connected to the electrode FI and the gate is connected to the terminal FW.

The writing method of the fuse circuit shown in FIG. 11 is basically exactly the same as the above-described voltage application method. However, in the fuse circuit shown in FIG. 11, when a high voltage is applied to the terminal FO, the resistance 10
6, and the data is written. Here, the resistor 105 has a larger resistance value than the resistor 106. When a high voltage is applied to the terminal FO, a large current flows through the resistor 106, and the resistor 106 is blown.

In the fuse circuit shown in FIG. 11, when data is not written (the resistance 10
6 is not blown), an "L" level is output to the FO terminal. On the other hand, if data is written (if the resistor 106 is blown), an "H" level is output to the FO terminal. Is output. As the polysilicon fuse circuit, for example, the description in Japanese Patent Application Laid-Open No. 58-175859 is referred to.

As described above, when data is written to a fuse cell by the conventional method, writing is performed one fuse at a time using the decoder of the main memory cell.

[0023]

However, the above-described method of writing fuse data according to the related art has the following problems.

(1) The first problem is that in the fuse data writing method in which a fuse is selected using a conventional main memory cell decoder, only one bit of data is written. This means that the time required to write the data becomes enormous.

The reason is that, in the above-mentioned prior art, as a means for selecting a fuse cell, it is selected only by the output of the main memory cell decoder.
It depends on the fuse.

(2) The second problem is that in the fuse data writing method in which a fuse is selected using a conventional main memory cell decoder, a corresponding external address exists for each bit of data to be written. That is to do. For this reason, it is necessary to provide this address data to the selection program, and there is a problem that the program size becomes long, enormous, and complicated as the number of fuses increases.

The reason is that, in the same manner as the first problem described above, in the above-described prior art, the fuse cell is selected only by the output of the main memory cell decoder as a means for selecting a fuse cell. This is due to the fact that it corresponds to one fuse.

(3) The third problem is that in the conventional fuse data writing method in which a fuse is selected using a main memory cell decoder, only one bit of data is written. For this reason, when writing adjacent data such as word redundancy, if a plurality of data (address data of word redundancy) can be inputted, two addresses can be written at the same time only by passing through an arithmetic circuit. This means that this is not possible due to the configuration.

The reason is that, in the above-mentioned prior art, a fuse cell is selected only by the output of the main memory cell decoder, so that a plurality of simultaneous writing cannot be performed.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to write a plurality of fuse data by designating only one address.
An object of the present invention is to provide a semiconductor memory device provided with a circuit for shortening the time for writing fuse data.

Another object of the present invention is to simultaneously write two or more sets of another set of write data obtained by calculating one set of data by writing a plurality of sets of data at the same time. It is an object of the present invention to provide a semiconductor memory device that can increase the speed and improve the productivity.

[0032]

In order to achieve the above object, a semiconductor memory device of the present invention has a circuit controlled by information held by a fuse, and the fuse is decoded by a decode signal of a main memory. A first switch that is activated by a decode signal of the main memory and outputs a fuse write voltage; and a fuse input voltage that is output from the first switch and that is commonly input to the semiconductor memory device that writes the information. A plurality of external input signals input to respective control terminals, a second switch group including a plurality of switches, and a plurality of write signals output from the second switch group connected to the respective write terminals. And a fuse group consisting of the above fuses.

The outline of the present invention will be described below. According to the present invention, as means for simultaneously writing the fuse cells, a plurality of fuse cells are simultaneously written using a main memory cell decoder and an external input signal. More specifically, in the present invention, preferably, a main memory cell decoder (consisting of gates 30 to 33 in FIG. 1) for selecting a certain set of fuse cells, and a write voltage selected by the main memory cell decoder Load transistors (21 and 25 in FIG. 1), selector transistors (22 to 28 in FIG. 1) for selecting individual fuses using external input signals (I0 to In in FIG. 1), and fuse cells (11 to 25 in FIG. 1). To 16).

According to the present invention, a plurality of fuse cells can be selected and written simultaneously by an address signal and an external input signal (I / O input signal).

As a result, for example, redundancy (redundancy) address data, which is a set of data, can be input from an I / O pin (or input pin) and written at a time.

Since word redundancy data is input with adjacent address data, by incorporating an address increment circuit in the write circuit, two sets of information can be written simultaneously only by inputting one set of plural data. This makes it possible to write data efficiently.

[0037]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a diagram schematically showing the principle of a fuse data writing method according to one embodiment of the present invention.

Referring to FIG. 1, in this embodiment, a main memory cell decoder (inverter 3) for inputting an external address signal and selecting a word line of a main memory is provided.
0, 31, NAND circuits 32, 33) and external input signals I0-In, and when writing fuse data, high voltage signals S0-Sn according to the external input signal.
, Write voltage load transistors 21 and 25 selected by the main memory cell decoder, and select transistors 22 and 2 for selecting individual fuses using high voltage signals S0 to Sn.
8 and fuse cells 11 to 16.

In FIG. 1, the fuse circuits 11 to 16 shown in the block diagram can have the same configuration as the circuit configuration illustrated in FIG. 10 or FIG. Please refer to FIG.

Referring to FIG. 1, FI terminals FI0 to FIn of a plurality of fuse circuits 11 to 13 are connected to the sources of transistors 21 through transistors 22, 23 and 24, respectively, acting as transfer gates.
FI terminals Fin + 1 of a plurality of fuse circuits 14 to 16
To FI2n + 1 are transistors 2 each acting as a transfer gate on the source of transistor 25.
They are connected via 2, 26 and 27.

FIG. 2 is a time chart for explaining the operation when data is written in the fuse cell shown in FIG. The operation of this embodiment will be described below with reference to FIGS. The basic write operation is the same as the above-described conventional technique. First, a word line WL0 is selected using an address signal ai to select a fuse cell to which data is to be written. At this time, the main memory decoder is configured to output a high voltage to the level of the word line WL0, and outputs a high voltage by using a level shifter for the inverters 30 and 31 in FIG.

In FIG. 2, first, the word line WL0 is selected. At the same time, the signals input by the external input signals I0 to I) are set to a high voltage level according to the input data via the buffers 41 to 43 and output as signals S0 to Sn.

Next, a high write voltage is applied to the fuse common power supply VPPW supplied from the external power supply. Then, the voltage of the VPPW terminal is applied to the drains of select transistors 22 to 24 for selecting a fuse cell through the transistor 21 selected by the word line WL0.

At this time, the on / off of the transistors 22, 23 and 24 is controlled by the output signals S0 to Sn of the buffers 41 to 43, and the electrodes FIi (i is 0
), A high voltage for writing is output.

Then, data is written in the fuse cell (see FIG. 10 or 11) in which the write high voltage is applied to the electrode FI in the same manner as in the above-described procedure of the prior art.

When writing to the fuse cell is completed, FIG.
As shown in FIG. 2, the power supply VPPW is set to the LOW level, and the next address ai and the external input signal I
Signals are input to 0 to In (indicated by signal In in FIG. 2). The next word line to be selected is WL1, whereby a high write voltage is selectively output to any of the terminals FIn + 1 to FI2n + 1 by the external input signals I0 to In.

In this embodiment, by the above operation,
It is possible to select a plurality of fuse cells and write data at the same time.

Embodiments of the present invention will be described below with reference to the drawings in order to explain the above embodiments in more detail.

FIG. 3 is a diagram showing an example of a circuit configuration of a fuse data writing system according to one embodiment of the present invention.

Referring to FIG. 3, in the present embodiment,
A main memory cell decoder (inverters 30 to 31, NAND circuit 3) that receives external address signals TA1 to TAi and BA1 to BAi and selects a word line of the main memory.
2 to 33) and external input signals I0 to I7, and a buffer 4 for generating high voltage signals S0 to S7 according to the values of external input signals T0 to T7 when writing fuse data.
1 to 43; write voltage load transistors 21 and 25 selected by the main memory cell decoder; select transistors 22 to 28 for selecting individual fuses using high voltage signals S0 to S7;
To 16 are provided. Here, regarding the fuse circuits 11 to 16 shown in the block diagram, FIG.
Alternatively, the configuration is the same as the configuration of the related art shown in FIG.

FIG. 4 is a time chart when data is written to a fuse cell in the circuit shown in FIG. With reference to FIGS. 3 and 4, the operation of writing fuse data according to the present embodiment will be described below. Note that the basic write operation is the same as in the above-described conventional technology.
The word line WL0 is selected using the address signal ADD in order to select a fuse cell into which data is to be written. At this time, the configuration is such that a high voltage (about 12 V) is output to the word line WL0 level.
A level shifter is used for 0 and 31 to output a high voltage.

In FIG. 4, first, the word line WL0 is selected. At the same time, the signals input as the external input signals I0 to I7 are set to a high voltage level (about 12 V) according to the data via the buffers 41 to 43 and output as signals S0 to S7.

Next, the high voltage for writing (about 6) is applied to the common power supply for fuse VPPW supplied from the external power supply.
V). Then, VPPW is applied to the drains of select transistors 22 to 24 for selecting a fuse cell through transistor 21 selected by word line WL0.
The terminal voltage is applied. At this time, a high voltage for writing is selectively output to the electrodes FI0 to FI7 by the signals S0 to S7.

The fuse cell applied to the electrode FIx is
Data is written in the same manner as in the above-described related art.

When writing to the fuse cell is completed, FIG.
As shown in (5), the power supply VPPW is set to the LOW level, and the next address ADD and external input signals I0 to I7, which are write data, are input. The next selected word line is WL
The high voltage for writing is selectively output to one of the terminals FI8 to F15 by the external input signals I0 to I7.

With the above operation, it is possible to select a plurality of fuse cells and write data simultaneously.

Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a diagram for explaining the configuration principle of another embodiment of the present invention, and is a diagram showing a concept of a fuse data writing method.

Referring to FIG. 5, in this embodiment, a main memory cell decoder (inverter 3) for inputting an external address signal and selecting a word line of a main memory is provided.
0 to 31, NAND circuits 32 to 33, and an external input signal D
ATA (I0-In) is input and the result of the operation is converted to signal II.
The data conversion circuit 3 outputs the data as 0 to II7, and the external input signals DATA (I0 to In) and the output signals II0 to II7 of the data conversion circuit 3, respectively.
Buffers 41 to 46 for generating high voltage signals S0 to S15 according to I7, write voltage load transistor 21 selected by the main memory cell decoder, and individual fuses using high voltage signals S0 to S15 Select transistors 22 to 27 and fuse cell 1
1 to 16 are provided. Here, as the fuse circuit shown in the block diagram, the circuit shown in FIG. 10 or FIG. 11 is used.

As a specific example of this embodiment, the data conversion circuit 3 has a circuit configuration as shown in FIG. 6 or FIG.

Referring to FIG. 6, this data conversion circuit 3
Includes an AND logic gate 61 _{0-61 6} for receiving the external input signal DATA (I0 to I7), the exclusive OR logic (Exclusive OR) gate 62 _{1-62 7} configuration binary adder of (I0 And outputs operation result signals II0 to II7.

Referring to FIG. 7, the data conversion circuit 3 receives an external input signal DATA (I0 to I7) and outputs an exclusive OR gate 71 for outputting signals B0 to B7.
_{1-71 7} and binary code conversion circuit constituted by, the AND logic gate 72 _1-72 for inputting a signal B0~B6
₆ , a binary adder (considering I0 as a lower bit) constituted by exclusive OR logic gates 73 _{1 to} 73 ₇ for outputting signals b0 to b7, and signals II0 to II7 Exclusive OR gate 74 for outputting II7
A Gray code conversion circuit constituted by _{72d 7,} and a.

Next, the operation of the arithmetic circuit shown in FIG. 5 will be described with reference to the time chart of FIG. The basic write operation is the same as in the above-described embodiment. First, a word line WL0 is selected by using an address signal ai to write data and select a fuse cell. At this time, a high voltage is output to the word line WL0 level, and the inverters 30 and 31 in FIG. 5 use a level shifter to output a high voltage.

In FIG. 8, first, the word line WL0 is selected. At the same time, the signals input by the external input signals DATA (I0 to I7) are input to the data conversion circuit 3, and the data conversion circuit 3 outputs the signals II0 to II7 (I
In) is output.

Output signals II0 to II7 are determined by calculating external input signals DATA (I0 to I7). For example, the external input signal DATA (I0 to I
7) When the first word redundancy address is input, the second word redundancy address is:
A value (adjacent address) obtained by adding "1" to the first word redundancy address is required.

As the data conversion circuit 3, the first word redundancy address and the second word redundancy address are obtained by using the binary adder shown in FIG. 6 (I0 is regarded as a lower bit). be able to. In Figure 6, one end of the AND gates 61 ₁ and an exclusive OR gate 62 ₁ is fixed to the power supply voltage (H level), and outputs a "1" is added to the result to an external input signal DATA.

A first word redundancy address which is an external input signal DATA (I0 to I7) and a second word which is an operation result signal (II0 to II7) of the data conversion circuit 3
Can be written at the same time. The operation of writing the fuse data thereafter is the same as the method described in the above-described related art, and the description thereof is omitted.

When the word lines of the main memory cells are arranged in the order of the gray code, the data conversion circuit 3
As a result, a first word redundancy address and a second word redundancy address can be obtained using a circuit as shown in FIG.

First, the external input signal DATA (I0) which is the first word redundancy address (gray code)
The ～I7), input to the binary code conversion circuit constituted by an exclusive OR logic gate 71 _{1-71 7,} and outputs a binary code signal B0-B7. Then, enter the binary code signal B0~B7 the AND logic gate 72 _{1-72 6} and the exclusive OR gate 73 _{1-73 7} configuration binary adder (which the I0 regarded as lower bits),
The value (adjacent address) obtained by adding “1” to the first word redundancy address (binary) is represented by a signal b0.
To b7.

Next, the signals b0 to b7 are again converted to a gray code through a gray code conversion circuit composed of exclusive OR gates 74 ₁ to 747, and the signals II 0 to II ₇ are output.
7 (Gray code) is output.

The reason why the word lines of the main memory cells are arranged in the order of the gray code will be supplemented below.

When word redundancy is used in the flash memory, two adjacent words of the replaced main memory may be simultaneously selected (for example, initial writing before erasure). At this time, if the word lines are arranged in Gray code order, it is easy to select two adjacent words at the same time.

By the above operation, the data conversion circuit as described above can be used by writing data to a plurality of fuse cells at the same time, and the operation of writing data to the fuse cells is simplified.

[0074]

As described above, according to the present invention,
The following effects are obtained.

(1) A first effect of the present invention is that a plurality of fuse cells can be selected and written simultaneously by an address signal and an external input signal. Thus, according to the present invention, for example, the redundancy address data that is a set of
Input from the O pin (or input pin) allows writing at one time.

(2) The second effect of the present invention is that, since a plurality of data are written at the same time, when inputting adjacent address data such as word redundancy address data, the input data is converted. Two sets of information (address data of the first word redundancy and address data of the second word redundancy) can be written at the same time, and data can be written efficiently. Thus, according to the present invention, the fuse writing step can be shortened, and the productivity can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a configuration principle of an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the embodiment of the present invention.

FIG. 3 is a diagram for explaining a configuration of an embodiment of the present invention.

FIG. 4 is a time chart for explaining the operation of one embodiment of the present invention.

FIG. 5 is a diagram for explaining a configuration principle of another embodiment of the present invention.

FIG. 6 is a diagram showing one example of a data conversion circuit according to another embodiment of the present invention.

FIG. 7 is a diagram showing another example of the data conversion circuit according to another embodiment of the present invention.

FIG. 8 is a time chart for explaining the operation of the embodiment of the present invention.

FIG. 9 is a diagram for explaining a fuse cell writing method of a conventional semiconductor memory device.

FIG. 10 is a diagram showing an example of a configuration of a fuse cell using a flash memory.

FIG. 11 is a diagram showing an example of a configuration of a fuse cell using a polysilicon resistor.

FIG. 12 is a time chart for explaining the operation of the conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st fuse circuit group 2 2nd fuse circuit group 3 Data conversion circuit 11-16 Fuse cell circuit block 21-28 N-type enhancement transistor 30, 31 Inverter logic circuit (level shifter) 32, 33 NAND logic circuit 41-46 Buffer (level shifter) 61 AND gate 62 Exclusive OR logic circuit 71 Exclusive OR logic circuit 72 AND gate 73 Exclusive OR logic circuit 74 Exclusive OR logic circuit 101 P-type enhancement transistor. 102 N-type depletion transistor. 103 flash memory cell 104 N-type enhancement transistor. 105 Resistance (high resistance value) 106 Resistance (low resistance value) 107 N-type enhancement transistor. VPPW Fuse write voltage terminal In External input signal FI0-FIn First fuse input terminal FIN + 1 to F12n + 1 Second fuse input terminal VP Fuse gate terminal FW Fuse write switch

Claims (10)

[Claims] 1. A semiconductor memory device having a circuit controlled by information held by a fuse, wherein the fuse is decoded by a decode signal of a main memory and writes the information, wherein the fuse is decoded by a decode signal of the main memory. A first switch that is activated to output a fuse write voltage; and a common input of the fuse write voltage output from the first switch, and a plurality of external input signals for performing a plurality of decodings. A second switch group consisting of a plurality of switches input to the control terminal; and a fuse group consisting of a plurality of fuses connecting write signals output from the second switch group to respective write terminals. A semiconductor memory device characterized by the above-mentioned. 2. The first switch comprises a MOS transistor which inputs the decode signal to a gate and outputs the fuse write voltage to a drain, and the second switch applies the external input signal to a gate. And a MOS transistor having one signal terminal connected to the drain of the MOS transistor of the first switch and the other signal terminal connected to the write terminal of the fuse. Item 2. The semiconductor memory device according to item 1. 3. A semiconductor memory device having a circuit controlled by information held by a fuse, wherein the fuse is decoded by a decode signal of a main memory and writes the information, wherein the fuse is decoded by a decode signal of the main memory. A switch that is activated to output a fuse write voltage; and outputs an external input signal and / or a predetermined calculation result of the external input signal between an output of the first switch and write terminals of a plurality of fuse circuits. A semiconductor memory device comprising a plurality of switches, each of which is controlled to be turned on / off, by inserting the switches. 4. The semiconductor memory device according to claim 1, wherein said fuse comprises an electrically erasable nonvolatile memory cell. 5. The semiconductor memory device according to claim 1, wherein said fuse is made of polycrystalline silicon. 6. A semiconductor memory device having a circuit controlled by information held by a fuse, wherein the fuse is decoded by a decode signal of a main memory and writes the information, wherein the fuse is decoded by a decode signal of the main memory. A first switch that is activated and outputs a fuse write voltage; and a common input of the fuse write voltage output from the first switch, and controls a plurality of external input signals to perform a plurality of decodings. A second switch group including a plurality of switches input to a terminal, a data conversion circuit that receives the plurality of external input signals and outputs a calculation result obtained by performing a predetermined calculation as a first signal group; The first signal group for commonly inputting the fuse write voltage output from the first switch and performing a plurality of decodings A third switch group composed of a plurality of switches for inputting the control signals to respective control terminals; and a fuse having write signals output from the second switch group and the third switch group connected to the write terminal of the fuse. And a group. 7. The first switch comprises a MOS transistor that inputs the decode signal to a gate and outputs the fuse write voltage to a drain, and the second switch inputs the external input signal to a gate. 7. The semiconductor device according to claim 6, further comprising a MOS transistor having one signal terminal connected to the drain of the MOS transistor of the first switch and the other signal terminal outputting the fuse write voltage. Semiconductor storage device. 8. The semiconductor memory device according to claim 6, wherein said fuse comprises an electrically erasable nonvolatile memory cell. 9. The semiconductor memory device according to claim 6, wherein said fuse is made of polycrystalline silicon. 10. The plurality of external input signals are a first address signal group that is replacement address information for word redundancy, and the data conversion circuit indicates one next to the replacement address for word redundancy. 7. The circuit according to claim 6, wherein the circuit is configured to output a second address signal group.
13. The semiconductor memory device according to claim 1.