JPS5816324A - Bus controlling system - Google Patents

Abstract

PURPOSE:To realize highly flexible bus control, by allotting plural priorities to each master card which is set in parallel to a common bus and controlled by a bus controlling card. CONSTITUTION:A bus controlling card BUC, (n) units of master cards MAC and a slave card SLC are connected in parallel to a common bus CB. The card MAC is controlled by the card BUC. Plural priorities of two kinds, for example, are allotted to each card MAC. In an emergency, a bus using request of a higher priority is delivered. While the bus using request of a lower priority is delivered in a normal state. In such a way, highly flexible bus control is possible.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a multi-master system in which a plurality of master cards are configured to access slave cards connected to the common path through a common path between the plurality of master cards. This invention relates to a priority control method for the right to use a common path.

In this case, the master card refers to a card that can acquire the right to use the common pass, and the O-slave card, which is a card that can access one slave card,
Cards that are accessed according to the instructions of the master card, such as memory cards, input cards, output cards, etc. With the advancement of technology and the multifunctionality of microphone and processor application systems, A large number of Master Card songs that share a common pass are now required, ranging from a few cards to several cards.
In such a multi-mask common path use priority control method (abbreviated as path control method) in which a large number of master cards share a common bus, the path use requests generated within each master card are subject to data processing time and Since there are various types of transfers, from those that require urgency to those that may be delayed, depending on the transfer time interval and the like, it is desirable to be able to assign a plurality of path usage priorities to each master card.

Fig. 1 is a block diagram showing the system configuration of such a multi-master system, Fig. 112 is a block diagram showing the relationship between the path control card and the master card in Fig. In the circuit diagram showing the internal sardine path, the 4th m is a time chart for performing the control operation e*.

The conventional multi-mask type path control system is based on a common path CB. OUC, etc. are connected in parallel with each other. Here, memory card MBC
and the output card is the slave card SLC. The common lotus CB is a path use priority control line P1 address line data line ID5 information transfer control line T and common lock line CL
It consists of K. The path use priority control IIP is 1, and the path use request signal is configured as shown in FIG.
P S G o ” P 8 Q is and BB8
YIIG1 signal line and 1 are used to mean the signal carried on that signal line, so they are distinguished by writing 1 or less as signal line or signal.

! Star Card MAC is Master Card MA in Figure 2.
As illustrated, the path request circuit 1g
BB, the path request circuit section BiL includes a flip 70 block FFxtFFg, an inverter I NIOs'
Nue I N12 (Open collector type inverter) Consists of S-and-channel AN1oeAN11. In addition, the path control card BUC has an inverter ■N21. lN22, AND circuit A
It is composed of N21 and a NAND circuit NA.

Here, for example, Master Card MA c in FIG.

When a request to use the common bus RB is issued in , the 7rip 7a block FF is sent via the AND circuit ANto.

is set, its output is inverted by inverter IN11, and path use request signal BRQO is output onto common bus CB (hereinafter treated as negative logic).

In the path control card BUC, the priority control circuit of the 3111th) gives the signal BRQo the highest priority (hereinafter, BRQl, BR(
h...BRQ), so the signal BRQ.

is inverted by inverter ■N21G and becomes NAND circuit NAG
is led to one terminal of the The other side of the NAND circuit NAG receives the path in use signal BB8Y from the inverter IN! 1゜lN2
However, if it is not in use, it is at a high level, so the output of the NAND circuit NA becomes a high level, and the path use permission signal PSGo is applied to the path master card MACo that issued the request. Permission to use this pass No. 11 P8G.

is inverted by the inverter lN5o in Fig. 2 and becomes 7 rip 7.
While resetting W knob FF1, flip 70 knob F
Fg is set to output the path use OK signal BOK, and the in-use signal BB8Y is output via the 1 inverter IN to block the use of the path CB by other master cards, and the master card MAco that has acquired the right to use the pass Start using. When the use of the path ends after a predetermined period of time, the path use end signal BOV is output, the 7rip 7rip rF2 is reset, the path use OK@'lj is dropped, and the path in use signal BB8Y is set to high level, allowing other masters to The above operation is expressed as (A) in 1st 411, but 1For example, when the path in use signal BB8Y of (4) is off (Heilepel), 1 pass is enabled. When the use request signals BRQ and BRQ2 are issued at the same time, only the signal BRQ1 is accepted because the first signal BRQ1 has a higher priority, as is clear from the circuit diagram of the third WJ. IN22 (IN2go) blocks the AND gate AN2. belonging to the signal BRQ2 (so that only the signal P8G1 is valid) and sends the bus busy signal BBSY to the common bus. Similarly, at the time (c), the only bus use request signal is the signal BRQ2, so the master card is given permission to use the bus by the signal P8Gz from the bus control card BUC. At the time of (d), the priority judgment has already been made and the signal BR is
Since the use permission signal P80g is given by Q2, even if there is a request signal -tBRQ1 with a higher priority than the next request signal CL, it will not be accepted and will be sent to the next delivery destination. This shows the case where priority is given to use. Note that (E) is a case where only the request signal BRQI is issued and there is no other competing signal.

In this way, in the conventional control method, bus usage is controlled based on one fixed priority. Master cards with a lower priority are used only when there is no request from a master card with a higher priority. There was an inconvenience in not being able to obtain permission.

The present invention has been made in view of the above, and it is an object of the present invention to provide a more flexible bus control method.

According to the present invention, a plurality of priorities are assigned to each ordinary master card on a common path, and a bus use request can be issued from the master card based on the assigned plurality of priorities. It is achieved by

For the following reasons, embodiments of the present invention will be described with reference to the drawings. Figures 5WJ and 116 are both circuit diagrams showing embodiments of the present invention, and 1st sg shows the internal circuit of the master card. Each shows the internal shadow path of the path control card.

The internal circuit of the master card according to the present invention is) No. 51! !
As is clear from the above, a setting board S H2r8E3, a flip 70 knob and its peripheral circuits are added to the conventional example shown in Fig. 2 so that, for example, two priorities can be assigned. This is what I did. Similarly, as is clear from Figure 1jI6, the internal circuit of the path control card is such that an OR circuit OR is added to the conventional example of 3g, and its input terminals TPAO to TPA15 and TPBO to TP
BIIS and output terminal TR1- of AND circuit AN41
The TR 31 can be appropriately connected to the TR 31 by wiring. In other words, if two priorities can be set for each master card using 6°SB3 on the setting device side, generally there will be twice as many bus use request signals 11BRQ- and path use requests as there are master cards. Although permission signals 111P8G~ are required, in the present invention, the above-mentioned bus use permission signal! In order to reduce Ill, path use request signals with two priorities are logically combined using an OR circuit, and a setter SE1 such as jI5H is provided in the master card, in other words, one priority is assigned. In response to the bus use request signal B-RQo-BRQst, each master card sends a path use permission signal P S Go
-P S Gu. For example, to assign a priority of Ill□# and 131" to a master card consisting of 1, use the setting device S E 1 e S E
Connect the No. 0 child of No. 2 and the No. 31 terminal of the setting ll5Hs like the i line, and connect the terminals TRo and T P of Fig. 6.
A□s Also, connect terminals TR and TPBo as shown by dotted lines.

By doing this, two priorities are assigned to the master card, and in case of a bird emergency, it issues a bus use request RE1 with a higher priority, for example, the 5th H, and in a normal case, it issues a bus use request RB2. By appropriately using the signals IIIBRQ~, l?, flexible system control becomes possible. , 8G ~ and customer Master Card support is available on the setting board 8 in the Master Card.
It can be specified flexibly using B1-883 and the setting terminal in the bus control card.

As described above, according to the present invention, pass usage requests are assigned twice to one master card, so one master card has two pass usage myc rankings, and the master card It becomes possible to issue a path usage request that matches the path usage purpose within the system.

In the embodiment of the present invention, a case has been described in which one must card has two path usage priorities, but the number of priorities assigned to each card can be easily expanded. Furthermore, by changing the number of priorities for each master card, it is possible to reduce the hardware of the path use request unit in the master card with a low path use request level and the total number of path use request signals. In this case, the setting terminal (TP
The number of inputs to the OR gate connected to (Am, TPBj) will change, but this is due to the program! Pull! This problem can be easily solved by using a thick array or the like.

Furthermore, in the embodiment of the present invention, the number of Master Cards is 16.
However, it is not limited to this and can be changed as appropriate depending on the number of pass usage requests and permission signals.

[Brief explanation of the drawing]

Part 1g shows the conventional path control system. Part 2m shows the configuration of the bus side control card in detail, especially the master card and the path usage priority control line shown in Fig. 1. Figure 5 is a circuit diagram showing the internal configuration of the master card according to the present invention, and Figure 6 is a large control card according to the present invention. O is a circuit diagram showing the internal configuration of
Code explanation CB・0. ...Common path, P...Pass use priority control line for one person...Address line, D...
Data line, T...Information transfer control line, CLK...
・・・Common Tsuta signal layer or signal line, BUC...
...Pass control card, MAC...Master card, MIC...Memory card, OUC...
...Output card, 8LC...Slave card, RIll * IEL 11 m RB 2...
...Pass use request, BOY..., -Pass use end signal, BOX...Pass use MiOK signal, BR-...
...Path request circuit section s B RQ o NBRQ
u...Path use request signal or signal @5Pf3
QO-P 8 Gu...Path use permission signal or signal line, BB8Y...Pass use signal or signal 11N...Inverter, AN...
...AND circuit, PF...Flip 7 ship, N, A...NAND circuit, OR...
OR circuit, TR, ~'rR3,,'rpA. ~TPA15. TPBo ~TPB13・-・One terminal%
8 Ex~8gm...Setting amount Agent Patent attorney Akio Namiki Agent Patent attorney Kiyoshi Matsuzaki

Claims (1)

[Scope of Claims] 1) A computer system comprising a plurality of master cards arranged in parallel on a common bus and each of which is assigned a path usage priority, and a common path control card that controls each of the master cards. 1. A path control method in which each master card is controlled by a path control card according to its priority order, characterized in that a wIWL priority order is assigned to at least one of the master cards. 2) In the path control method described in Claim H, paragraph 1, the common path includes at least a signal line for sending a path use request signal from the master card to the path control card, and one path from the control card to the master card. The number of path use permission signal lines, the total number of master cards, the number of path use request signal lines, and the number of path use priority levels each master card has individually. A path control method in which the total number is equal to each other is set as 0. A path control method characterized in that the priority order can be arbitrarily set and changed by using the setting board.