JPS58162042A - Semiconductor device and preparation thereof - Google Patents

Semiconductor device and preparation thereof

Info

Publication number
JPS58162042A
JPS58162042A JP4463682A JP4463682A JPS58162042A JP S58162042 A JPS58162042 A JP S58162042A JP 4463682 A JP4463682 A JP 4463682A JP 4463682 A JP4463682 A JP 4463682A JP S58162042 A JPS58162042 A JP S58162042A
Authority
JP
Japan
Prior art keywords
film
resin film
polyimide resin
nitride film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4463682A
Other languages
Japanese (ja)
Inventor
Ken Ogura
謙 小椋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP4463682A priority Critical patent/JPS58162042A/en
Publication of JPS58162042A publication Critical patent/JPS58162042A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

Abstract

PURPOSE:To reject alpha ray and alleviate warpage of wafer by forming a silicon nitride film and then a polyimide resin film sequentialaly on the element region of semiconductor substrate. CONSTITUTION:When a silicon nitride film 14 is formed by the PRD method on a silicon substrate 11, a stress by the PRD method works on the silicon substrate 11 in the direction where it elongates, causing the substrate 11 to be warped upward. Then, a polyimide resin is coated in the thickness of 30-100mum on a nitride film 14 and it is converted into the polyimide by the baking. When the polyimide resin film 15 is formed, the polyimide resin is contracted, warping downward the substrate 11. Accordingly, the substrate 11 becomes flat. Thereafter, a resist pattern is formed on the resin film 15, the resin film 15 and nitride film 14 of the bonding pad and scribe line are removed by sequentially etching the resin film 15 and nitride film 14, and moreover element is heated. Thereby, the alpha ray rejecting and protecting film consisting of the silicon nitride film 14 and polyimide resin film 15 can be obtained on the element region 12.

Description

【発明の詳細な説明】 この発明社、α線阻止保護膜を有する高集積半導体メモ
リ素子などを有する半導体装置およびその製造方法に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a highly integrated semiconductor memory element having an α-ray blocking protective film, and a method for manufacturing the same.

電離作用の強い放射線がメモリアレイ領域を透過する際
に記憶データが反転してしまう現象が起ること線、19
78年T 、 CMayなどによシ、ダイナイックRA
M、COD に関して発表され、16th   Ann
ual  Proc@@d1ng  off  97 
8  InternatlonalBeliall 1
1tF PhFsias S)rmposiumに詳述
されている。この現象は、セルへ再度書込めば、正常に
動作することからデバイスが破壊されていない丸め、「
ソフトエラー」と呼ばれている。この「ソフトエラー」
を生じる電離作用が強い放射線とは、ノ辛ツケージ材料
あるいはガラスフリットさらにリット°中にppm単位
で存在するり2ン、トリウムなどの自然放射性元素が崩
壊する際に発生するα線である。・臂ツケージ材料A・
ら発生するα粒子は、素材によって異なるが1−当り1
時間に0.1〜30個発生する。
Line 19: A phenomenon in which stored data is reversed when radiation with a strong ionizing effect passes through the memory array area.
1978 T, CMay, etc., Dynaic RA
Published on M, COD, 16th Ann
ual Proc@@d1ng off 97
8 InternationalBeliall 1
1tF PhFsias S)rmposium. This phenomenon means that if you write to the cell again, it will operate normally, so the device will not be destroyed.
This is called a "soft error." This "soft error"
The radiation with a strong ionizing action that causes ions is α rays, which are present in ppm units in hard cage materials, glass frits, and lits, and are generated when natural radioactive elements such as ion and thorium decay.・Arm cage material A・
The α particles generated from
0.1 to 30 occur per hour.

α線のエネルギーは最大9M・マ、平均5M5v@度で
ある0例えば*#IT h−6msmHg K g壊変
によシ放出されるα粒子のエネルギーは、””R&の核
の質量228.03123 amuとα粒子の質量4.
00260amuとの和232.03383 amu 
t−””Thの核の質量232.03821amuから
減じた0、00438竺uから、0.00438X93
1=4.08Mayとなる。
The energy of alpha particles is maximum 9M・ma, average 5M5v@degrees. and the mass of the α particle4.
Sum of 00260 amu 232.03383 amu
0.00438x93 from 0.00438xu subtracted from the mass of the nucleus of t-""Th 232.03821amu
1=4.08 May.

4M5vのα粒子の空気中の飛程Ra1t  は3.5
3でTo、j、si 中の飛程はSl の質量t−28
とし、密度ρ= 2.33 f/edとすれば、すなわ
ち、25μm中に4M@vのエネルギーを失5?−とに
なる。
The range Ra1t of 4M5v α particles in the air is 3.5
3, the range in To, j, si is the mass of Sl t-28
If the density ρ = 2.33 f/ed, that is, 4 M@v of energy is lost in 25 μm, and 5? − becomes.

したがって、4Mevのα線はSt中を約25μm走シ
、この時、1μm当夛発生する電子数nは3.6825 となシ、1.1 x 10a個/25μmとなる。
Therefore, the α ray of 4 Mev travels through St for about 25 μm, and at this time, the number n of electrons generated per 1 μm is 3.6825, which is 1.1×10a/25 μm.

そして、できた電子−正孔対のうち、正孔はp渥基板の
nチャンネルMOBデバイスの場合、基板側電極に流れ
落ちる。電子の方は活性領域に収集され、これが誤動作
の原因となる。1.I X Igs個の電子がほぼ10
0 nsかかつて電極に収集されると、そこに約2μ人
の電流が流れる。換言すれば、α線が当るということは
2μAのノ譬ルス状のリーク電流が発生することに等し
い。
Of the electron-hole pairs created, the holes flow down to the substrate-side electrode in the case of an n-channel MOB device with a p-type substrate. Electrons are collected in the active region, causing malfunctions. 1. I X Igs electrons are approximately 10
Once 0 ns is collected at the electrode, a current of about 2 μ flows through it. In other words, being hit by α rays is equivalent to generating a nollus-like leak current of 2 μA.

最初にα線の影響が問題にされたのは、前述したように
、CODメモリとダイナミックMOS RAMであった
がスタチックMO8RAM 、とくに多結晶シリコンの
高抵抗を負荷に使ったスタチックMO8RAMもα線の
影響を受は易いと考えられている。これは消費電力を下
げるためにMΩ以上の負荷抵抗によ)電流を小さくして
いるからである。
As mentioned above, the effects of alpha rays first became an issue with COD memory and dynamic MOS RAM, but static MO8RAM, especially static MO8RAM that uses high resistance polycrystalline silicon as a load, was also affected by alpha rays. considered to be easily affected. This is because the current is reduced (by using a load resistance of MΩ or more) to reduce power consumption.

前述したα線の対策には大別して、 ■ パッケージの出すα線を減少させる、■ デバイス
設計で対処する、 ■ デッグ表面に何かを塗って0αiIを止める、の3
つがある。
Countermeasures against alpha rays mentioned above can be roughly divided into three: ■ Reducing alpha rays emitted by the package, ■ Dealing with device design, and ■ Stopping 0αiI by coating the surface of the device.
There is one.

ノ譬ツケージ材料の改良によシ、ある程度α線を下げる
ことが可能でめるが、結局どのタイグの/Iパッケージ
も、0.01〜0.1 cm−” hr −” 程度が
限界である。
Although it is possible to lower alpha rays to some extent by improving the cage material, the limit for any Taigu /I package is about 0.01 to 0.1 cm-"hr-". .

α線に強くするために、デバイス設計上の改良をするに
は大別して次の2つの方法がある。
There are two main ways to improve device design in order to make it resistant to alpha rays.

(1)メモリ部に対して記憶セルの蓄積電荷容量を増大
させる方法 (11)  セ/スアング部に対してセンスアング感度
を増大させる方法 でる・る、しかし、これらデバイス設計上の改良にはチ
ップ面積が増大とするという欠点がある。
(1) A method to increase the storage charge capacity of storage cells in the memory section. (11) A method to increase the sense sensitivity in the sensor/sensing section. However, these improvements in device design require The disadvantage is that it increases.

これらの結果、「ン7トエラー」の防止については、集
積回路チップ上に、有機材料管コーティングする方法が
最も確実な方法とされている。
As a result, the most reliable method for preventing "interval errors" is to coat an integrated circuit chip with an organic material tube.

従来のチップコート方法は、チップラ・量ツクージに組
立てた後に、ボリイ建ドあるいはシリコンIs4脂を−
下し、加熱硬化させている。しかし、この方法は、を極
ワイヤと樹脂との接触によ・シ、ワイヤに張力がかかり
断線を生じる場合がToJ)、信頼性上大きな問題とな
る。
In the conventional chip coating method, after assembling the chip plate or coating, a coating of BORI-KEN or silicon Is4 resin is applied.
It is then heated and cured. However, this method poses a major problem in terms of reliability, as the contact between the pole wire and the resin may cause tension on the wire, resulting in disconnection (ToJ).

この問題を解決するために、ウェハ表面に樹脂を塗布し
た後にパッド部分を除去する方法、めるいは樹脂をスク
リーン印刷法によってノ4ツド部分以外に塗布する方法
が、電極ワイヤ部と樹脂とを接触させないために検討さ
れている。しかし、こ朴らの方法は、樹脂塗布後の加熱
によるm脂の収縮によってウェハのそ)がきわめて大き
くなるという問題がある。
To solve this problem, there is a method in which the pad portion is removed after applying resin to the wafer surface, or alternatively, a method in which the resin is applied to areas other than the grooves using a screen printing method. Consideration is being given to prevent contact. However, the method of Koboku et al. has a problem in that the wafer warp becomes extremely large due to shrinkage of the resin due to heating after resin coating.

第1図にウェハのそシと樹脂膜厚との関係を示す、第1
図かられかるように、樹脂膜厚が50μmでおよそ11
00j@度の凹形のそりをウェハに与える。そして、ウ
ェハの装置ステージへの真空チャッキング動作が不可能
とな夛、プ四セス進行が不可能になるという欠点がある
Figure 1 shows the relationship between wafer edge and resin film thickness.
As can be seen from the figure, when the resin film thickness is 50 μm, it is approximately 11
A concave warp of 00j@degrees is given to the wafer. Furthermore, since vacuum chucking of the wafer to the apparatus stage is not possible, it is also impossible to proceed with the process.

これについて、jIZ図葎)、(b)t−#照して説明
する。第2図(a)において、1紘シリコン基板、2は
シリコン基板1に形成した集積回路能動チップ部。
This will be explained with reference to jIZ diagram) and (b) t-#. In FIG. 2(a), 1 is a silicon substrate, and 2 is an integrated circuit active chip portion formed on the silicon substrate 1.

3はシリコン基板lに前記集積回亀能動チッグ部2t−
覆って塗布したポリイミド*m*である。シリコン基板
1にポリイミ、ド樹脂膜3t−塗布した後、これ′t−
ポリイミド化する丸めに加熱工程を行うと、第2図(b
)に示すようにシリコン基板1が凹形にそり、この基板
11:集積回路製造装置の基板真空デャツキング部4に
吸引チャッキングさせようとしても、吸引によるチャッ
キングが不可能になる。
3, the integrated circuit active chip part 2t- is mounted on the silicon substrate l.
It is polyimide*m* coated over it. After coating the silicon substrate 1 with a polyimide resin film 3t-, this 't-
When a heating process is performed on the rounded material to be converted into polyimide, the result is shown in Figure 2 (b).
), the silicon substrate 1 warps in a concave shape, and even if the substrate 11 is attempted to be suction-chucked by the substrate vacuum decking section 4 of the integrated circuit manufacturing apparatus, chucking by suction becomes impossible.

この発明は、前述した従来の欠点を除去しようとするも
のでToシ、半導体基板の素子領域上にシリコン窒化膜
を形成し、この窒化膜上にポリイミド樹脂膜を形成する
ことによシ、αat阻止でき、しかもウェハのそりを軽
減させることができる半導体装置およびその製造方法を
提供することを目的としている。
This invention attempts to eliminate the above-mentioned conventional drawbacks, and by forming a silicon nitride film on the element region of a semiconductor substrate and forming a polyimide resin film on this nitride film, αat It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can prevent warping of a wafer and reduce warping of a wafer.

以下、この発明の一実施例につき第3図(&)〜(@)
′t−参照して説明する。
The following is an example of this invention shown in Figs. 3 (&) to (@).
't- will be explained with reference to.

第3図(&)〜(e) hこの発明の一実施例による半
導体装置の製造方法を工程順に示す、第3図(&)にお
いて、11はシリコン基板、12はシリコン基板11に
形成した集積回路能動チップ部である。第3図(b)は
第3図(a)に示すウエノ・にプラズマデポジション法
(以下PRD法という)によってシリコン窒化膜を形成
している状態を示す、なお、第3図(b)中13はプラ
ズマである。この工程で、第3図(a)に示すように、
シリコン基板1上に厚さ1〜5μmのシリコン窒化膜1
4を形成する。前記PRD法1による応力はシリコン基
板1に対して伸びる方向に働き、第3図(c)に示すよ
うに、シリコン基板1會凸形にそらせる。そして、PR
D法によるシリコン窒化膜は膜厚を厚くしてもクラック
が生じない利点があることを見出した6次に、第3図(
d)に示すように、シリコン窒化[14上にポリイミド
樹脂を厚さ30〜100μm塗布し、ベーキングしてポ
リインド化させ、ポリイミド樹脂膜15を形成する。こ
の工程で、ポリイ< ffN脂は収縮するので凸形にな
っていたシリコン基板1゛會凹形にしようとし、シリコ
ン基板11tl−平板化させる。その後、ポリイミド樹
脂膜上にネガ形ホトレジス)t−塗布してベーキングし
、所定部分tμ光して現像し、レジストノ臂ターンを得
る。その後、ヒドラノン系エッチャントによってポリイ
セド樹脂Jfi15f:エッチングし、さらに、下層の
PRD法によるシリコン窒化膜14’tCFA系プラズ
マによってエツチングすることにより、ボンデインダノ
ダツド部分およびスクシイゾライン部分の前記樹脂膜1
5および窒化膜14を除去した後。
3(&) to (e) h A method for manufacturing a semiconductor device according to an embodiment of the present invention is shown in order of steps. In FIG. 3(&), 11 is a silicon substrate, and 12 is an integrated circuit formed on the silicon substrate 11. It is a circuit active chip part. FIG. 3(b) shows a state in which a silicon nitride film is formed by the plasma deposition method (hereinafter referred to as PRD method) on the Ueno film shown in FIG. 3(a). 13 is plasma. In this process, as shown in Figure 3(a),
Silicon nitride film 1 with a thickness of 1 to 5 μm on a silicon substrate 1
form 4. The stress produced by the PRD method 1 acts on the silicon substrate 1 in an elongated direction, causing the silicon substrate 1 to deflect into a convex shape, as shown in FIG. 3(c). And PR
It was discovered that the silicon nitride film produced by the D method has the advantage that no cracks occur even when the film thickness is increased.
As shown in d), a polyimide resin is applied to a thickness of 30 to 100 μm on the silicon nitride film 14 and baked to form a polyind film, thereby forming a polyimide resin film 15. In this step, since the polyester resin shrinks, the silicon substrate 11, which had been convex, is made into a concave shape, and the silicon substrate 11tl is flattened. Thereafter, a negative type photoresist (T) is coated on the polyimide resin film and baked, and a predetermined portion is exposed to Tμ light and developed to obtain a resist arm turn. Thereafter, the polyiside resin Jfi15f: is etched using a hydranone etchant, and the lower silicon nitride film 14' formed by the PRD method is further etched using CFA-based plasma to form the resin film 1 on the bonded and oxidized portions and the squeezable line portion.
5 and after removing the nitride film 14.

レノストを除去し、さらに加熱することにより第3図(
6)に示すように、半導体基板11の素子領域上に7リ
コン窒化展14とポリインド樹脂JI115とからなる
α線阻止保睦膜を有した半導体装置を得る。
By removing the lenost and further heating, Figure 3 (
As shown in step 6), a semiconductor device having an α-ray blocking protective film made of 7-licon nitride 14 and polyind resin JI 115 on the element region of the semiconductor substrate 11 is obtained.

前述したように、この発明の一実施例では、Iリイミド
樹脂膜の加熱による収縮でシリコン基板が凹形にそるこ
とによる欠点を、犀さ5μm以上の膜厚でもクラックを
生じることがない利点をもつPRD法によるシリコン窒
化J[t−予めシリコン基板に堆積させてこの基板を凸
形にしてお亀、その凹形のそりと相殺することで、シリ
コン基板を平坦化して解消することができる。そして、
この製造工程は、従来のLSI製造工箇の自動化装置を
使用して、ポリイミド樹脂膜會容易に・9ターニング形
成することができ、集積回路チップの容器からのα線を
阻止し、高性能、高信頼性のLSIが得られる。
As mentioned above, in one embodiment of the present invention, the drawback that the silicon substrate warps into a concave shape due to shrinkage due to heating of the I-imide resin film is overcome by the advantage that no cracks occur even when the film thickness is 5 μm or more. Silicon nitride by the PRD method can be deposited on a silicon substrate in advance to make the substrate convex and offset the concave warpage, thereby flattening the silicon substrate and eliminating the warpage. and,
This manufacturing process uses conventional automated LSI manufacturing equipment to easily form a polyimide resin film with 9 turns, blocks alpha rays from the integrated circuit chip container, and achieves high performance and high performance. A highly reliable LSI can be obtained.

以上説明したように、この発明の半導体装置は。As explained above, the semiconductor device of the present invention is provided.

高集積素子を有する半導体基板の素子領域上に。On an element region of a semiconductor substrate having highly integrated elements.

PRD法で形成したシリコン窒化膜と、この窒化膜上に
形成したポリイミド樹脂膜とからなるα線阻止保護膜を
設けたので、半一導体基板のそ#)を軽減して、ポリイ
ミド11脂膜t−30〜100μm以上の厚さに形成す
ることができ、α線による「ソフトエラー」を確実に阻
止できる効果があ夛、超LSIに利用することができる
。1だ、この発明による半導体装置の製造方法は、前述
したα線阻止保ia膜を有する半導体装置を、従来の製
造装置によって容易に製造できるという効果がある。
Since we provided an α-ray blocking protective film consisting of a silicon nitride film formed by the PRD method and a polyimide resin film formed on the nitride film, the thickness of the semiconductor substrate was reduced and the polyimide 11 resin film was It can be formed to a thickness of t-30 to 100 μm or more, has the effect of reliably preventing "soft errors" caused by alpha rays, and can be used for VLSI. First, the method for manufacturing a semiconductor device according to the present invention has the effect that a semiconductor device having the above-mentioned α-ray blocking ia film can be easily manufactured using conventional manufacturing equipment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はポリイミド樹脂膜によるシリコン基板のそシを
説明する図、第2図(a)および(b)はシリコン基板
にポリイミド樹脂を塗布し丸断面図およびポリイミド樹
脂膜を加熱した後の断面図、第3図←)〜(e)はこの
発明の一実施例による半導体装置の製造方法を工程順に
示す断面図である。 11・・・シリコン基板、12・・・集積回路能動チッ
プ部、13・・・グラズマ、14・・・シリコン窒化膜
、15・・・ポリイミド樹脂膜。 特許出願人  沖電気工業株式会社 第1図 ;t、” リ(ミル噂tt Jl! J!さくpm)第
2図 第3図 手続補正書 昭和57年8月31日 特許庁長官****  殿 1、事件の表示 昭和s7年畳 許  願第 しtsss  号2 @@
04称 亭導体装置およびその調造2F機 3、補正をする者 事件との関係     畳 許 出願人(01・)沖電
気工皇株式金社 4、代理人 5、補正命令の日付  昭和  年  月  日(幽−
)「動11ab息10FJ&訂五す為。
Figure 1 is a diagram illustrating the bending of a silicon substrate using a polyimide resin film, and Figures 2 (a) and (b) are a round cross-sectional view after applying polyimide resin to a silicon substrate, and a cross-sectional view after heating the polyimide resin film. Figures 3<->) to 3(e) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. DESCRIPTION OF SYMBOLS 11... Silicon substrate, 12... Integrated circuit active chip part, 13... Glazma, 14... Silicon nitride film, 15... Polyimide resin film. Patent Applicant: Oki Electric Industry Co., Ltd. Figure 1; t," Ri (Mill Rumor tt Jl! J! Saku pm) Figure 2 Figure 3 Procedural Amendment August 31, 1980 Commissioner of the Patent Office **** Hall 1, Display of the incident Showa s7 year tatami permission request number shi tsss number 2 @@
04 name conductor device and its preparation 2F machine 3, relationship with the case of the person making the amendments Akira Tatami Applicant (01.) Oki Electric Co., Ltd. Kinsha 4, Agent 5, Date of amendment order Showa year, month, day (Yu-
) ``To do 11ab breath 10FJ&revise.

Claims (2)

【特許請求の範囲】[Claims] (1)高集積素子を有する半導体基板の素子領域上に1
プラズマデポジシM/法で形成したシリコン窒化膜と、
この窒化膜上に形成し九ポリイ電ド樹脂膜とからなるα
線阻止保護膜を設は九ことを特徴とする半導体装置。
(1) One layer is placed on the element area of a semiconductor substrate having highly integrated elements.
A silicon nitride film formed by plasma deposition M/ method,
α formed on this nitride film and consisting of a nine polyide resin film
1. A semiconductor device comprising a radiation blocking protective film.
(2)半導体基板に高集積素子を形成する工程と、前記
高集積素子を有する半導体基板上にプ5)Jeマデボヅ
シlン法でシリコン窒化膜を形成する工程と、前記窒化
膜上にポリイミド樹脂を塗布して加熱しポリイミド樹脂
膜を形成する1龜と、このボリイ建ド樹脂膜上にレゾス
トの塗布、加熱、無光、amを行いがンデインダパッド
部分およびスクライプライン部分のポリインド樹脂膜お
よびシリコン窒化膜を除去して素子領域上にシリコン窒
化膜とポリイミド樹脂膜とからなるα線阻止保護膜を残
す工程と、°前記しVストを除去し先後加熱する工程と
を含むことを特徴とする半導体装置の製造方法。
(2) a step of forming a highly integrated element on a semiconductor substrate; a step of forming a silicon nitride film on the semiconductor substrate having the highly integrated element; The polyimide resin film is coated and heated to form a polyimide resin film, and the polyimide resin film and silicon nitride are coated on the polyimide resin film, heated, non-lighted, and subjected to an ampere treatment. A semiconductor characterized by comprising a step of removing the film to leave an α-ray blocking protective film made of a silicon nitride film and a polyimide resin film on the element region, and a step of removing the V-stride and heating before and after. Method of manufacturing the device.
JP4463682A 1982-03-23 1982-03-23 Semiconductor device and preparation thereof Pending JPS58162042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4463682A JPS58162042A (en) 1982-03-23 1982-03-23 Semiconductor device and preparation thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4463682A JPS58162042A (en) 1982-03-23 1982-03-23 Semiconductor device and preparation thereof

Publications (1)

Publication Number Publication Date
JPS58162042A true JPS58162042A (en) 1983-09-26

Family

ID=12696907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4463682A Pending JPS58162042A (en) 1982-03-23 1982-03-23 Semiconductor device and preparation thereof

Country Status (1)

Country Link
JP (1) JPS58162042A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6229143A (en) * 1985-07-29 1987-02-07 モトロ−ラ・インコ−ポレ−テツド Application of material for semiconductor wafer
KR100652395B1 (en) 2005-01-12 2006-12-01 삼성전자주식회사 Semiconductor device having reduced die-warpage and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6229143A (en) * 1985-07-29 1987-02-07 モトロ−ラ・インコ−ポレ−テツド Application of material for semiconductor wafer
KR100652395B1 (en) 2005-01-12 2006-12-01 삼성전자주식회사 Semiconductor device having reduced die-warpage and method of manufacturing the same

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