JPS58161358A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58161358A
JPS58161358A JP57032234A JP3223482A JPS58161358A JP S58161358 A JPS58161358 A JP S58161358A JP 57032234 A JP57032234 A JP 57032234A JP 3223482 A JP3223482 A JP 3223482A JP S58161358 A JPS58161358 A JP S58161358A
Authority
JP
Japan
Prior art keywords
wiring
circuit units
circuit
short
units arranged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57032234A
Other languages
Japanese (ja)
Inventor
Keizo Aoyama
青山　慶三
Takahiko Yamauchi
山内　隆彦
Teruo Seki
照夫 関
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57032234A priority Critical patent/JPS58161358A/en
Priority to EP83301104A priority patent/EP0087979B1/en
Priority to DE8383301104T priority patent/DE3380548D1/en
Publication of JPS58161358A publication Critical patent/JPS58161358A/en
Priority to US06/915,967 priority patent/US4809046A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/005—Circuit means for protection against loss of information of semiconductor storage devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G11C11/4125—Cells incorporating circuit means for protecting against loss of information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To reduce space among circuit units, and to improve the degree of integration by arranging a second wiring of comparatively low resistance orthogonally crossing with first wiring of comparatively high resistance so as to run along the insides of the circuit units. CONSTITUTION:Wirings SL'1, SL'2 for short-circuiting a grounding wire are arranged so as to run along the central sections of memory cells MC13, MC23, MC33..., MC16, MC26, MC36... in parallel with bit lines BL1, BL2 at a regular interval (an interval corresponding to three memory cells in the figure). Accordingly, since there is no special space, the area required of the device is reduced, and the degree of integration can be improved.

Description

【発明の詳細な説明】 （１）発明の技術分野 本発明は配線構造を改良して集積度を向上させた半導体
装置に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device with improved wiring structure and increased degree of integration.

（２）発明の背景 近年、半導体装置の集積度は益々向上して来ているが、
その要求は依然として高い。本発明は、マトリックス状
に配列された回路ユニットを備えた半導体装置において
、電源電圧や信号を供給するための配線の配置に改良を
加えて集積度を高くしようとするものであシ、例えばス
タティック型半導体配憶装置の接地線の配置の改良に関
する。(2) Background of the Invention In recent years, the degree of integration of semiconductor devices has been increasing.
The demand remains high. The present invention aims to increase the degree of integration by improving the arrangement of wiring for supplying power supply voltage and signals in a semiconductor device equipped with circuit units arranged in a matrix. This invention relates to improvements in the arrangement of ground lines in type semiconductor storage devices.

（３）従来技術と問題点 第１図は本出願人により、本願と同日に特許出軸された
「半導体記憶装置」において開示された配線構造を採用
したスタティック型半導体記憶装置の要部を示すブロッ
ク図である。第１図において、スタティック型メモリセ
ルＭＣ１１＋　ＭＣ，、、・・・がマ）　ＩＪソックス
状配置されており、各列方向のメモリセルＭＣｌｌｌＭ
Ｃ２１９ＭＣ５１，・・・、ＭＣ１□、ＭＣ２２゜ＭＣ
３□、・・・、にはそれぞれ、ビット線対ＢＬ１とる。(3) Prior Art and Problems Figure 1 shows the main parts of a static semiconductor memory device that employs the wiring structure disclosed in "Semiconductor Memory Device", which was patented by the applicant on the same day as the present application. It is a block diagram. In FIG. 1, static type memory cells MC11+ MC,... are arranged in an IJ sock shape, and memory cells MCllllM in each column direction
C219MC51,..., MC1□, MC22゜MC
Each of 3□, . . . has a bit line pair BL1.

従来は、接地線はビット線対と同一の導電層で形成され
、各ビット線対の間をビット線対と同一の方向に走行す
るように配置されていたが、上記本出願人の提案による
「半導体記憶装置」において示したように接地線をビッ
ト線と異なる導電層で形成して、積層構造にしたことに
より、第１図に示すように、接地線ＧＮＤ、、ＧＮＤ２
．・・・をビット線と直交する方向に走行するように配
置することが可能となった。接地線ＧＮＤ　、は行方向
のメモル・・・も同様に各行方向のメモリセルと接続さ
れている。接地線ＧＮＤ１．　ＧＮＤ２．・・・　をポ
リシリコン等の比較的高抵抗の導電層で形成した場合、
接地線の抵抗値の増大を補償するためにアルミニウム等
の比較的低抵抗の導電層で接地線を短絡すゐ必要が生じ
る。第１図においてはビット線と同一の導電層で形成さ
れた短絡用配線８Ｌ１．　ＳＬ２．・・・がビット線に
平行に所定間隔（図においてメモリセル３個分゛の間隔
）を置いて配置されておシ、配線ＳＬ、は接地線ＧＮＤ
１１ＧＮＤ２１ＧＮＤ３．・・・にノードＮ、１１Ｎ２
１１　Ｎ３１　’・・・でそれぞれ接続されておシ、配
線ＳＬ２は接地線ＧＮＤ４．　ＧＮＤ２．　ＧＮＤ、　
、・・・にノードＮ１２゜Ｎ２□ＴＮ５２＋・・・でそ
れぞれ接続されている。Conventionally, the ground line was formed of the same conductive layer as the bit line pair, and was arranged to run between each bit line pair in the same direction as the bit line pair. As shown in "Semiconductor Memory Device", the ground line is formed of a conductive layer different from that of the bit line and has a laminated structure, so that the ground lines GND, , GND2, as shown in FIG.
．． ... can now be arranged so as to run in a direction perpendicular to the bit lines. The ground line GND is similarly connected to the memory cells in the row direction. Ground wire GND1. GND2. ... is formed from a relatively high-resistance conductive layer such as polysilicon,
To compensate for the increased resistance of the ground line, it becomes necessary to short the ground line with a relatively low resistance conductive layer such as aluminum. In FIG. 1, short-circuit wiring 8L1. is formed of the same conductive layer as the bit line. SL2. ... are arranged parallel to the bit line at a predetermined interval (an interval of three memory cells in the figure), and the wiring SL is connected to the ground line GND.
11GND21GND3. ... to node N, 11N2
11, N31'..., and the wiring SL2 is connected to the grounding line GND4. GND2. GND,
, . . . are connected to nodes N12°N2□TN52+ . . . , respectively.

従来は、短絡用配線ＳＬ１．８Ｌ２．・・・を配置する
丸めに、メモリセルの間に特別のスペースＳＰが設けら
れておシ、この特別のスペースＳＰの存在ニよυ、スタ
ティック型半導体記憶装置の集積度の向上に制限が加え
られていた。Conventionally, short circuit wiring SL1.8L2. A special space SP is provided between the memory cells to arrange ..., and the existence of this special space SP imposes restrictions on the improvement of the degree of integration of static semiconductor memory devices. It was getting worse.

（４）　　発明の目的 本発明の目的は、上述の杢出頌人提案の「半導体記憶装
置」における接地線と接地線短絡用配線の配置に付随す
る問題にかんがみ、マ）　ＩＪソックス状配置された回
路ユニットを備えた半導体装置゛において、比較的高抵
抗の第１の配線と直交する比較的低抵抗の第２の配線を
回路ユニットの内側を走行するように配置することによ
り、回路ユニット間のスペースを縮少させて集積度を向
上させることにある。(4) Purpose of the Invention The purpose of the present invention is, in consideration of the problems associated with the arrangement of the grounding wire and the wiring for shorting the grounding wire in the above-mentioned "semiconductor storage device" as proposed by Mokide, In a semiconductor device equipped with a circuit unit, by arranging a relatively low-resistance second wire that is orthogonal to a relatively high-resistance first wire so as to run inside the circuit unit, the connection between the circuit units is improved. The goal is to reduce the space required and improve the degree of integration.

（５）発明の構成 上記の目的を達成するために、本発明によシ提供される
ものは、第１の方向および第２の方向にマトリックス状
に配置された回路ユニット、該第１の方向に配列された
回路ユニットに接続され、第１の導′邂層により形成さ
れる第１の配線、該第１の配線上の所定距離毎に該第１
の配線と交差し、該第１の導電層よりも低抵抗の第２の
導電層により形成され、該第２の方向に走行する第２の
配線および該第１の配線と該第２の配線との交差部に設
けられ、該第１の配線と該第２の配線を短絡するための
コンタクト部、を具備し、該第２の配線の各々は、該第
２の方向に配置された一列の該回路ユニットの内側を走
行するように配置されておシ、該第１の配線と該第２の
配線を介して骸回路ユニットの各々に電源電圧又は信号
を供給するようにした半導体装置である。(5) Structure of the Invention In order to achieve the above object, the present invention provides circuit units arranged in a matrix in a first direction and a second direction; a first wiring connected to the circuit units arranged in the first wiring and formed by the first conductive layer;
a second wiring that intersects with the wiring, is formed of a second conductive layer having a lower resistance than the first conductive layer, and runs in the second direction, and the first wiring and the second wiring. a contact portion provided at an intersection of the first wire and the second wire for short-circuiting the first wire and the second wire, each of the second wires having a contact portion arranged in a row arranged in the second direction. A semiconductor device arranged to run inside the circuit unit, and supplying a power supply voltage or a signal to each of the circuit units via the first wiring and the second wiring. be.

該回路ユニットはスタティック型メモリセルであシ、該
第１の配線はポリシリコンで形成された接地線であシ、
該第２の配線はアルミニウムで形成された接地線短絡用
配線であることが好ましい。The circuit unit is a static memory cell, the first wiring is a ground line made of polysilicon,
Preferably, the second wiring is a ground line shorting wiring made of aluminum.

（６）発明の実施例 以下、本発明の実施例を図面に基づいて説明する。(6) Examples of the invention Embodiments of the present invention will be described below based on the drawings.

第２図は本発明の一実施例によるスタティック型半導体
記憶装置の要部ブロック図である。第２図において第１
図と異なるところは、接地線短絡用配線ＳＬ、、　ＳＬ
２．・・・に替えて、ＳＬ、’　、　８Ｌ２’、・・・
が設けられておシ、メモリセル間に接地線短絡用配線Ｓ
Ｌ１’　、　ＳＬ、’・・・　のための特別なスペース
が設けられていないことである。接地線短絡用配線ＳＬ
、’。FIG. 2 is a block diagram of main parts of a static semiconductor memory device according to an embodiment of the present invention. In Figure 2, the first
The difference from the diagram is the ground wire short-circuit wiring SL, SL
2. ...instead of SL,', 8L2',...
is provided, and a ground wire short-circuit wiring S is provided between the memory cells.
No special space is provided for L1', SL,'... Ground wire short circuit wiring SL
,'.

ＳＬ２’、・・・は、所定間隔（図においてはメモリセ
ル３個分の間隔）を置いてビット線に平行にメモリセル
ＭＣ１，、ＭＣ２５，ＭＣ！１．、−、　ＭＣ，６，Ｍ
Ｃ２６，ＭＣ，６゜・・・の中央部を走行するように配
置されている。第１図に示した舶き、特別のスペースＳ
Ｐが存在しないので、装置の所用面積は縮少され高集積
化を図ることができる。特にメモリ容量が大の場合、そ
の効果は大でぞ・る。SL2', . . . are memory cells MC1, MC25, MC! parallel to the bit line at predetermined intervals (in the figure, an interval of three memory cells). 1. ,−, MC,6,M
It is arranged so as to run in the center of C26, MC, 6°... Vessel shown in Figure 1, special space S
Since P is not present, the area required for the device is reduced and high integration can be achieved. The effect is particularly large when the memory capacity is large.

第３図は第２図に示したメモリセルの１つであるＭＣ１
，の等価回路図である。第３図において、メモリ達択用
ＭＯ８）ランジスタＱ１　＋　Ｇ２のゲートにワード線
、ＷＬが共通接続されておシ、これらのトランジスタの
ドレイン（又はソース）にはピッ）ｌｉｌＢＬ、ＢＬが
それぞれ接続さねている。FIG. 3 shows MC1, which is one of the memory cells shown in FIG.
, is an equivalent circuit diagram of . In FIG. 3, a word line, WL, is commonly connected to the gates of MO8 transistors Q1 + G2 for memory selection, and pins BL, BL are connected to the drains (or sources) of these transistors, respectively. Sleeping.

交差結合されてフリップフロップを構成するＭＯＳトラ
ンジスタＱ３．Ｇ４のドレインと、トランジスタＱ１．
Ｑ２のソース（又はドレイン）はそれぞれ、ノードＮ１
およびＮ２において接続されている。MOS transistor Q3. which is cross-coupled to form a flip-flop. G4 and the transistor Q1.
The source (or drain) of Q2 is connected to node N1, respectively.
and connected at N2.

ノードＮ、、Ｎ２はそれぞれ負荷抵抗Ｒ４，Ｒ２を介し
て電源線ｖ０゜に接続されている。トランジスタＱ、ｌ
Ｑ４のソースは接地線ＧＮＤ、に共通接続されている。Nodes N, , N2 are connected to the power supply line v0° via load resistors R4 and R2, respectively. Transistor Q, l
The sources of Q4 are commonly connected to the ground line GND.

本実施例において設けられた接地線短絡用配線８Ｌ１’
　　はノードＮ、ｓにおいて接地線ＧＮＤ　。Ground line short-circuit wiring 8L1' provided in this embodiment
is the ground line GND at node N, s.

に接続されている。It is connected to the.

第４図は第３図に示したメモリセルＭＣ１３の構造を示
す平面図である。第４図において、半導体基板５ＵＢＯ
上に、トランジスタＱ３およびＧ４のゲート電極用配線
Ｇ、およびＧ４が、ポリシリコン配線層で形成されて行
方向に平行に走行するように配置されている。ＧＩＳ　
、　Ｇ４に平行に、やはりポリシリコン配線層で形成さ
れたワード線ＷＬ、接地線ＧＮＤ１、および電源Ｍｖｏ
ｏが配置されている。FIG. 4 is a plan view showing the structure of memory cell MC13 shown in FIG. 3. In FIG. 4, a semiconductor substrate 5UBO
Above, gate electrode wiring G and G4 of transistors Q3 and G4 are formed of a polysilicon wiring layer and are arranged so as to run parallel to the row direction. GIS
, parallel to G4, a word line WL also formed of a polysilicon wiring layer, a ground line GND1, and a power supply Mvo.
o is placed.

ＷＬ、　ＧＮＤ、、　Ｖ、ｃ、　Ｇ３およびＧ４の上に
絶縁層を介してアルミニウム配線層で形成されたビット
線対ＢＬ、およびＢＬ、と接地線短絡用配ＭＡＬ１’　
　が列方向に走行するように配置されている。接地線Ｇ
ＮＤ　、と接地線短絡用配線ＳＬ　、’とけノードＮ１
３で示される；ンタクト部を介して短絡されている前述
の本出願人提案の「半導体記憶装置」で示した如く、接
地線ＧＮＤ、をビット線対とは巣なる導電層でビット線
対と直交する方向に走行するように形成したことにより
、列方向の配線密度は小となって、ビット線対ＢＴ、、
、ＢＬ、の間に接地線短絡用配線ＳＬ１’を走行させる
ことが可能となった。A bit line pair BL formed with an aluminum wiring layer via an insulating layer on WL, GND, V, c, G3 and G4, and a wiring for shorting between BL and the ground line MAL1'
are arranged so that they run in the column direction. Ground wire G
ND, ground line short-circuit wiring SL, 'toke node N1
3; As shown in the above-mentioned "semiconductor memory device" proposed by the applicant, the ground line GND, which is short-circuited via a contact part, is called a bit line pair. By forming them so that they run in orthogonal directions, the wiring density in the column direction is reduced, and the bit line pairs BT, ,
, BL, it is now possible to run the ground line short-circuit wiring SL1' between the lines BL and BL.

本発明は上述のスタティック型半導体記憶装置に限定さ
れるものではなく、様々の変形が可能である。一般に、
マトリックス状に配置された回路ユニットに電源箱１圧
又は信号を供給する比較的高抵抗の第１の配線と、これ
に直交する比較的低抵抗の第２の配線とを備えた半導体
装置において、第２の配線を回路ユニットの内側を走行
させることで本発明の効果は達成される。The present invention is not limited to the above-described static type semiconductor memory device, and various modifications are possible. in general,
In a semiconductor device including a relatively high-resistance first wiring that supplies one voltage or a signal to a power supply box to circuit units arranged in a matrix, and a relatively low-resistance second wiring that is perpendicular to the first wiring, The effects of the present invention are achieved by running the second wiring inside the circuit unit.

（７）発明の効果 以上述べたように、本発明により、特にスタティック型
半導体記憶装置において、接地線短絡用配線をメモリセ
ルの内側を走行するように配置することによ如、接地線
短絡用配線のための特別のスペースが不要になり集積度
の大巾な向上を図ることが可能になる。(7) Effects of the Invention As described above, the present invention makes it possible to prevent ground line short-circuits by arranging the ground line short-circuit wiring so as to run inside the memory cell, especially in a static type semiconductor memory device. This eliminates the need for special space for wiring, making it possible to greatly improve the degree of integration.

勿論、一般の半導体装置においても、配線を回路ユニッ
トの内側を定行させることで、集積車の向上を図ること
が同様に可能である。Of course, in general semiconductor devices, it is also possible to improve the integration efficiency by having the wiring run regularly inside the circuit unit.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本出願人によシ、本願と同日に特許出願された
「半導体記憶装置」において開示された配線構造全採用
したスタティック型半導体記憶装置の要部を示すブロッ
ク図、第２図は本発明の一実施例によるスタティック型
半導体記憶装置の要部ブロック図、ｌＩ３図は第２図に
示したメモリセルの１つであるＭＣ１３の等価回路図、
８４図は第５図に示したメモリセルＭＣ１３の構造を示
す平面図である。 ＧＮＤ、　、　ＧＮＤ２．　ＧＮＤ３・・・接地線ＢＬ
１．　ＢＬｌ、　ＢＬ２．　ＢＬ２・・・ビット線対Ｓ
Ｌ、’、　ＳＬ２’・・・接地線短絡用配線Ｎ１３１Ｎ
２５＋・・・ｌＮ１６１Ｎ２６１・・・　接地線と接地
線短絡用配線のコンタ クト部 手続補正書 昭和５８年４　月２７日 特許庁長官　若杉和　夫　殿 １、事件の表示 昭和５７年　特許願　　第３２２３４号２、発明の名称 半導体装置 ３、補正をする者 事件との関係　　特許出願人 名称　（５２２）富士通株式会社 ４゜代理人 （外　３名） ５、補正の対象 明細書の「発明の詳細な説明」の欄 ６　補正の内容 明細書第７頁第１０行の［ワード線、ＷＬＪを「ワード
線ＷＬ」と補正する。FIG. 1 is a block diagram showing the main parts of a static semiconductor memory device that employs all of the wiring structures disclosed in "Semiconductor Memory Device", which was filed by the applicant on the same day as the present application, and FIG. A block diagram of a main part of a static semiconductor memory device according to an embodiment of the present invention, FIG. 1I3 is an equivalent circuit diagram of MC13, which is one of the memory cells shown in FIG.
FIG. 84 is a plan view showing the structure of memory cell MC13 shown in FIG. GND, , GND2. GND3...Grounding wire BL
1. BLl, BL2. BL2...Bit line pair S
L, ', SL2'...Grounding wire short-circuit wiring N131N
25+...lN161N261... Ground wire and ground wire short-circuit wiring contact section procedure amendment April 27, 1980 Director of the Japan Patent Office Kazuo Wakasugi 1, Indication of case 1982 Patent Application No. 32234 2 , Name of the invention Semiconductor device 3, Relationship with the case of the person making the amendment Name of patent applicant (522) Fujitsu Limited 4゜ Agent (3 others) 5. "Detailed description of the invention" of the specification to be amended Column 6: Contents of correction [Word line, WLJ on page 7, line 10 of the specification is corrected to be "word line WL."

Claims (1)

【特許請求の範囲】 １、　第１の方向および第２の方向にマトリックス状に
配置された回路ユニット、 該第１の方向に配列された回路ユニットに接続され、第
１の導電層によシ形成される第１の配線、該第１の配線
上の所定距離毎に該第１の配線と交差し、該第１の導電
層よシも低抵抗の第２の導゛邂層によシ形成され、該第
２の方向に走行する第２の配線、および 該第１の配線と該第２の配線との交差部に設けられ、該
第１の配線と該第２の配線を短絡するためのコンタクト
部、 を具備し、該第２の配線の各々は、該第２の方向に配置
された一列の核回路ユニットの内側を走行するように配
置されておシ、 ＃第１の配線と該第２の配線を介して該回路ユニットの
各々に電源電圧又は信号を供給するようにしたことを特
徴とする半導体装置。 ２、該回路ユニツ１はスタティック型メモリセルでおυ
、該第１の配線はポリシリコンで形成された接地線であ
シ、該第２の配線はアルミニウムで形成された接地線短
絡用配線であることを特徴とする特許請求の範囲第１項
記載の半導体装置。[Scope of Claims] 1. Circuit units arranged in a matrix in a first direction and a second direction, connected to the circuit units arranged in the first direction, and connected to the circuit units arranged in the first direction, and connected to the circuit units arranged in the first direction, The first wiring to be formed intersects the first wiring at predetermined distances on the first wiring, and is formed by a second conductive layer having a lower resistance than the first conductive layer. a second wiring formed and running in the second direction; and a second wiring provided at an intersection of the first wiring and the second wiring to short-circuit the first wiring and the second wiring. a contact portion for, each of the second wirings being arranged to run inside a row of nuclear circuit units arranged in the second direction, #first wiring; and the second wiring, a power supply voltage or a signal is supplied to each of the circuit units. 2. The circuit unit 1 is a static type memory cell.
, the first wiring is a grounding line made of polysilicon, and the second wiring is a grounding line shorting wiring made of aluminum. semiconductor devices.
JP57032234A 1982-03-03 1982-03-03 Semiconductor device Pending JPS58161358A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP57032234A JPS58161358A (en) 1982-03-03 1982-03-03 Semiconductor device
EP83301104A EP0087979B1 (en) 1982-03-03 1983-03-02 A semiconductor memory device
DE8383301104T DE3380548D1 (en) 1982-03-03 1983-03-02 A semiconductor memory device
US06/915,967 US4809046A (en) 1982-03-03 1986-10-06 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57032234A JPS58161358A (en) 1982-03-03 1982-03-03 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58161358A true JPS58161358A (en) 1983-09-24

Family

ID=12353283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57032234A Pending JPS58161358A (en) 1982-03-03 1982-03-03 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58161358A (en)

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