JPH0114706B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device.
This paper relates to a master slice method that can implement RAM and random gates in an area-efficient manner.

[Prior art]

Master slice LSI is a device that manufactures LSIs with desired electrical circuit behavior by creating only a few masks corresponding to wiring out of the ten or so masks used when manufacturing LSIs, depending on the product being developed. It is.

Figure 1 shows the configuration of a conventional master slice LSI. The LSI chip 1 has a bonding pad and an input/output circuit area 2 on its outer periphery, and inside it has a basic cell row 4 in which basic cells 3 consisting of transistors and the like are arranged in the x-axis direction, with a wiring area 5 in between. It has a repeating configuration. In order to obtain desired electric circuit characteristics, one or several adjacent basic cells 3 are connected to form a logic gate such as a NAND gate or a flip-flop. One LSI is constructed by connecting these logic gates according to the logic diagram.

FIG. 2 shows a plan view of the basic cell 3. The basic cell 3 includes a P ⁺ type region 6 which becomes the source or drain of a P type MOS transistor, an N ⁺ type region 7 which becomes the source or drain of an N type transistor,
P-WELL region 11 formed in the N type substrate to form the N ⁺ type region 7, P and N type MOS
Two polysilicon gate electrodes 8 shared by transistors (some do not share gate electrodes),
Vcc power line 1 that supplies power to both transistors
2. GND power line 13, P ⁺ , N ⁺ diffusion layers 6 and 7
It is comprised of a contact hole 10 for connecting to an Al wiring (not shown) and a contact hole 9 for connecting the gate electrode 8 and the Al wiring.

FIG. 3 is an expanded view of the cross-sectional structure of the basic cell 3, the wiring region 5, and the structure of the wiring layer.
Components that are the same as in FIG. 2 are designated by the same reference numerals. Elements such as transistors are formed on one surface side of the N-type substrate 20. The field oxide film 21 is the substrate 20
It exists on one surface of the film and has a film thickness of about 1 μm. There is a gate oxide film 31 under the gate electrode 8 of the transistor, and the film thickness is 500 to 1000 Å.
There is an insulating film 22 on the polysilicon wiring constituting the gate electrode 8, etc., and on top of this, the power wiring 12, 13 and the like are made of Al and run parallel to the cell rows in the longitudinal direction.
First wirings such as Al wirings 25 and 26 are formed.
Contact holes 9 and 10 are formed in the insulating film 22 when it is necessary to connect the polysilicon wiring or the diffusion layers 6 and 7 to the first wiring. An insulating film 23 is disposed on the first wiring, and second wirings 29 and 3 made of Al are disposed on top of the insulating film 23 so that most of the longitudinal direction thereof is perpendicular to the cell row.
0 is formed respectively. When it is necessary to connect the first wiring and the second wiring, a contact hole 28 is opened in the insulating film 23. An insulating film 24 is on the top layer.
It protects transistors and wiring. In a typical master slice LSI, a desired LSI is obtained by changing the mask for forming the first wiring, the second wiring, and the contact hole for connecting the two for each product. Furthermore, the mask for forming the contact hole for connecting the first wiring and the polysilicon wiring or the diffusion layer may also be changed depending on the product.

Generally, when configuring an LSI, it is often a combination of random logic circuits and a group of registers that store data values. Therefore, the deciding factor is how efficiently the above circuit can be mounted.
Possible register configuration methods include those shown in FIGS. 4 and 5 a.

FIG. 4 shows a register composed of general logic gates, including an inverter 40, AND gates 41 and 42,
It consists of NOR gates 43 and 44. When data input is input to the signal line 45 and address signals are input to the signal lines 46 and 47, the output signal 48 obtains the same value as the data input, the output signal 49 obtains its inverted value, and the NOR gates 43 and 44 obtain the same value as the data input. The state is maintained by a constructed flip-flop. If this circuit were constructed using a CMOS circuit, 18 transistors would be required. The basic cell of FIG. 2 requires five cells.

FIG. 5a shows a memory circuit that utilizes the high impedance state of the clocked inverter 50.
First, the clocked inverter will be explained with reference to FIG. 5b. The clocked inverter is composed of a MOS transistor 59 and an NMOS transistor 60, as shown in the figure. The input signal 57 is
The control signal 53 is input to both the PMOS and NMOS transistors, and the control signal 54, which generally has an inverted value thereof, is input to the NMOS transistor. Control signal 53,5
When 4 is at low level and high level respectively,
Both transistors to which the respective signals are input become conductive, and the clocked inverter operates as a normal inverter. Therefore, the output signal 58
is the inverted value of the input signal 57. Conversely, when the control signals 53 and 54 are at High level and Low level, respectively, both transistors to which the respective signals are input become non-conductive, and the output signal 58 becomes a high impedance state. Returning to Figure 5a,
This memory circuit is composed of a clocked inverter 50, an inverter 51, and an NMOS transistor 52. Data writing is performed by setting the clocked inverter 50 to a high impedance state, setting the address signal 56 to a high level, and turning the NMOS transistor 52 into a conductive state. When data is input from the input/output signal 55 connected to the data bus, the address signal 56 is set to low level.
The NMOS transistor is made non-conductive to disconnect the memory circuit and the data bus, and the control signal 53,
A flip-flop is formed by a clocked inverter 50 and an inverter 51, which operate as an inverter, by setting the clocked inverter 50 and the inverter 51 to low and high levels, respectively, to hold data. To read data,
While the clocked inverter 50 is operating as an inverter, the address signal 56 is set to a high level to turn on the NMOS transistor, thereby outputting the data of the memory circuit to the data bus.

What must be noted in this memory circuit system is the transistor size of the NMOS transistor 52. This will be explained with reference to FIG. Capacitor 61 equivalently represents the load capacitance of the data bus connected to input/output signal 57, and the same parts as in FIG. 5 are represented by the same symbols. Consider reading when the data held in the memory circuit is at a high level (point A is at a high level). In other words, when the PMOS transistor 59 is in a conductive state and the NMOS transistor 52 changes from a non-conductive state to a conductive state, the capacitor 6
1 flows. This charging current I causes the potential at point A to change to the PMOS transistor 59.
and the on-resistance of the NMOS transistor 52. If the potential at point A is lower than the threshold potential of the inverter 51, the output 57
is reversed, and the contents stored in the memory circuit are reversed. Therefore, it is necessary to make the on-resistance of the NMOS transistor 52 sufficiently large so that the potential at point A does not fall below the threshold voltage of the inverter 51. A similar situation occurs regarding low level reading.

Taking this point into consideration, FIG. 7 shows a memory circuit constructed using the conventional basic cells shown in FIG. 2. In this figure, transistors are represented by symbols, and the same parts as in FIGS. 2 and 5 are indicated by the same reference numerals. Moreover, the thick solid line represents Al wiring. In this example, the gate electrode 8 is separated to facilitate the construction of a clocked inverter, but 2.5 basic cells are still required to construct one bit of memory.

Configuring a memory circuit using conventional basic cells in this way requires a large number of basic cells and is extremely inefficient.

[Purpose of the invention]

An object of the present invention is to provide a master method that can efficiently implement random gates and memories in a master slice LSI.

[Summary of the invention]

The present invention provides an i series (for example, i=2, 3......)
In addition to the pair of first conductivity type MOS transistors (for example, PMOS) and second conductivity type MOS transistors (for example, NMOS), one second conductivity type MOS transistor (for example, NMOS)
A MOS transistor is arranged in a basic cell, and this first conductivity type MOS transistor and a second conductivity type
The implementation efficiency of memory circuits, etc. is improved by separating the gate electrodes of at least one of the i pairs of MOS transistors and sharing the gate electrodes of the other pairs. .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 8 shows a plan view of a basic cell according to the present invention. Components that are the same as in FIG. 2 are designated by the same reference numerals.
This basic cell is composed of two PMOS transistors 82 and 83 that share a source or drain, three NMOS transistors 84, 85, 86 that share a source or drain, and a polysilicon underpass 87.
2 and the NMOS transistor 84 share the gate electrode 8, and the PMOS transistor 83 and the NMOS transistor 85 are separated like the gate electrodes 80 and 81. Furthermore, the NMOS transistor 86 that is not paired with the PMOS transistor is
To configure the memory, the transistor size is about 1/3 that of other NMOS transistors.
In this way, by separating the gate electrodes of a pair of PMOS and NMOS transistors, it is easier to configure a clocked inverter, and it is also possible to create a more compact clocked inverter.
By adding NMOS transistors to basic cells, it is possible to realize memory circuits with a small number of basic cells.

FIG. 9 is an example in which the memory circuit of FIG. 5 is constructed using basic cells according to an embodiment of the present invention. Although the conventional basic cell required 2.5 gates, the basic cell of this embodiment can be configured with only 1.5 gates.

Figure 10 shows an expanded version of the 1-port memory shown in Figure 5, which allows independent reading/writing from two systems.
1 shows a circuit diagram of a port memory and an example of its configuration using basic cells according to an embodiment of the present invention. If this memory circuit were constructed using conventional basic cells, it would require four cells, but with this basic cell, it can be constructed using only half of that, two cells. If a memory is configured using this basic cell in this way, it will take 30 to 30 minutes including the decoder circuit, etc.
A 40% area efficiency improvement is possible.

In addition, when configuring the memory circuit, as shown in FIGS. 9 and 10, a small NMOS transistor 86 is used.
However, in a logic block consisting only of NAND and NOR gates, this small NMOS transistor 86 is unused. In this case,
By using the gate electrode of the NMOS transistor 86 as an underpass for wiring like the underpass 87, wiring within the logic block is facilitated. In this way, it can be effectively used as a transistor when configuring a memory, and as an underpass at other times.

In this embodiment, an example of two PMOS transistors and three NMOS transistors was explained, but two NMOS transistors and three NMOS transistors are also used.
It may be a PMOS transistor, and further,
3 series PMOS transistors, 4 series NMOS transistors, or 3 series NMOS transistors,
The present invention can also be applied to a quadruple PMOS transistor or the like.

〔Effect of the invention〕

According to the present invention, since logic gates and memory circuits can be efficiently and densely mounted, a highly integrated master slice LSI can be obtained.

[Brief explanation of drawings]

Fig. 1 is a plan view of a master slice LSI, Fig. 2 is a plan view of a conventional basic cell, Fig. 3 is a developed view of basic cell wiring layers, etc., Fig. 4 is a flip-flop circuit, Fig. 5 is a memory circuit, FIG. 6 is an explanatory diagram of malfunction of a memory circuit, FIG. 7 is an example of a memory circuit configuration using a conventional basic cell, FIG. 8 is a plan view of a basic cell according to an embodiment of the present invention, and FIGS. 9 and 10 are 1 is an example of a memory circuit configuration using a basic cell according to an embodiment of the present invention. 82, 83...PMOS transistor, 84,
85, 86...NMOS transistor.

Claims (1)

[Claims] 1. At least i series of first conductivity type MOS transistors having sources or drains connected in series, and i+1 series of second conductivity type MOS transistors having sources or drains connected in series on one main surface. At least one of the i pairs in which the first conductivity type MOS transistor and the second conductivity type MOS transistor are arranged relative to each other has a polysilicon gate electrode separated, and the other pairs share the polysilicon gate electrode. A plurality of basic cell rows are arranged in parallel in one direction to form a basic cell row, a semiconductor substrate is formed by arranging a plurality of basic cell rows in parallel in a direction perpendicular to the basic cell row, and an insulating film is formed on the semiconductor substrate. 1. A semiconductor integrated circuit device comprising a plurality of layers of wiring that are stacked together and connect within basic cells and between basic cells. 2 In claim 1, the first conductivity type
A semiconductor integrated circuit device characterized in that a second conductivity type MOS transistor that is not paired with a MOS transistor is smaller in size than other MOS transistors. 3. A semiconductor integrated circuit according to claim 1 or 2, characterized in that the gate electrode of the second conductivity type MOS transistor that is not paired with the first conductivity type MOS transistor is also used as an underbus. Device.