JPH0568862B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to, for example, a master slice type gate array type semiconductor integrated circuit device (gate array LSI).

Gate array LSI is generally known as a logic LSI design method for low-volume, high-mix production, using a master slice manufacturing process and various CAD tools, and the number of gates that can be accommodated is increasing as semiconductor technology advances in recent years. I am following.

By the way, as the scale of circuits to be accommodated increases, the number of logic circuits consisting only of random logic is decreasing, and there is a strong demand for the development of gate array LSIs with built-in memory circuits.

Figure 1 shows an example of the chip configuration of a gate array LSI with a built-in memory circuit that has been announced to date.
In the figure, on gate array LSI chip 1,
A dedicated memory area 2, an internal gate area 3 for configuring random logic, and an input, output, and input/output buffer area (hereinafter referred to as buffer area) 4 are formed.

As is well known, gate array LSIs are created in advance through the diffusion process (master process) to form transistors, and then the subsequent wiring process (slice process).
By using different mask patterns, it is now possible to realize different logic LSIs using the same master chip.

In the conventional example shown in FIG.
By changing the wiring, it has become possible to realize various logic circuits. Furthermore, the wiring between the memory dedicated area 2, internal gate area 3, and buffer area 4 can also be changed. By changing the wiring process in this manner, various logic circuits including memory circuits can be realized.

Since the conventional device is configured as described above, in order to realize a logic circuit including a memory circuit, it is necessary to provide a memory-only area designed exclusively for memory in advance in the master chip. Also, when realizing a logic circuit that does not use a memory circuit,
This dedicated memory area cannot be used for other purposes, which reduces the effective utilization rate of the chip and increases the cost of the chip.

Therefore, the main object of the present invention is to eliminate the need to provide a dedicated memory area on the master chip in advance.
An object of the present invention is to provide a semiconductor integrated circuit device in which a memory area can be realized in an arbitrary area by wiring basic cells in a wiring process.

In summary, the present invention is based on a gate array chip having a structure in which a plurality of cell row blocks are arranged in multiple stages with a wiring area in between, each consisting of a plurality of basic cells arranged on a semiconductor substrate and each consisting of a plurality of transistors. A memory circuit having a memory cell, an input/output control circuit, and a selection circuit is formed by appropriately wiring the basic cells, and the memory cell is one
A sub-memory block of bits×N words (N is an integer of 2 or more) is configured as one unit, and each sub-memory block is configured to be arranged in the same cell column block, and each sub-memory block is arranged in the same cell column block. The bit lines in the cell row block are formed along the direction in which the basic cells are arranged in the cell row block.

The above objects and other objects and features of the present invention will become more apparent from the following detailed description with reference to the drawings.

FIGS. 2 to 8 are diagrams showing an embodiment of the present invention. First, an embodiment in which a static random access memory is configured in a CMOS gate array LSI will be described with reference to FIGS. 2 to 8. In addition, in the following figures, the same reference numbers indicate the same or corresponding parts.

Figure 2 shows a gate array to which this embodiment is applied.
FIG. 3 is a diagram showing the configuration of an LSI master chip. In the figure, four buffer regions 4 are formed on a master chip 11 of a gate array LSI at its periphery. In a region surrounded by buffer region 4, internal gate region 3 is formed. In this internal gate region 3, a plurality of strip-shaped cell row blocks 30, 30, . . . are arranged at intervals. The area between each cell column block 30 is a wiring area 5,
5,... In each cell column block 30, circuit elements such as transistors are regularly arranged, as will be described later. For example, various logic gates are configured by forming wiring for these circuit elements. The inputs and outputs of the logic gate configured in this manner are appropriately connected to each other through wiring in the wiring area 5.
In this way, a circuit that performs a specific operation is created.

FIG. 3 is a plan view showing the structure of an example of basic cells formed in the cell row block 30 shown in FIG. 2. FIG. This basic cell consists of polycrystalline silicon layers (hereinafter referred to as polysilicon layers) 301a to 301a, which constitute the gate of a P-channel MOS transistor (POST).
01d, polysilicon layers 302a to 302d forming the gate of the N-channel MOS transistor (NMOS), and P-type diffusion regions 303a to 303e forming the source and drain of the PMOST.
and N that constitutes the source and drain of NMOST
It includes type diffusion regions 304a to 304e and an N-well diffusion region 305 formed on a P-type substrate.

FIG. 4 is a sectional view taken along the line - shown in FIG. 3. In the figure, on a P-type semiconductor substrate 9,
The aforementioned polysilicon layers 301a to 301d and P-type diffusion regions 303a to 303e are formed, and a thick field insulating film 6 made of SiO ₂ is formed.
Then, a first interlayer insulating film 7 and a gate insulating film 8 made of a thin oxide film are formed. The first interlayer insulating film 7 includes polysilicon layers 301a to 301d.
This is to electrically insulate the wiring layer and the wiring layer above it. The gate insulating film 8 is for electrically insulating the gate and the channel region.

FIG. 5 is a sectional view taken along the line - shown in FIG. 3. Since the cross-sectional structure of FIG. 5 is almost the same as the cross-sectional structure of FIG. 4 described above, detailed explanation thereof will be omitted. Note that in FIG. 5, the N-well diffusion region 305 as shown in FIG. 4 is not provided.
This is because the semiconductor substrate 9 is of P type and FIG. 5 shows the cross-sectional structure of NMOST.

FIG. 6 is a circuit diagram showing an example of a transistor circuit of a memory cell used in this embodiment. In the figure, this transistor circuit consists of PMOST401
b and 401c and NMOST402a-40
2d, and data terminals 406a and 406b.
and a memory cell selection terminal 407. PMOST4
01c and 401b and NMOST 402c and 402b form a bistable circuit using a CMOS inverter. NMOST402a
and 402d are pass gate switches that connect or disconnect the terminal where data of the bistable circuit is held (holding terminal) and the data terminals 406a and 406b. That is, when the potential of the memory cell selection 407 is logically high potential (high level), the pass gate switches 402a and 402
d is turned on, and the above-mentioned holding terminal and data terminal 406
Connect a and 406b. At this time, the memory cell can be read and written. On the other hand, when the potential of the memory cell selection terminal 407 is logically low potential (low level), the pass gate switch 40
2a and 402d are turned off, cutting off the holding terminal and data terminals 406a and 406b. At this time, the memory cell retains the stored data.

Figure 7 shows the transistor circuit shown in Figure 6.
FIG. 2 is a plan view showing a 1-bit memory cell realized on the basic cell shown in the figure. In the figure, first and second wiring layers are stacked on a basic cell, and various wirings are provided by these first and second wiring layers. That is, bit line 30
6a and 306b and two word lines 30
7, a power line 310, and a ground line 311 are formed. Note that the bit lines 306a and 306b, the power supply line 310, and the ground line 311 are interconnects in the first interconnect layer. Further, the word line 307 is a wiring formed in the second wiring layer. Furthermore, the basic cell has two wires 3
08 and two wirings 309 are formed. The wiring 308 is a wiring in the first wiring layer, and each
Connect the gate, source, and drain of MOST.
Further, the wiring 309 is a wiring in the first wiring layer, and connects the gate of the word line 307 and a predetermined MOST. Each line and each wiring
Connection with the MOST is made by forming a contact hole 101. This contact hole 101 is formed in the first interlayer insulating film 7 (FIG. 4 and (See Figure 5).
Further, the word line 307 and the wiring 309 are connected by forming a through hole 102. This through hole 102 is formed in a second interlayer insulating film (an electrical connection between the first wiring layer and the second wiring layer) in order to electrically connect the first wiring layer and the second wiring layer thereon. (insulating film for electrical insulation)
It is a hole made in the.

Figure 8 shows a 2-bit x 4-word system consisting of the 1-bit memory cell and peripheral circuitry shown in Figure 7.
FIG. 3 is a circuit diagram showing the configuration of RAM. In the figure,
This RAM is composed of a memory cell selection signal generation circuit (address decoder) 41 and two sub-memory blocks 42. The memory cell selection signal generation circuit 41 includes two inverters 50a and 5
0b and four AND gates 51a to 51b. A binary address signal for selecting a predetermined word in sub memory block 42 is applied to address signal input terminals AO and A1. Address decoder 41 decodes this address signal and AND gates 51a to 5
A selection signal is derived from 1d for a desired memory cell.

1-bit memory cells 40a-40h are the 1-bit memory cells shown in FIG. 1-bit memory cells 40a and 40e, 40b and 40f, 40
c and 40g, and 40d and 40h each constitute one word. These 2 bits x 4 words memory cells are divided into 1 bit x 4 words submemory blocks. That is, one of the two sub-memory blocks 42 includes 1-bit memory cells 40a to 40d, and the other sub-memory block includes 1-bit memory cells 40a to 40d.
Including e to 40h.

Here, each sub-memory block 42 is formed on the same cell example block 30 (see FIG. 2). That is, one submemory block 42 is not formed across a plurality of cell column blocks 30. Therefore, 1-bit memory cells 40a to 40d are formed on the same cell column block, and similarly 1-bit memory cells 40a to 40d are formed on the same cell column block.
Cells e to 40h are also formed on the same cell row block. Then, 1-bit memory cells 40a to 40d
The bit lines 306a and 306a are arranged adjacently for each bit and connect the respective memory cells.
06b is wired along the arrangement direction of each memory cell. Similarly, 1-bit memory cells 40e to 4
Bit lines 306a and 306 are also arranged adjacent to each other for each bit, and connect each memory cell.
b is wired along the arrangement direction of each memory cell. Preferably, bit lines 306a and 3
06b is wired on the cell column block 30 shown in FIG. However, the cell row block 30
If there is no such wiring space above, the wiring may be done in the wiring area 5. However, in this case as well, the bit lines 306a and 30
6b is wired parallel to the arrangement direction of each 1-bit memory cell. With such a configuration, the wiring lengths of the bit lines 306a and 306b in each sub-memory block 42 are substantially constant and short. Therefore, the bit line parasitic capacitance of each sub-memory block becomes constant and small. As is well known, in a memory circuit, if the parasitic capacitance of the bit line is large, the access time becomes long. Furthermore, if the parasitic capacitance of the bit line has large variations, the access time will fluctuate and the operation will become unstable. In this embodiment, the parasitic capacitance of the bit line can be made small and constant as described above, so that access time can be shortened and performance can be stabilized.

Each sub-memory block 42 further includes an input/output circuit and a pull-up circuit. The input/output circuit of one sub-memory block 42 is an inverter 50.
50e and a pass control transistor switch 404a based on NMOST.
The input/output circuit of the other sub-memory block 42 is composed of inverters 50d, 50f and a pass control transistor 404b formed by NMOST. Further, the pull-up circuit of one sub-memory block 42 is connected to PMOST 403a and 403b.
and the other sub-memory block 4
2 pull-up circuit is PMOST403c and 4
03d.

Next, a more detailed configuration and operation of the embodiment shown in FIG. 8 will be explained.

The pull-up circuit provided in each sub-memory block 42 includes bit lines 306a and 30.
6b is connected. This pull-up circuit connects bit lines 306a and 30 when reading data.
This is to prevent erroneous data from being written into the memory cell due to the parasitic capacitance of 6b. Further, the bit line 306b of one sub-memory block 42 is connected to the data output terminal D _OUT 0 via the inverter 50c.
It is connected to data input terminal D _IN 0 via pass control transistor switch 404a and inverter 50e. Similarly, the bit line 306b of the other sub-memory block 42 is connected to the inverter 50.
It is connected to the data output terminal D _OUT 1 through the pass control transistor switch 404b.
and data input terminal via inverter 50f.
Connected to _IN 1.

In addition, the pass control transistor switch 404a
A terminal 60 is connected to the gate terminals of and 404b through an inverter 50g, respectively. A read/write control signal is applied to this terminal 60.

Further, 1-bit memory cells 40a and 40e are connected by a word line 307, and one end of the word line is connected to the output end of AND gate 51a. Similarly, 1-bit memory cells 40b and 40
f, 40c and 40g, 40d and 40h are connected by a word line 307, and one end of each word line is connected to an AND gate 51b, 5
It is connected to the output terminals of 1c and 51d. Here, for a combination of logical values of two address signals input to address signal input terminals A0 and A1, one of AND gates 51a to 51d is selected.
So that the output of the AND gate is high level,
Address decoder 41 is configured. Therefore, a high level signal is derived to one of the word lines 307 by the address decoder 41, and a high level signal is output to one of the word lines 307 connected to that address line.
A bit memory cell is selected. That is, when the word line 307 goes high, the pass gate switches 402a and 402d shown in FIG.
is turned on, and the holding terminal of this memory cell is connected to bit lines 306a and 306b via data terminals 406a and 406b.
The pass gate switches 402a and 402d of the other 1-bit memory cells are turned off, and the bistable circuits and bit lines of these memory cells are electrically isolated. In this way, the structure is such that only the bistable circuit of one selected memory cell is connected to the same bit line. Therefore, the data of the selected memory cell is output to the data output terminal D _OUT 0 (or D _OUT 1) via the bit line. At this time, a high level signal is applied to the terminal 60, and by turning off the overcontrol transistor switches 404a and 404b, the bit line 306b and the inverter 50 are switched off.
e and 50f output terminals are separated from each other. When writing data, by applying a low level signal to the terminal 60, the pass control transistor switches 404a and 404b are turned on, and the input signals applied to the data input terminals D _IN 0 and D _IN 1 are transmitted to the bit line. Furthermore, it is configured to write into the selected 1-bit memory cell. With the above configuration, it is possible to read data from and write data to any memory cell.

In the above embodiment, a 2-bit x 4-word RAM was explained, but the memory capacity is
You can select any number within the number of basic cells provided.

Further, in the above-described embodiment, the case of a CMOS static random access memory has been described, but a bipolar type memory may also be used, and the same effect can be obtained even in the case of a read-only memory.

An example in the case of a read-only memory will be described below.

FIG. 9 is an example of a memory cell used in another embodiment of the invention. NMOST 602 is a memory cell that also serves as a storage device selection device. In this memory cell, whether the logic data "H" or "L" is held is determined depending on whether the gate terminal of the NMOST 602 is connected to the selection terminal 607 or the ground terminal.

FIG. 10 is a plan view showing an example in which the memory cell shown in FIG. 9 is implemented for 4 bits on the basic cell shown in FIG. 3. In the figure, on the basic cell shown in FIG.
~507d, a bit line 506 formed by the first wiring layer, and a ground line 511 formed by the first wiring layer.
Then, a wiring 309 connecting the selection terminal and the memory cell in the first wiring layer is formed. Note that the bit line 506 is wired along the direction in which the memory cells are arranged. Then, a contact hole 101 and a through hole 102 for connection are placed at predetermined positions.
is formed to constitute a 4-bit memory cell.

Figure 11 shows a ROM configured by the memory cells, basic cells, and part of the slice part shown in Figure 10.
FIG. 2 is a circuit diagram showing a circuit. In the figure, this embodiment includes two sub-memory blocks 43. Each sub-memory block is provided with memory cells 60a and 60b as shown in FIG.

According to the invention described above, the following unique effects are achieved.

Since a memory circuit can be configured in any area on a master slice type gate array chip, there is no need to prepare a dedicated memory area in advance as in the past, and the effective utilization rate of the chip can be improved. .

A plurality of bit cells are divided into sub-memory blocks of 1×N words, and each sub-memory block is arranged on the same cell column block,
Since the bit lines in each sub-memory block are arranged along the direction in which the bit cells are arranged, the wiring length of the bit lines in each sub-memory block can be kept short and constant. Therefore, the parasitic capacitance of the bit line becomes small and constant for each sub-memory block, making it possible to shorten the accelerator time of the memory circuit and stabilize performance.

As mentioned above, performance can be stabilized, so for example, memory cells configured with CMOS inverters, which operate unstable but have a smaller number of elements than flip-flops, can be used as memory cells. Can be used. Therefore, a memory circuit with a small number of elements can be realized.

[Brief explanation of the drawing]

Figure 1 shows a conventional gate array with a built-in memory circuit.
1 is a diagram showing an example of the configuration of an LSI chip. FIG. 2 is a diagram showing a master chip configuration of a gate array LSI to which this embodiment is applied. FIG. 3 is a plan view of a basic cell grounded on the master chip of FIG. Figure 4 shows the basic cell shown in Figure 3 with the line -
FIG. FIG. 5 is a sectional view of the basic cell shown in FIG. 3 taken along the line -.
FIG. 6 is a circuit diagram of a memory cell used in this embodiment. FIG. 7 is a plan view showing the configuration of a memory cell in which the memory cell circuit shown in FIG. 6 is realized using a part of the sliced portion on the basic cell shown in FIG. 3. FIG. 8 is a circuit diagram showing an example of a memory device constructed using the memory cells, basic cells, and part of the slice portion shown in FIG. 7. FIG. 9 is a circuit diagram of a memory cell of a read-only memory used in another embodiment of this invention. FIG. 10 is a plan view of a memory cell in which four words of the memory circuit shown in FIG. 9 are implemented on the basic cell shown in FIG. 3. FIG. 11 is a circuit diagram of a memory device constructed using the memory cells, basic cells, and part of the slice portion of FIG. 10. In the figure, 1 is a gate array LSI chip, 2 is a gate array LSI chip,
is a memory dedicated area, 3 is an internal gate area, 4 is a buffer area, 5 is a wiring area, 6 is a field insulating film, 7 is a first interlayer insulating film, 8 is a gate insulating film,
9 is a P-type semiconductor substrate, 11 is a gate array chip, 30 is a cell row block, and 40a to 40h are 1
bit memory cell, 41 address decoder, 4
2 is a sub memory block, 50a to 50g are inverter circuits, 51a to 51d are AND gates, 1
01 is a contact hole, 102 is a through hole, 301a to 301d are polysilicon layers forming the gate of PMOST, and 302a to 302d are
The polysilicon layer that constitutes the gate of NMOST,
303a to 303e are P-type diffusion regions that constitute the source and drain of PMOST, and 304a to 304e are P-type diffusion regions that constitute the source and drain of PMOST.
305 is an N-well diffusion region, 306a and 306b are bit lines, 307 is a word line, 310 is a power supply line, 311 is a ground line,
506 is a bit line, 507a to 507d are selection lines, and 511 is a ground line.

Claims (1)

[Claims] 1. Using a plurality of the basic cells on a gate array chip having a structure in which a plurality of cell row blocks are arranged in multiple stages, each consisting of a plurality of basic cells arranged on a semiconductor substrate and each consisting of a plurality of transistors. A memory circuit having a plurality of memory cells, an input/output control circuit, and a selection circuit for selecting a required number of the memory cells is formed, and the plurality of memory cells are 1 bit×N words (N is 2 or more). Each of the sub-memory blocks is constructed within the same cell column block, and the bit line for exchanging data between the memory cells within the memory cell is 1. A semiconductor integrated circuit device characterized in that the semiconductor integrated circuit device is formed along the arrangement direction. 2. The semiconductor integrated circuit device according to claim 1, wherein the sub-memory block includes: N memory cells and an input/output circuit. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the bit line is formed within a region of the cell column block. 4. The semiconductor integrated circuit device according to any one of claims 1 to 3, wherein the wiring patterns in each of the sub-memory blocks have the same pattern shape.