JPH0747869Y2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor memory device having an improved wiring structure to improve the degree of integration.

In recent years, the degree of integration of semiconductor memory devices has improved more and more, but the demand is still high. The present invention aims to improve the degree of integration by improving the layout of wirings for supplying power supply voltage and signals in a semiconductor device having circuit units arranged in a matrix, for example, static type. The present invention relates to an improvement in the arrangement of ground lines in a semiconductor memory device.

[Conventional technology]

FIG. 1 is a block diagram showing a main part of a static semiconductor memory device adopting the wiring structure disclosed in “Semiconductor Memory Device” filed by the applicant on the same day as the utility model registration application. In FIG. 1, static memory cells MC ₁₁ , MC ₁₂ , ... Are arranged in a matrix, and memory cells MC ₁₁ , MC ₂₁ , MC ₃₁ ,.
₁₂ , MC ₂₂ , MC ₃₂ , ..., respectively have bit line pairs BL ₁ and ▲
▼, BL ₂ and ▲ ▼, BL ₃ and ▲ ▼, ... Are connected. Conventionally, the ground line is formed of the same conductive layer as the bit line pair, and is arranged so as to run between the bit line pairs in the same direction as the bit line pair. forming a conductive layer different from the bit line to the ground line as indicated in the "semiconductor memory device", by which a laminated structure, as shown in FIG. 1, the ground line GND _1, G
It has become possible to arrange ND ₂ , ... so as to run in the direction orthogonal to the bit line. The ground line GND ₁ is connected to the memory cells MC ₁₁ , MC ₁₂ , ... In the row direction at nodes N ₁₁ , N ₁₂ ,. The ground lines GND ₂ , GND ₃ , ... Are similarly connected to the memory cells in each row direction. Ground wire GND ₁ , G
When ND ₂ , ... Is formed of a relatively high resistance conductive layer such as polysilicon, it is necessary to short the ground line with a relatively low resistance conductive layer such as aluminum to compensate for the increase in the resistance value of the ground line. Occurs. In FIG. ₁ , the short-circuit wirings SL ₁ , SL ₂ , ... Formed of the same conductive layer as the bit lines are parallel to the bit lines at a predetermined interval (an interval for three memory cells in the drawing).
, And wiring SL ₁ is ground line GND ₁ , GND ₂ , G
ND ₃ , ... Are connected to nodes N ₁₁ , N ₂₁ , N ₃₁ , ..., respectively, and the wiring SL ₂ is connected to ground lines GND ₁ , GND ₂ , GND ₃ , ... To nodes N ₁₂ , N ₂₂ , N ₃₂ ,. ... are connected to each other.

[Problems to be solved by the invention]

Conventionally, a special space SP is provided between the memory cells for arranging the short-circuit wirings SL ₁ , SL ₂ , ..., Due to the existence of the special space SP, the static semiconductor memory device is integrated. There was a limit to the degree of improvement.

In view of the problems associated with the arrangement of the ground lines and the short-circuiting lines between the ground lines in the above-mentioned "semiconductor memory device" proposed by the present applicant, the object of the present invention is to provide a semiconductor memory including circuit units arranged in a matrix. In the device, by arranging the relatively low resistance second wiring orthogonal to the relatively high resistance first wiring so as to run inside the circuit unit, the space between the circuit units is reduced and integrated. It is to improve the degree.

[Means for solving problems]

In order to achieve the above object, the present invention provides a memory cell matrix composed of a plurality of static memory cells, arranged in each column in the memory cell matrix, and extending in the column direction. Are arranged for each row in the memory cell matrix, and each bit line connected to each static memory cell in that column is extended in the row direction. A ground line connected to the bit line and a ground line formed in a layer different from that of the bit line are arranged in the same layer as the bit line at a ratio of one to a plurality of columns in the memory cell matrix and extend in the column direction. And a wire for short-circuiting between ground lines that intersects the ground line, the ground line is formed of the same material as the gate electrode in the same layer as the gate electrode that constitutes the memory cell, and the bit line and The wiring for short-circuiting between ground lines is made of a material having a resistance lower than that of the ground line, and the wiring for connecting the ground lines is arranged so as to pass over the elements constituting the static memory cell. The semiconductor memory device is characterized in that the two are interconnected at the intersection with the short-circuiting line to reduce the substantial resistance value of the ground line.

The circuit unit is a static memory cell, the first wiring is a ground line made of polysilicon,
The second wiring is preferably a grounding wire short-circuiting wiring made of aluminum.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of essential parts of a static semiconductor memory device according to an embodiment of the present invention. First in FIG.
The difference from the figure is that the wiring lines for short-circuiting between ground lines SL ₁ , SL ₂ , ...
, SL ₁ ′, SL ₂ ′, ... Are provided, and no special space is provided between the memory cells for the wiring SL ₁ ′, SL ₂ ′,. Is. The wirings for short-circuiting between ground lines SL ₁ ′, SL ₂ ′, ... Have memory cells MC ₁₃ , MC ₂₃ , MC ₃₃ , MC ₃₃ , MC ₂₃ , MC ₃₃ , parallel to the bit lines with a predetermined interval (an interval for three memory cells in the figure). …, MC ₁₆ , MC ₂₆ , MC ₃₆ ,
It is arranged so that it runs in the center of. As shown in FIG. 1, since there is no special space SP, the required area of the device can be reduced and high integration can be achieved.
Especially when the memory capacity is large, the effect is great.

FIG. 3 is an equivalent circuit diagram of MC ₁₃ , which is one of the memory cells shown in FIG. In FIG. 3, memory selection MOS
The word line WL is commonly connected to the gates of the transistors Q ₁ and Q ₂ , and the bit lines BL and ▲ ▼ are connected to the drains (or sources) of these transistors, respectively. The drains of the MO transistors Q ₃ and Q ₄ and the sources (or drains) of the transistors Q ₁ and Q _{2 which} are cross-coupled to form a flip-flop are connected to nodes N ₁ and N ₂ , respectively.
Are connected in. The nodes N ₁ and N ₂ are connected to the power supply line V _cc via load resistors R ₁ and R ₂ , respectively. Commonly connected to the source ground line GND ₁ of the transistors Q ₃ and Q ₄ . Wiring SL for short-circuiting between ground lines provided in this embodiment
₁ 'is connected to the ground line GND ₁ at node N _13.

FIG. 4 is a plan view showing the structure of the memory cell MC ₁₃ shown in FIG. In FIG. 4, on the semiconductor substrate SUB,
The gate electrode wirings G ₃ and G ₄ of the transistors Q ₃ and Q ₄ are formed of a polysilicon wiring layer and are arranged so as to run parallel to the row direction. A word line W also formed of a polysilicon wiring layer in parallel with G ₃ and G _4.
L, ground line GND ₁ , and power supply line V _cc are arranged. W
Bit line pair BL ₃ and ▲ formed of an aluminum wiring layer via an insulating layer on L, GND ₁ , V _cc , G ₃ and G ₄
▼ and the ground line short-circuit wiring SL ₁ ′ are arranged so as to run in the column direction. Ground wire GND ₁ and ground wire short-circuit wiring SL
Are short-circuited via the contact portion indicated by the node N ₁₃ and ₁ '. As shown in the above-mentioned “Semiconductor Memory Device” proposed by the applicant, the ground line GND ₁ is formed in a conductive layer different from that of the bit line pair so as to run in the direction orthogonal to the bit line pair. The density is low, and it has become possible to run the ground line short-circuit wiring SL ₁ ′ between the bit line pair BL ₃ and ▲ ▼.

The present invention is not limited to the static semiconductor memory device described above, and various modifications are possible. In general,
In a semiconductor device including a first wiring having a relatively high resistance for supplying a power supply voltage or a signal to circuit units arranged in a matrix and a second wiring having a relatively low resistance orthogonal to the first wiring, The effect of the present invention is achieved by running the wiring of (1) inside the circuit unit.

[Effect of device]

As described above, according to the present invention, particularly in the static type semiconductor memory device, by arranging the wiring for shorting between ground lines so as to run inside the memory cell, a special wiring for shorting between ground lines is provided. No space is required, and the degree of integration can be greatly improved.

Of course, also in a general semiconductor device, it is possible to improve the degree of integration by running the wiring inside the circuit unit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a static semiconductor memory device adopting the wiring structure disclosed in “Semiconductor Memory Device” filed by the applicant on the same day as this application for utility model registration, and FIG. FIG. 3 is a block diagram showing a main part of a static semiconductor memory device according to an embodiment of the present invention. FIG. 3 is an equivalent circuit diagram of MC ₁₃ , which is one of the memory cells shown in FIG. FIG. ₁₄ is a plan view showing the structure of the shown memory cell MC ₁₃ . GND ₁ , GND ₂ , GND ₃ …… Ground wire, BL ₁ , ▲ ▼, BL ₂ , ▲
▼ …… Bit line pair, SL ₁ ′, SL ₂ ′ ... Ground wire short-circuit wiring, N ₁₃ , N ₂₃ , ..., N ₁₆ , N ₂₆ …… Ground wire and ground wire short-circuit wiring contact part .

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 27/04 27/10 471 27/11 H01L 21/88 Z (56) References JP-A-53 -14586 (JP, A) JP-A-56-161668 (JP, A) JP-A-53-148398 (JP, A) Actual development Sho-55-75900 (JP, U)

Claims (2)

[Scope of utility model registration request] 1. A memory cell matrix composed of a plurality of static memory cells, arranged in each column in the memory cell matrix, and extending in the column direction, and connected to each static memory cell in the column. A plurality of bit lines arranged in each row in the memory cell matrix, extending in the row direction, connected to each static memory type memory cell in the row, and in a layer different from the bit line. And a ground line formed in the same layer as the bit line at a ratio of one for a plurality of columns in the memory cell matrix, each extending in the column direction and intersecting the ground line. And a wiring for short-circuiting between the ground lines, the ground line is formed of the same material as the gate electrode in the same layer as the gate electrode forming the memory cell, The ground line is formed of a material having a resistance lower than that of the ground line, and the wiring for connecting the ground lines is arranged so as to pass over an element forming the static memory cell. A semiconductor memory device characterized in that the two are interconnected at the intersection with and the substantial resistance value of the ground line is lowered. 2. The semiconductor memory device according to claim 1, wherein the ground line is made of polysilicon, and the short-circuit wiring between ground lines is made of aluminum.