JPS58160989A - Liquid crystal drive circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a liquid crystal driving circuit Kll for driving a multi-grain liquid crystal display panel.

Currently, liquid crystal display boards are used as displays in many devices. Normally, the liquid crystal display board is contacted with the printed circuit board on which the drive circuit is mounted through a conductive pommel by applying pressure, so it is easy to check whether or not the contact is complete. As a means to do this, the device is required to have a function of lighting all segments of the liquid crystal display panel.

Furthermore, in digital watches that generally employ a liquid crystal display board as a display, the liquid crystal drive output is often monitored to finely adjust the oscillation frequency of the oscillation circuit that determines the precision of the watch.

In this case, a function is required to statically drive all segments of the liquid crystal display panel and output a signal to turn them on or off.

FIG. 1 is a circuit diagram showing a conventional drive circuit that has the function of lighting all segments of a liquid crystal display panel.

In FIG. 1, reference numeral 1 denotes a segment drive circuit for causing a liquid crystal display panel to perform normal display.

9. 2 is a segment/gate drive waveform input capable of lighting all segments, and is applied to one input terminal of NAND f-)4. A control signal human power 3 is applied to the other input terminal of the Nando Dart 4.

The output of the Nandt gate 4 is applied to one input terminal of each of the Nandt gates 6 and 8°10. In addition, the above control signal human power 3
is applied through an inverter 11 to one input terminal of each of NAND v-)5 and 7.9. The output of the segment drive circuit 1 is applied to the other input terminal of the NAND P-) 5, 7.9. Nando P
The output of -)5°7.9 is applied to the other input terminal of Nandogoo)6, 8.10.

In FIG. 1, when performing a normal display, the control signal input is rOJ, and therefore the NAND f-to-4
The output of the segment drive circuit 1 is prohibited, and the segment drive circuits output from the segment drive circuit 1 are the Nant gates 5, 6, 7, and 8.
Through 9 and 10, segment signal output terminals S, ~Sn
is output to.

In addition, when lighting all segments of the liquid crystal display board, the control signal 3 becomes ``1'', and this control signal 3
is passed through the inverter 11/r-)5, 7.9...
・Prohibit the output of. In addition, segment drive waveform human power 2
is outputted to segment signal output terminals 8I-8n via NANDs 4 and 6, 4 and 8, and 4 and 10.

Although all the segments of the liquid crystal display board can be lit by the liquid crystal drive circuit as shown in FIG. and 10, and also
The number of wires also increases. %, such a liquid crystal drive circuit is
When implementing SI, an increase in chip area is unavoidable.

This invention aims to eliminate the above-mentioned conventional drawbacks.

This technology allows all segments of a liquid crystal display board to be turned on or off without a significant increase in the number of elements and wiring, and has a static drive function. The purpose is to provide an effective liquid crystal driving path.

Embodiments of the liquid crystal drive circuit of the present invention will be described below with reference to the drawings. FIG. 2 is a circuit diagram of one embodiment. FIG. 2 shows an example of application to a drive circuit for an h-duty multiplex liquid crystal display panel.

In FIG. 2, CPIN is a clock pulse input terminal. This clock pulse input terminal CPIN is connected to the input terminal of a T flip-flop 12 (hereinafter referred to as TFF) 12, and also to an input terminal of an or-dart 14. It is connected to each first input terminal of ANDP-115, and is further connected to the first input terminal of ORP-17 via an inverter 13, and the first input terminal of A/Y? - to the first input terminals of ports 16, respectively.

Also, ON is the control signal input terminal, and the above OR P-)
14.17 and is connected to the second input terminal of 14.
and r-) 15.16.

The output of the above TFF12 is the common signal generation circuit 20゜21
The signal is sent to the input terminals (1) and 19 of the exclusive OR (P-) 19. The outputs of OR (r-) 14 and 17 are input to the input terminals I and 21 of the common signal generation circuits 20 and 21, respectively.

The output of the exclusive OR P-) 19 is the output of the exclusive OR P-) of each of the seven drive circuits 26 to 28.
The signal is transferred to the first input terminal of No. 25. Since the segment drive circuits 26 to 28 each have the same circuit configuration, FIG. 2 shows the internal configuration of the segment drive circuit 28 as a representative.

The segment drive circuit 28 is an exclusive Noah r-
) 25, andP-)22.23 and Noah r-)2
It is composed of 4 and K. Each segment drive circuit 26
~28 ANDP −) The first input terminal of 22 is ANDf
-) Connected to output 15 and 17 Y? ”-123
A first input of is connected to an output of ANDR 16.

ANDr-) of segment drive circuit 28.26.28
Segment signal input terminals 5IG-1, 5IG-2, and 5IGI-N are connected to the second input terminals of 22, respectively. Similarly, segment drive circuits 28, 26 .
27 and r -) 23 has segment signal input terminals 5IG2-1, 5IG2-2゜5IG2-N, respectively.
is connected.

These segment signal input terminals 5IGI-1゜5IG
Segment signals before multiplexing are input to I-2, 5IGI-N, 5IG2-1, 5IG2-2, and 8IG2-N, respectively.

Each segment drive circuit 28.26.2707y r-)
22. The output terminals of 23 are respectively connected to the first node of node 24.
The input terminal is connected to the second input terminal. This Noah r-
The output end of the gate 24 is connected to the output end of the exclusive gate 25.

The output end of this exclusive node P-) 25 is connected to the segment signal output terminal 5EGI.

Similarly, the output terminals of the exclusive nodes P-) of the segment drive circuits 26 and 27 are also connected to the segment signal output terminals 5FG2 and 8EGN.

Further, each output terminal of the common signal generating circuit 20.21 is connected to common signal output terminals COMI and C0M2. This common signal output terminal COMI.

The common signal obtained at C0M2 and the segment output signals from the segment signal output terminals 8EG1, 5EG2, and 8EGN are respectively applied to a liquid crystal display board (not shown).

Next, the operation of the liquid crystal drive circuit of the present invention configured as described above will be explained with reference to FIG. 3 and subsequent figures. When a clock pulse CPI (FIG. 4(a)) with a middle frequency of n is input to the clock pulse input terminal CPIN, this clock pulse CPI is input to the TFF 12 and at the same time is input to the first input terminal of the ORP 14. ,and? -)15
It is inputted to the first input terminal of 17, and is further inverted at 13, and input to the '1st input terminal of ORr-) 17, and P
-) is also input to the first input terminal of 16.

By inputting the clock pulse CPI to the TFF 12, this clock pulse CPI is frequency-divided by two, and becomes a lock pulse CP2 having a frequency η as shown in FIG. 4(b).

When performing normal display, rOJ is input to the control signal input terminal ON, and the input terminal I of the common signal generation circuit 20
The clock pulse CP2 from the TFF 12 is input to the input terminal I, and the clock pulse CPI is input to the input terminal I through the OR (r-)14.
Clock pulse CP2 is also input to the 10 input terminal I,
The clock pulse CPI inverted by the inverter 13 is inputted to the input terminal I through the ORP 17. This common signal generating circuit 20.21 operates as shown in FIG. Common output signals as shown in FIG. 4(C) and FIG. 4(d) are obtained from COMI and CMO2, respectively.

In Fig. 3, "0" and "1" of I, , and I represent the logic level of the input, "0" of OUT and "vD"
D” represents the voltage of the output signal, and % VD
It represents the intermediate voltage between rjir OJ and rv.

In addition, segment signal input terminals S I GH, S I G
The segment signal input to 2-1 is ANDP-)22
At ゜23, the clock pulse CPI and its inverted clock pulse CPI are ANDed, and the NOR r -
) 24 years ago, this Noah P-)
The output of 24 is applied to the second input of exclusive node r-) 25.

Since the output of the exclusive or dart 19 is input to the first input terminal of the exclusive or dart 25, the output whose phase has been changed so that an alternating electric field is applied to the liquid crystal display panel is sent to the segment signal output terminal 5EG. (Fig. 4(-)) is output as a segment output signal.

The segment drive circuits 26 and 27 input signals to the segment signal input terminals 5IGI-2 and 5IG2-1 in the same manner as the input signals to the segment signal input terminals 5IGI-1 and 5IG2-1.
The input signals to 2.8IG1-N and 5IG2-N are multiplexed, and the phases of the multiplexed signals are changed so that an alternating electric field is applied to the liquid crystal display panel, and the signals are output to the segment signal output terminals 5F3G2.5KGNK, respectively. Segment output signals as shown in FIG. 4(f) and FIG. 4- are sent out.

Note that rOJ and rlJ of the clock pulses CPI and CP2 shown in FIGS. 4(a) and 4(b) indicate logic levels, and the common signals shown in FIGS. 4(C) and 4(d),
The voltages of the segment output signals r OJ , rVl) DJ + r HVpDM of the segment output signals shown in FIG. 4 1e) to FIG. 4(g) are represented.

In addition, segment/to signal input terminals 5IG1-1, 5IG2
-1,5IGI-2,5IG2-2,5IGI-N,5
The signals input to IG2-N are rlJ and rOJ, respectively.
, rOJ.

rlJ, rlJ, rlJ.

Next, a case will be described in which all segments of the liquid crystal display panel are lit. In this case, the control signal input terminal ON is set to “1”.
" is input. Therefore, andP−)15.16
Both output lines are "0", and ANDP-)22
, 23 also becomes "0". For this reason, Noah P-)
24 output, tsumashi, exclusive Noah f-) 2
The second input terminal of 5 becomes "1".

Also, the clock pulse input terminal CPIN is connected to the clock pulse input terminal CPIN as shown in FIG.
), the lock pulse CPI is input and T
Added to FF12. As a result, the clock pulse CP1a is frequency-divided by TFF12 in the same way as in the ninth case described above, and a lock pulse CP2 appears at its output terminal as shown in FIG. 5(b).

Jin's clock pulse CP2 is exclusive or r-
) 19 to Excl.
Transferred to the input terminal. This is exclusive! A normal clock pulse CP2 is output from the node 25. Similarly, the other segment drive circuits 26 and 27 output a high p-sku pulse CP2. After a while,
Segment signal input terminal 8KG1.8EG2,5EGN
The front segment output signals appear as shown in FIG. 5(.)K, respectively.

9, the TFF 120 output terminal crossing pulse CP2 is applied to each terminal 11 of the common signal generating circuit 20, 21, and the input terminal of the common signal generating circuit 2o is the common signal C.
PI is added to the input terminal 1. of the common signal generation circuit 21.
In this case, the clock pulse CPI is inverted or the four clock pulse C
PI is input.

Therefore, the output of 14.17 gives
Input terminal I of common signal generation circuit 20.21! is always “1”
”, the common signal is “0” and “vDD” according to Figure 3.
'', a common signal as shown in FIG. 5 1e) and FIG. 5(d) is obtained, and all segments of the liquid crystal display panel are illuminated by static driving.

Note that in FIG. 5, as in FIG. 4, r OJ and rlJ of one clock pulse CPI and CF2 represent logic levels, and common signals COMI and C0M2, and rOJ and r of segment output signals 5EGI, 5EG2, and 5EGN,
VDD' represents the voltage.

The above has been explained using an example in which all segments of the liquid crystal display board are turned on by static driving, but when turning off all segments, an exclusive or r-) 190
), the clock pulse CP2 is inverted by an inverter to generate nine clock pulses CP2
) The circuit is configured so as to be applied to the first input terminal of 25.

Ninth, if you don't need static drive.

Remove or dirt 14 and 17 and common signal generation circuit 2
The circuit configuration may be such that the clock pulse CPI is input to the 0 input terminal, and the 9 clock pulse CPI, which is an inversion of the clock pulse CPI, is input to the input terminal of the common signal generation circuit 21.

As explained above, the segment drive circuit 28 itself that provides segment signals is exactly the same as one without the function of lighting all segments of the liquid crystal display panel. and rounding AND/GO 1 circuits 15, 16 for inhibiting the output of the multiplex circuit composed of AND r-) 22, 23 and NOR r-) 24 in the segment drive circuit 28;
Exclusive OR for switching the phase control signal input to the inverter 18C) &'-) and the exclusive OR for changing the phase of the multiplexed signal so that an alternating electric field is applied to the liquid crystal display panel P-) 25 f-) Desired functions can be increased just by adding 1G.

Therefore, for each of the seven segment drive circuits,
&'-) is not required and there is no need for additional wiring diagrams. There is an advantage that the liquid crystal display panel can be statically driven by adding the rounded gates 14 and 17 which simultaneously make the output of the common signal generation circuit swing between "0" and "vDD".

As described above, 1. According to the liquid crystal drive circuit of the present invention, during normal lighting of the liquid crystal display lamp, segment input signals are input to the segment drive circuit and multiplexed, and the phase of the signal is V multiplexed in correspondence with the clock pulse. When the LCD panel is fully lit, multiplexing of the segment input signal in the segment drive circuit is prohibited, and a signal corresponding to the clock pulse is output from the segment drive circuit. As a result, it is possible to turn on or off all the LED lights on the liquid crystal display board without significantly increasing the number of elements and wiring, and this makes it possible to turn on or off all the lights on the liquid crystal display board, making it easy to use when integrated into an LSI. This is particularly effective.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional liquid crystal drive circuit, FIG. 2 is a circuit diagram showing an embodiment of the liquid crystal drive circuit of the present invention, and FIG. Figures 4 (1) to 5 (-) and 5 (1) to 5 (•), which show the relationship between outputs in a table, are used to explain the operation of the liquid crystal drive circuit of the present invention, respectively. FIG. 12...T flip-flop circuit, 13.18...
・Inverter, 14.17-... Noah r-), 15゜1
6.22.23...and f-), 19...excluse 1 nort, 20, 21...common signal generation circuit, 24...norr-), 25...exclude Scrooge 1 Noah r-), 26-2B...Segment drive circuit. Patent Applicant Oki Electric Industry Co., Ltd. Figure 3 Figure 4 Figure 5 Procedural Amendment September-3, 1981 Commissioner of the Patent Office! I, No. 11, No. 1, Incident Display, Showa Doorma, Tatami Permit No. 1198, 2, 弗-0
4th person yakusho g*■step 3, relationship with the person making the amendment Case: Applicant (O atmosphere) Kami Electric Co., Ltd. Kinsha 4, Agent 5, Date of amendment order Showa year, month, day (1) Member) 6. Subject of amendment 7. Contents of amendment 1) "2I!! #Claims" in the specification will be corrected as shown in the attached sheet. 2) On page 2 of the specification, line 12, "Meno" is corrected to "Mini". 3) On page 3, line 15, "input ga" is corrected to "input 3". 4) On page 3, line 17, "segment" is corrected to "segment". 5) rsnjt r on page 3, line 19, page 4, line 6, and line 9, respectively.
Correct it to sNJ. 6) Delete "0." on page 4, line 3. 7) Delete "12" on page 5, line 9. 8) On page 5, line 15, correct it to read "No.6 2J" tr.6 2nd. 9) On the last line of page 5, correct "sent to input terminal 1 of" to "sent to each input terminal 11 of". 10) On page 6, line 1, ``to do'' is corrected to ``to be''. 11) On page 6, line 3, "input end" is corrected to "each input end." 12) Same page 6 line 19 r28.26.28J as “28°2
Corrected to 6.27J. 13) Same page 7 line 1 r8IG-1, 8IQ-2J tr8
Corrected to IG1-1.5IGI-kl. 14) On page 7, line 3, "for 23" has been corrected to "for the second input terminal of 23." 15) On page 7, line 8, correct it to read "Ni Jtr wa." 1g) On page 7, line 14, "output terminal" is corrected to "second input terminal". 17) Same page 7 line 19 r 5FGZ J [5KG2J
I am corrected. 18) On page 8, line 6, ``It appears as if you can see it.'' is corrected to ``You can see it.'' 19)lii page 19 line 11 rcMO2J [C0M2
Correct it as j. 20) Same page 9, line 17 ““vDD’s” is “vDD’s”
I am corrected. 21) On page 9, line 18, r8IGHJ is corrected to r8IG1-IJ. 22) Same page 10, line 9 r8EG (Fig. 4 (・))'' to 1'
Corrected to -3EGLJ. 23) On page 10, line 10, ``as a signal'' is corrected to ``as a signal (Figure 4 (-))''. 24) Correct the following on page 12, line 2, r 1/2 J tr 2 J. 25) Page 12, lines 16 to 19 [added...
... has been input. '' is added. Also, since the second input terminal of OR'r-) 14.17 is connected to the control signal input terminal ON, "1" is input. ” he corrected. 26) lii page 113 line 16 (-#al'-) J t
r Noah Gate,” he corrected. 27) Delete "Circuit" on page 14, line 10. 28) Delete “no r-to” on page 14, line 11. ・29)
On page 14, line 14, "Signal switching" is corrected to "Signal switching." 30) On page 14, line 18, "Wiring diagram" is corrected to "Number of wires." 31) On the last line of page 14, "Noah" is corrected to "Or". 32) On page 15, line 4, “indicator light” is corrected to “display board.” 33) Page 10, line 9 “Suru no kai” t – “Suru no t”
I am corrected. 34) ljllB page 12 and 13 “As you do”
Delete. 35) Delete "Circuit" on page 16, line 5. 36) Fj page 16, line 6, “Noah” is corrected to “or”. 2. Scope of claims 1! - ment input signal fq multiplexer 1yu
A segment drive circuit that supplies the i+ display board, a common signal generation circuit that receives the clock/yars and supplies common signals to the liquid crystal display board according to the normal lighting and all segment lighting of the liquid crystal display board, and the normal lighting mentioned above. At the same time, the above segment input signal is used in the segment drive circuit! A circuit that multiplexes matJII in the segment drive circuit during full lighting, and a circuit that multiplexes matJII in the segment drive circuit during normal lighting. A liquid crystal drive circuit comprising a circuit that outputs a signal from the drive circuit and outputs a signal corresponding to the clock pulse from the segment drive circuit when all lights are on.

Claims (1)

[Claims] a segment drive circuit that multiplexes segment input signals of a liquid crystal display board; a common signal generation circuit that receives clock pulses and supplies common signals to the liquid crystal display board according to when the liquid crystal display board is normally lit and when all segments are lit; A circuit that multiplexes the segment input signal in the segment drive circuit during normal lighting and inhibits the function of multiplexing in the segment drive circuit during full lighting, and a circuit that changes the phase of the multiplexed signal in the segment drive circuit during normal lighting. A liquid crystal drive circuit comprising a circuit for causing a segment drive circuit to output an alternating electric field so as to apply an alternating electric field to a liquid crystal display board, and for outputting a signal corresponding to the clock pulse from the segment drive circuit when all lights are on.