JPS58159393A - Method of producing semiconductor device - Google Patents

Method of producing semiconductor device

Info

Publication number
JPS58159393A
JPS58159393A JP4317482A JP4317482A JPS58159393A JP S58159393 A JPS58159393 A JP S58159393A JP 4317482 A JP4317482 A JP 4317482A JP 4317482 A JP4317482 A JP 4317482A JP S58159393 A JPS58159393 A JP S58159393A
Authority
JP
Japan
Prior art keywords
substrate
resin
temperature
board
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4317482A
Other languages
Japanese (ja)
Inventor
長島 健二
博 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP4317482A priority Critical patent/JPS58159393A/en
Publication of JPS58159393A publication Critical patent/JPS58159393A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、へイブリッド集積回路等の基板の反りを矯
正できる半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device that can correct warpage of a substrate such as a hybrid integrated circuit.

〔発明の技術的背景〕[Technical background of the invention]

一般に、ハイブリッド集積回路等の半導体装置は、第1
図に示すようにアルミニウム等の金属板10表面りにア
ルミナ(Aj、 0. )nのセラミックrvg xを
溶射で形成してなる基板1を有している。この基板3の
表dikに回路構成1必要な4体1−4および抵抗体5
などを溶射または印Il)技術で形成する。
Generally, a semiconductor device such as a hybrid integrated circuit has a first
As shown in the figure, it has a substrate 1 in which alumina (Aj, 0.)n ceramic RVG x is formed by thermal spraying on the surface of a metal plate 10 made of aluminum or the like. In the table dik of this board 3, the circuit configuration 1 requires four bodies 1-4 and a resistor 5.
etc. are formed by thermal spraying or by Il) technology.

を記のような基板3は、成体的にはまず金属板1の表面
をナンVプツストまたは化学エツチングで、例えば蹟大
20〜30μ乳の凹凸になる様に机面化する。そして、
この金属板1の表面Eにセラミックー2を溶射(デツズ
マ溶射)で形成−「る。この場合、セツミック層2には
連結した空孔が形成される。この空孔が存在すると、湿
気を吸入した場合に金属板1およびセツミック層2七に
形成される導体層4間の絶縁性が低下する不都合がある
To prepare the substrate 3 as described above, first, the surface of the metal plate 1 is made into a rough surface with a roughness of, for example, 20 to 30 .mu.m, by printing or chemical etching. and,
A ceramic layer 2 is formed on the surface E of the metal plate 1 by thermal spraying (Detsuma thermal spraying). In this case, connected pores are formed in the ceramic layer 2. When these pores exist, moisture is absorbed. In this case, there is a disadvantage that the insulation between the conductor layer 4 formed on the metal plate 1 and the static layer 27 is reduced.

このような不都合を解消するために、基板1全体を気密
封止して湿気が入らない様にすることが考えられるが、
気密封止の技術は回磁であり、韓遣コストも増大するこ
とになる、そのため、通虜はJ:、紀セラミック層2の
空孔に樹脂を詮漬する方法が行なわれている。この方法
では、熱硬化性樹脂を含浸し、例えば200cfi度の
温度で樹脂を硬化させる。このようなセラミック層2を
有する基板s上に、上記のように導体層4および抵抗体
5が形成され、さらに襖2図に示すようにノ譬ワードラ
ンジスタロ4がIIX IJ Itけられる。この場合
、ノ臂ワードランジスタロは、放熱用の@fロック1を
介して導体層441に半田付は等で固定される。
In order to eliminate this inconvenience, it is possible to hermetically seal the entire board 1 to prevent moisture from entering.
The hermetic sealing technique is magnetization, which increases the cost of shipping to Korea.Therefore, the method used by connoisseurs is to soak resin into the pores of the ceramic layer 2. In this method, a thermosetting resin is impregnated and the resin is cured at a temperature of, for example, 200 cfi degrees. On the substrate s having such a ceramic layer 2, the conductor layer 4 and the resistor 5 are formed as described above, and furthermore, as shown in FIG. In this case, the arm word transistor is fixed to the conductor layer 441 by soldering or the like via the @f lock 1 for heat radiation.

〔背景技術の問題点〕[Problems with background technology]

ところで、上記のような基板1の様に一般的C;熱膨張
率の異る214類の11質a@*a電からなる場合(#
43図(A))、この2檀類の@貞を結合させたときの
温度を基準にして、第3図IB) I=示すように温度
がt昇すれば熱膨張率の大きい方1□を外側にして反り
、逆に@3図1c)に示すように温度が低下すれば熱膨
張率の小さい方amを外側にして反る樺になる。このよ
うにして、と紀基板1に反りが生じると、例えば嘱4図
体)に示すように1&1を放熱板1に収り付けた場合、
発熱した熱が効率よ(放熱板Iに伝辱しな悪影*V及ぼ
すことになる。@4図−)に示すように基板1が反って
いても、放熱板1に取り付けた際、基板1がネジ−止め
等の圧力でフラットになる場合は、放熱効果のEではそ
れほど問題にならないが、基板j自体に無通な負荷が加
わる不都合がある。また、室温で基板1自体がフラット
であれば、放熱板1への取付は後の温に菱化はそれほど
問題にならないが、特にj1温ctでに基板3が反って
いる場合は問題がある。
By the way, when the substrate 1 as mentioned above is made of general C;
Figure 43 (A)), based on the temperature when these two types of @te are combined, Figure 3 IB) I = As shown, if the temperature increases by t, the one with the larger coefficient of thermal expansion 1□ On the other hand, as shown in @3 Figure 1c), if the temperature decreases, birch will warp with am, which has a smaller coefficient of thermal expansion, on the outside. In this way, if the board 1 warps, for example, when 1 & 1 are placed on the heat sink 1 as shown in Figure 4),
Even if the board 1 is warped as shown in Fig. 4, the heat dissipated from the heat sink will cause a negative impact on the heat sink I. If 1 is flattened by the pressure of screwing, etc., this is not a big problem in terms of the heat dissipation effect E, but there is a problem in that an unnecessary load is applied to the board j itself. Also, if the board 1 itself is flat at room temperature, rhombus formation will not be a problem after mounting to the heat sink 1, but it will be a problem especially if the board 3 is warped at j1 temperature ct. .

このような展板Jの反りは、を記のような従来の製造工
程において、下記のような工程で発生すると考えられる
。$1に、基板1の金w4板1の表面を粗面化するナン
ドプラストの工程である。この工程では、金−板10表
面を通常アルミナ等の粒子を噴射して粗面化するもので
、この際七の表面の表面積が大きくなるので裏面どのバ
ランスのtから反ってくる。@2は、金属板1の表面に
セラミックを溶射する工程で、金+ll4fノの隠蓑が
L昇し、室温にもどった際盆−板lを内側にして基板S
が反る場合である。
It is thought that such warping of the spread plate J occurs in the following steps in the conventional manufacturing process as described below. Step 1 is a Nando Plast step to roughen the surface of the gold W4 plate 1 of the substrate 1. In this step, the surface of the gold plate 10 is roughened by spraying particles of alumina or the like, and at this time, the surface area of the surface of the metal plate 10 becomes large, so that the back surface is warped from the balance t. @2 is the process of thermal spraying ceramic on the surface of the metal plate 1, and when the gold+ll4f metal rises to L and returns to room temperature, the substrate S is placed with the tray and plate L inside.
This is the case when the material warps.

さらc、@3は、セラミック層1の空孔にSt脂な含浸
し、硬化する工程での反りである。この場合、樹脂含浸
後、室温で硬化できれば、室温での反りはなくなるが、
物理的および4気的特性な考慮すると高温で硬Cヒする
熱硬化性樹脂を便用する必要がある。したがって、温度
TI(室温より高温)で、熱膨張率α、の金tg板1お
よび熱膨張率α、(α、〉α、)の樹脂を含浸したセラ
ミック層2とが結合された基板1は、温度T、ではフラ
ットになっているが、室温dユもどすと金−板1を内側
にして反ることC二なる(嘱3図(C) ) 、。
Further c, @3 is a warpage caused in the process of impregnating St resin into the pores of the ceramic layer 1 and curing it. In this case, if the resin can be cured at room temperature after being impregnated, the warping at room temperature will disappear, but
Considering the physical and mechanical properties, it is necessary to use a thermosetting resin that hardens at high temperatures. Therefore, at temperature TI (higher temperature than room temperature), a substrate 1 in which a gold tg plate 1 with a coefficient of thermal expansion α and a ceramic layer 2 impregnated with a resin with a coefficient of thermal expansion α, (α,〉α,) are combined. It is flat at temperature T, but when returned to room temperature d, it warps with the metal plate 1 inward (Figure 3 (C)).

〔発明の目的〕[Purpose of the invention]

この発明は、k、記の事情を鑑みてなされたもので、ハ
イブリツy果槓回路尋の基板の製造工程において、基板
に生ずる反りを#実C二塙正して、安定な半導体装置を
製造できる半導体Mllの製造方法を提供することな目
的とする。
This invention was made in view of the circumstances mentioned above, and it corrects the warpage that occurs on the substrate during the manufacturing process of the hybrid circuit board, thereby producing a stable semiconductor device. An object of the present invention is to provide a method for manufacturing a semiconductor Mll that can be manufactured.

〔発明のaa*) すなわち、この発明においては、基板を構成rるセラミ
ック層の空孔1;熱硬化性樹脂を含浸し、一定の温度で
その樹脂を熱硬化させる。そして、基板な樹脂を熱硬化
させたfIAlfよりも高い温度で晩なましを行なって
、基板の反りを矯正するものである。
[aa* of the invention] That is, in the present invention, the pores 1 of the ceramic layer constituting the substrate are impregnated with a thermosetting resin, and the resin is thermosetted at a constant temperature. Then, the substrate resin is annealed at a higher temperature than fIAlf, which is a thermoset resin, to correct the warpage of the substrate.

〔銅明の実弛例〕[Example of actual failure of Tongmei]

Nu F図面を参照してこの発明の一実施例屯=ついて
説明する。l1%5図IA) 、 (B)はこの発明の
一実施ミー二1糸るハイブリッド集積回路等の基板1の
製造工程を示す図である。すなわち、この基板jを製造
するC;は、まず純アルミニウム等の金・^教(例えば
大きさが330X330−で、厚さが2.0 Am )
 1の表面をサンyブラストで20〜30μ無程度の凹
凸になる様に粗面化する。
An embodiment of the present invention will be described with reference to the drawings. Figures IA) and (B) are diagrams showing the manufacturing process of a substrate 1 such as a hybrid integrated circuit according to one embodiment of the present invention. That is, C to manufacture this substrate j is first made of gold such as pure aluminum (for example, the size is 330 x 330- and the thickness is 2.0 Am).
The surface of No. 1 is roughened by San-Y blasting so that it has an unevenness of about 20 to 30 μm.

この金IA仮1の表面1=、例えば粒径5〜bOμ乳の
アルミナ(A為0.)の粉末な溶射(デツズマ廣吋)し
てセラミック層(100〜150μ県程度の厚さ)2を
形成する(第5図囚)。さらに、基板3を100℃程度
の温度で加熱しな力tら熱硬化性樹脂(例えば三◆ガス
化学社製の商品名BT3103 )J oをセラミック
mzの空孔11に含浸し、5〜10分間程度放置する(
第5図(B) )。次に、基板3のl!I!面に残った
樹脂1゜を収り除いた後、200℃程度の温度で約1時
間加熱しt記熱硬化性樹脂10を硬化させる。
The surface 1 of this gold IA temporary 1 is coated with a ceramic layer 2 (thickness of about 100-150μ) by thermal spraying (Hiroaki Detsuma) of alumina powder (A for 0.) with a particle size of 5 to 20μ, for example. form (Figure 5 Prisoner). Further, the substrate 3 is heated to a temperature of about 100° C., and then a thermosetting resin (for example, BT3103, manufactured by Gas Kagaku Co., Ltd.) is impregnated into the pores 11 of the ceramic mz, and 5 to 10 Leave it for about a minute (
Figure 5(B)). Next, l! of board 3! I! After removing 1° of the resin remaining on the surface, heating is performed at a temperature of about 200° C. for about 1 hour to harden the thermosetting resin 10.

そして、硬化後、基板1全体を360℃程度の温度で約
5分間加熱し、その後徐々に室温まで冷却する。
After curing, the entire substrate 1 is heated at a temperature of about 360° C. for about 5 minutes, and then gradually cooled to room temperature.

このようにして、製造した基板3を例えば40X60−
の大きさに打抜いた後、olemi図に示すように基板
S上に導体4114および抵抗体5を形成して、ハイブ
リッド集積回路等を構成することができる。ところで、
上記のよう寵二基板1のセラミック層1の空孔に熱硬化
性樹脂10を含浸し、硬化させる等の工程により、通常
基板1に第6図に示すような反りa(基板3の輻67f
lに対して)が150μ馬程度で生ずる。そこで、この
発明では、上記のように樹脂10が硬化後、基板S全体
を樹脂10の熱硬化層まで冷却する工程、すなわち暁な
ましである熱処理工程により基板Jの上記のような反り
を大幅に1正できる。具体的には、矯正後の基板3のス
リ暑は30μ淋程度にまで緬少することができた。した
がって、このような反りを矯正した1uにノ譬ワートラ
ンジ^り等の回路素子す般けて、放熱板に収り付けた場
合、基板3は皓央に1a熱教と接続され、十分な放熱効
果を得ることができる。
In this way, the manufactured board 3 is, for example, 40×60-
After punching out the size, conductors 4114 and resistors 5 are formed on the substrate S as shown in the OLEM diagram to construct a hybrid integrated circuit or the like. by the way,
By impregnating the thermosetting resin 10 into the pores of the ceramic layer 1 of the second substrate 1 as described above and curing it, the substrate 1 is usually warped a (radius 67f of the substrate 3) as shown in FIG.
1) occurs at about 150 μm. Therefore, in the present invention, after the resin 10 is cured as described above, the entire substrate S is cooled down to the thermoset layer of the resin 10, that is, the heat treatment step is used to significantly reduce the above-mentioned warping of the substrate J. I can make one correct answer. Specifically, the scratchiness of the substrate 3 after straightening could be reduced to about 30 μm. Therefore, when circuit elements such as a power transition are installed in a heat sink on a 1u circuit with such warpage corrected, the board 3 is connected to the heat sink 1a at the center, and sufficient heat radiation is achieved. effect can be obtained.

ところで、を紀のような製造工程の中で71板1のべ而
Eにセラミック層2を形成して熱硬化性向1111を含
浸した後、150℃の温度で15分曲、べらに200℃
の温度で1時間加熱し樹脂を硬1ヒさせる。その後、基
板の表面tに一ペースト(例えばアサヒ化学社製の商品
名人CP−OOJ)をスクリーン印刷法で所定のノ譬タ
ーンに形・、IEL、、導体層を形成する。そして、1
iiI素(N、)ガス中で、基板全体を温度300′G
で焼なまL7を行なう。
By the way, in the manufacturing process described above, after forming the ceramic layer 2 on the base E of the 71 plate 1 and impregnating it with thermosetting property 1111, it was bent at a temperature of 150°C for 15 minutes, and heated to 200°C with a latch.
Heat at a temperature of 1 hour to harden the resin. Thereafter, a conductive layer (IEL) is formed on the surface of the substrate using a paste (for example, Meijin CP-OOJ manufactured by Asahi Chemical Co., Ltd.) in a predetermined pattern by screen printing. And 1
iii The entire substrate is heated to 300'G in elemental (N,) gas.
Perform annealing L7.

このような製造方法であれば、@ペーストの焼なましお
よび基板の反り矯正を同時に行なうことができるため、
製造工程の効率な調めることができる効果がある。
With this manufacturing method, it is possible to anneal the paste and straighten the warp of the board at the same time.
This has the effect of making it possible to check the efficiency of the manufacturing process.

ここで、上記のような製造方法により形成した墓仮につ
いて、その反りを矯正した結果を各柿樹脂および金Tl
lI4板の14類に応じて鵡体的ミニ示す。数値は、@
6図に示した、烏の大永さで重信はμ罵、方向は鴫7図
(At 、 (Blで示すようにセラミックmJ&−外
稠にして反った場合を十万同、内偶にして反った場合な
一方向とした。
Here, the results of correcting the warpage of the grave temporary formed by the above manufacturing method are shown in each persimmon resin and gold Tl.
The corpuscular mini is shown according to class 14 of lI4 plate. The numbers are @
As shown in Fig. 6, Shigenobu is μ in the long length of the crow, and the direction is shown in Fig. 7 (At, (as shown in Bl, the ceramic mJ If it is warped, it will be in one direction.

表(1)(金属板が耐食アルミニウム板)表(2)(金
属板が純アルミニウム板)時間、さらに温度200℃で
1時間加熱し、反りの矯正は温度300℃で5分で行な
ったう1記表(11、(2)から明らかな様に、金@板
が純アルミニウム板で硬化樹脂がBT2100の場合C
二、反りを最も小さくするように矯正できる。このよう
に、金属板の材質お上び含浸樹脂を適当に選択すれば、
基板の反りを一定の範囲内で小さく押えることも可能で
あるー 〔発明の効果〕 以と詳述したようにこの発明によれば、へイデリツド集
積回路等の基板の製造工程において、基板に生ずる反り
を確実に矯正することができる。したがって、ノ譬ワー
トランジスタ等の回路素子を設けた基板を、放熱板に取
り付ける場合、十分な放熱効果を得ることができるなど
の効果がある。
Table (1) (Metal plate is a corrosion-resistant aluminum plate) Table (2) (Metal plate is a pure aluminum plate) Time, further heated at a temperature of 200°C for 1 hour, and warp correction was performed at a temperature of 300°C for 5 minutes. As is clear from Table 1 (11, (2)), when the gold plate is a pure aluminum plate and the cured resin is BT2100, C
2. It can be corrected to minimize warpage. In this way, if the material of the metal plate and the impregnated resin are appropriately selected,
It is also possible to suppress the warpage of the board within a certain range. [Effects of the Invention] As detailed below, according to the present invention, the warpage that occurs on the board during the manufacturing process of boards such as heidelised integrated circuits can be suppressed. Warpage can be reliably corrected. Therefore, when a substrate provided with a circuit element such as a power transistor is attached to a heat sink, it is possible to obtain a sufficient heat dissipation effect.

【図面の簡単な説明】[Brief explanation of drawings]

′#41図およびi@2図は従来の半導体装置の構成囚
、第3回置乃至(C)は温度変化による幕板の反りの状
態を説明する図、第4図囚、TB))よ従来の基板を放
熱板に収り付けた場合の状態を示す図、#45図囚0(
B)はこの発明の一実施例I:係る半導体装置の製造工
程を示す図、嘱6図および′@7図囚回置B)は基板の
反りの矯正状態を説明する図である。 1・・・金属板、2・・・セラミック噛、3・・・4仮
、4・・・導体層、5・・・抵抗体、5・・・ノ臂ワー
トランシスタ、I・・・放熱板、10・・・熱硬化性樹
ll旨、1ノ・・・空孔。 出禰人代理人  弁理士 鈴 江 武 鉢?
Figure 41 and i@2 are diagrams showing the configuration of a conventional semiconductor device, Figures 3 to 3 (C) are diagrams explaining the state of warpage of the curtain plate due to temperature changes, Figure 4 (TB)) A diagram showing the state when a conventional board is installed on a heat sink, #45 Figure 0 (
Embodiment I of the present invention: B) is a diagram illustrating the manufacturing process of such a semiconductor device; FIGS. DESCRIPTION OF SYMBOLS 1... Metal plate, 2... Ceramic mesh, 3... 4 Temporary, 4... Conductor layer, 5... Resistor, 5... Arm transistor, I... Heat dissipation Board, 10... thermosetting resin, 1... void. Dene person's agent Patent attorney Takeshi Suzue Hachi?

Claims (1)

【特許請求の範囲】[Claims] 金属板の表面上にセツミック層を溶射で形成する工程と
、上記セラミックーに熱硬化性樹81iiを含浸し樹脂
な熱硬化する工程と、上記金I14板およびセラミック
層からなる基板をに、1st詣の熱硬化温度よりも高い
温度で焼なましを行なって、基板の反りを矯正する工程
とからなることを特徴とする半導体iiiの製造方法。
The process of forming a ceramic layer on the surface of the metal plate by thermal spraying, the process of impregnating the ceramic with the thermosetting resin 81ii and thermosetting the resin, and the substrate consisting of the gold I14 plate and the ceramic layer are performed. A method for manufacturing a semiconductor III, comprising the step of annealing at a temperature higher than the thermosetting temperature of the substrate to correct warpage of the substrate.
JP4317482A 1982-03-18 1982-03-18 Method of producing semiconductor device Pending JPS58159393A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4317482A JPS58159393A (en) 1982-03-18 1982-03-18 Method of producing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4317482A JPS58159393A (en) 1982-03-18 1982-03-18 Method of producing semiconductor device

Publications (1)

Publication Number Publication Date
JPS58159393A true JPS58159393A (en) 1983-09-21

Family

ID=12656514

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4317482A Pending JPS58159393A (en) 1982-03-18 1982-03-18 Method of producing semiconductor device

Country Status (1)

Country Link
JP (1) JPS58159393A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63193547A (en) * 1987-02-06 1988-08-10 Showa Denko Kk Circuit board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63193547A (en) * 1987-02-06 1988-08-10 Showa Denko Kk Circuit board
JPH054820B2 (en) * 1987-02-06 1993-01-20 Showa Denko Kk

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