JPS58157243A - Terminal device - Google Patents

Abstract

PURPOSE:To reduce the burden on a processing processor, by providing a monitor section which monitors the data transfer between a communication control section and a storage section and transmits an interruption signal to a processing processor when a data communication end signal is detected. CONSTITUTION:In the data input from a line 14, the processing processor 3 indicates a data storage area in a storage device 1 to a channel CH ad starts the data input to a communication controlling section 2. The controlling section 2 informs the presence of data transfer request to the device 1 to the CH section 4. The CH section 4 receives this request and indicates the controlling section 2 to put the transfer data to the device 1 on a data bus 5 and stores the data on the bus 5 in a specified area of the device 1. When a monitoring section 7 monitors the bus 5 and detects a telegraphic message end code of data on the bus 5 during this time, the section 7 gives an interruption signal 13 to the processor 3 and gives information to the processor 3 for the end processing of data communication. Thus, the burden on the processor 3 is reduced and high-speed data communication is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to a device that communicates data with other devices via a line.

Disadvantages of the prior art In the past, data communication δ was performed without a procedure and according to a basic procedure.
In a terminal device that performs a message, there are various codes that indicate the end of a message, etc., so the processor inspects the data exchanged with the line every time, and checks whether the code indicates the end of the message, etc. When data was transferred and high-speed data communication was performed, the processor could not perform other processing as a terminal device.

In order to solve this problem, conventional methods have been implemented in which a processor for data communication is further added to the communication control section, but this method has the disadvantage that the communication control section is expensive.

Purpose of the Invention The present invention was made in order to eliminate the drawbacks of the conventional ones as described above.Once the processor starts data communication, the processing continues until a code indicating the end of the message is generated. The object of the present invention is to provide a terminal device capable of high-speed data communication without involving a processor in data communication.

Structure of the present invention FIG. 1 is a block diagram showing an embodiment of the present invention.
In the figure, is tl) data? Storage device for storing (2)
is a communication control unit in charge of data communication with other devices, (3
) performs processing as a terminal device using the data stored in the storage device (1), and also controls the communication control unit (2).
), and (4) is the storage device + 11 and the communication control unit (2) in which the processing processor (3) has activated the operation of the data communication unit 1d of the communication control unit (2).
), (5) is a data bus, (6) is an address bus, ('I) + t4 times control unit (2) transfers data to and from the storage device t (
11 and the data bus (
a monitoring unit that monitors the contents of (5) and sends an interrupt signal to the processor (3) when it detects data indicating the end of the data communication, causing the processing to end the data communication;
8) is a memory control signal, (9) is a memory transfer request signal,
The voice is the processing processor Riki Ota control signal, αυ is the channel section input/output control signal, 0 is the communication control section input/output control signal, Q3
is an interrupt signal, 0 is a line, and QS is an OR gate.

Operation of the present invention FIG. 2 is a timing chart showing the timing of each signal in an embodiment of the present invention, in which the same symbols as in FIG. 1 indicate the same signals, and FIG. 14
1, data on the data bus (5).

The operation of an embodiment of the present invention will be described below, taking as an example the case where data is input from a line.

To input data from line 0, the processor (3) first uses the data bus (5) and the processor input/output control signal U, and inputs data to the channel section (4) from the storage device (11). When data input is started, the communication control unit (2) waits for data from the line (14). When data is input, the memory transfer request signal (9) is used to notify the channel section (4) that there is a data transfer request to the storage device t1 (FIG. 2(b)).

The channel unit (4) receives this memory transfer request and sends the memory transfer request to the communication control unit (2)! ! The channel unit input/output control signal αI) is used to instruct the data bus (5) to transfer the data to be transferred to the device (1) (FIG. 2(C)).

The channel part input/output control signal circle is logically summed with the processing processor input/output control signal QI by the OR gate 0S, and becomes the communication control part input/output control signal (I). An instruction is given to load the data to be transferred to the storage device m onto the data bus (5).

Channel g (4) transfers the data on the data bus (5) to a predetermined area of the storage device (1) via the address bus (6).
) and determines whether the data on the data bus (5) matches the code indicating the end of the message, etc. If the code does not indicate the end of the message, no signal is generated, but if the code indicates the end of the message, as shown in Figure 2, when the C code is input, an interrupt is generated to the processing processor (3). A signal α is generated (FIG. ff2 (fl)), which advises the processing processor (3) to terminate the data communication.

In response to this interrupt signal C13, the processor (3) instructs the communication control unit (2) to stop inputting data in the same manner as at the time of startup (second position)). After this, even if data is input to the communication control unit (2) from the line (1), the memory transfer request number (9) will not occur.

In addition, although the case where data is inputted from the line (141) was explained above as an example, it goes without saying that the same effect can be achieved when data is outputted to the line I.

After starting the data input, Tsusa (3) waits until the monitoring unit (power interrupt No. 4g Q31 is sent).
Communication system related to data communication @ Miyako (2) and storage device (1)
It is not involved in data transfer with the channel section (4).
The effect of this is that even if high-speed data communication is performed, the load on the processor (3) will be negligible, making it possible to obtain a terminal device capable of high-speed data communication. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a timing chart showing the timing of each 4N inch in one embodiment of the present invention. In the figure, (1) is the storage device, (2) is the algorithm unit, +31 is the processor, (4) is the channel unit, (5) is the
) is a data bus, (6) is an address bus, (8) is a memory control (g), (9) is a memory transfer request signal, a+m is a processor input/output control signal, and U
υ is the channel unit input/output control number, Q3 is the communication system @ metropolitan input/output system # signal, u is the interrupt signal, I is the line, u51
is a logical L1 gate. Agent Shin Kuzuno - 1st! IA

Claims (1)

[Claims] In a terminal device that performs data communication with other devices via a line, a storage device that stores data, a communication control unit that is in charge of data communication with other devices, and uses the data stored in the storage device. a processing processor that performs processing as a terminal device and also operates the above-mentioned trace 1g control section, and the above-mentioned storage device and the above-mentioned communication control section after this processing processor starts the data communication operation of the communication control section. The communication control unit monitors the contents of the data bus when the channel unit ≦2 performs data transfer with the storage device, and determines the end of data communication. 1. A terminal device comprising: a monitoring section that sends a creation signal to the processing processor to cause the processing processor to terminate data communication when misused.