JPH1039957A - Reset control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To immediately perform a processing no matter what kind of an operation mode a reset request is generated in, and to protect the contents of a memory by outputting respectively specified signals at the time of power supply OFF, at the time of a CPU operation mode and at the time of a CPU standby mode by a reset control circuit. SOLUTION: A CPU 1 outputs bus cycle signals to this reset control circuit 8 and inputs reset request signals from the reset control circuit 8. The reset control circuit 8 outputs system reset signals at all times regardless of the presence/absence of the reset request signals at the time of the power supply OFF, outputs the system reset signals asynchronized with the reset request signals and synchronized with a CPU bus cycle at the time of the CPU operation mode and outputs the system reset signals synchronized with the reset request signals at the time of the CPU standby mode. Thus, no matter what timing a reset SW 10 is depressed at, memory access does not become abnormal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset control circuit, and more particularly, to a reset control circuit for a portable information device driven by a battery.

[0002]

2. Description of the Related Art In a conventional reset circuit, when there is an external reset request, a reset request signal is transmitted regardless of the operation cycle of the CPU.

When the protection of the memory contents is necessary, the reset request signal is synchronized with the bus cycle of the CPU without competing with the memory access. For example, the reset request signal is kept waiting until the end of the bus cycle of the operating CPU. Was sent out. Such a technique of synchronizing a reset request at the time of CPU operation with a bus cycle of the CPU is disclosed in Japanese Unexamined Patent Publication No. Hei.
Japanese Patent Application Laid-Open No. 3-242718 discloses a technique for synchronizing a reset request during CPU operation with RAM access.

[0004]

However, in the above prior art, the memory contents can be protected against an external reset request while the system power supply including the CPU is on, but when the system power is turned on or the power is turned off. However, there is a problem in that the memory contents are not protected against an external reset request when the power supply is unstable or when the system power is off, and the reset request is not immediately processed.

An object of the present invention is to provide a reset control circuit which can solve the above problems.

[0006]

According to a first aspect of the present invention, there is provided a reset control circuit which is activated by a signal indicating a power on / off mode of a CPU of a system, a signal indicating a CPU standby mode, and a reset request signal from the outside. A circuit, which always outputs a system reset signal regardless of the presence or absence of the reset request signal when the power is off, and outputs a system reset signal asynchronously with the reset request signal and in synchronization with a CPU bus cycle in the CPU operation mode. Output a bus cycle inhibit signal and output a system reset signal in synchronization with the reset request signal in the CPU standby mode.

According to a second aspect of the present invention, there is provided a reset control circuit according to the first aspect, wherein a backup signal for a system memory is output in synchronization with the system reset signal in a CPU operation mode. Features.

A reset control circuit according to a third aspect of the present invention is the reset control circuit according to the first aspect, wherein the reset request signal is output again after a predetermined period of time in a CPU operation mode. I do.

[0009]

FIG. 1 shows the configuration of a system using a reset control circuit according to the present invention. Here, the CPU 1 is a processor, and reads / writes data from / to the memory 3 and the IO control unit 4 via the bus 5. Regarding data access to the memory 3, the memory control unit 2 performs access control. The system control unit 7 controls the operation mode and power supply of the system 6 including the CPU 1, and stops the system clock, cuts off the system power supply, and the like according to a command from the CPU 1. Further, the system control unit 7 outputs to the reset control circuit 8 a signal indicating whether or not the system power is turned off and an operation state of the CPU 1. C
The PU 1 and the system control unit 7 exchange various operation mode signals and interrupt signals. Further, the CPU 1 outputs a bus cycle signal of the CPU 1 to the reset control circuit 8 and receives an external reset request signal from the reset control circuit 8 as an input. The battery 9 supplies power to the memory 3, the system control unit 7, and the reset control circuit 8, and this power is always supplied in a different system from the power supplied to the system 6. The reset SW 10 performs an operation when a system reset is required, and inputs a reset request to the reset control circuit 8.

Next, the operation of the reset control circuit 8 will be described with reference to FIGS. FIG. 2 shows a detailed circuit of the reset control circuit 8, and FIG. 3 is an operation time chart thereof. The reset control circuit 8 controls the flip-flop 1
1, an OR gate 12 and an AND gate 13, and the power supply voltage VBAT is always supplied by the battery 9.

The flip-flop 11 has a reset SW1
The state of the reset request signal RESREQ from 0
It is set at the rising timing of the bus cycle signal BCYST of PU1, and the bus cycle inhibit signal bar BUS is set.
Outputs INH.

The system control unit 7 is instructed by the CPU 1
Controls the operation mode of the system 6 and outputs a signal POFFMOD indicating the power-off mode and a signal bar STANDBY indicating the standby mode.

When the reset switch 10 is pressed in the operation mode of the system 6 in which the CPU 1 is operating, the reset request signal RESREQ becomes active (L), and a system reset is requested to the reset control circuit 8. The CPU 1 is operating, and the memory 3 and the IO
Each time the control unit 4 is accessed, the bus cycle signal BCYS
T becomes active. At the rising timing of BCYST, the flip-flop 11 is reset, the bus cycle inhibit signal BUSINH becomes active (L), the system reset signal RESET is output to the system 6 via the OR gate 12 and the AND gate 13, and the system A reset is performed. Reset SW1
0 is depressed asynchronously with the bus cycle, but is output in synchronization with the rise of the bus cycle signal BCYST. At the same time, the bus cycle inhibit signal bar BUSINH is output to the memory control unit 2 to inhibit the subsequent memory access. .

For this reason, the reset S
Even if W10 is pressed, the memory access does not become abnormal and the memory contents are not destroyed.

The standby mode is a mode for suppressing the power consumption of the system 6, and the system control unit 7 stops the clock supplied to the system 6 according to an instruction from the CPU 1, and enters the standby mode. Thereafter, the operation mode returns to the operation mode after a lapse of a predetermined time or by a special interrupt request or the like.

In the standby mode, the standby mode signal STANDBY becomes active (L), the flip-flop 11 is reset, the bus cycle inhibit signal BUSINH is always active (L), and the reset request signal RESREQ remains unchanged in the system. The reset signal becomes RESET, and the system reset is executed.

In the standby mode, the memory 3 is in the memory backup mode by the memory control unit 2, and even if an asynchronous reset is performed on the system, the memory contents are not destroyed.

The power-off mode of the system 6 is a memory backup mode, and the power of the system 6 including the CPU 1 is not supplied. However, the memory 3 has a battery 9
Supplies power for backup. In the power-off mode, the power-off mode signal POFFMOD becomes active (L), and via the AND gate 13, during the power-off mode, the system reset signal RESE.
When T becomes active, it is always in a system reset state.

Next, another embodiment of the reset control circuit 8 will be described with reference to FIGS. FIG.
Is configured such that a system reset signal RESET and a standby mode signal STANDBY
4 and a signal MEMBAC requesting a memory backup is output to the memory control unit 2.

The method of memory backup differs depending on the memory used. For example, a PS-RAM (Pseud Sta
In the tic RAM), if the OE (output enable) terminal is activated for a certain period or more, the self-refresh mode, which is the backup mode, is automatically set.

That is, as shown in FIG.
The memory backup mode is set only at the time of a system reset in the operation mode, the power-off mode, and the standby mode. Therefore, the backup mode is set except when the CPU may access the memory, and a good system can be obtained from the viewpoint of memory protection and power consumption.

In the operation mode, if the CPU 1 malfunctions (runaway, hang-up, etc.) for some reason, the CPU bus cycle signal BCYST may not be output. In this case, the system is operating abnormally, and it is necessary to reset the system to restore normal operation.

Therefore, another embodiment of the reset control circuit 8 for enabling the reset SW 10 even in the case of such a system malfunction will be described with reference to FIGS. FIG. 6 shows the configuration of FIG. 2 in which the reset request signal RESREQ is delayed by a certain period and output, and the output signal of the delay circuit 15 and the reset request signal RESREQ are input to the OR gate 16 and the AND gate 16 13 'is added. The delay circuit 15 is composed of, for example, a CR circuit, and the delay time of the delay circuit 15 is set to a time longer than the maximum bus access interval time of the system.

In a normal system operation mode, when the reset switch 10 is pressed, a reset request signal RESREQ becomes active (L), and a system reset is requested to the reset control circuit 8. At this time, if the CPU 1 does not output the bus cycle signal BCYST, the flip-flop 11 is not set, so that the output signal 107 does not become active (L) and the system reset signal RESET is not output. However, since the reset request signal RESREQ is active (L), the output signal 110 becomes active after a fixed time set in the delay circuit 15, and the output signal 111 becomes active (L) via the OR gate 16 to reset the system. A signal RESET is output to the system 6 to execute a system reset.

[0025]

As described above, according to the present invention, a reset control circuit capable of immediately processing a reset request and protecting the contents of a memory no matter what operating mode of the system the external reset request occurs. realizable.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system configuration according to the present invention.

FIG. 2 is a diagram illustrating details of a reset control circuit according to the embodiment of the present invention;

FIG. 3 is an operation time chart of the reset control circuit of FIG. 2;

FIG. 4 is a diagram illustrating details of a reset control circuit according to another embodiment of the present invention.

FIG. 5 is an operation time chart of the reset control circuit of FIG. 4;

FIG. 6 is a diagram showing details of a reset control circuit according to still another embodiment of the present invention.

FIG. 7 is an operation time chart of the reset control circuit of FIG. 6;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Memory control part 3 Memory 4 I0 control part 5 Bus 6 System 7 System control part 8 Reset control circuit 9 Battery 10 Reset SW

Claims (3)

[Claims] 1. A reset control circuit which is activated by a signal indicating a power on / off mode of a CPU of a system, a signal indicating a CPU standby mode, and a reset request signal from the outside. Irrespective of the CPU reset mode, in the CPU operation mode, outputs a system reset signal and a bus cycle prohibition signal in synchronism with the CPU bus cycle asynchronously with the reset request signal. A reset control circuit, which sometimes outputs a system reset signal in synchronization with the reset request signal. 2. The reset control circuit according to claim 1, wherein in a CPU operation mode, a backup signal for a system memory is output in synchronization with the system reset signal. 3. The reset control circuit according to claim 1, wherein in the CPU operation mode, the reset request signal is re-output after a predetermined period of time.