JPS58157214A - Digital receiver - Google Patents
Digital receiverInfo
- Publication number
- JPS58157214A JPS58157214A JP4128482A JP4128482A JPS58157214A JP S58157214 A JPS58157214 A JP S58157214A JP 4128482 A JP4128482 A JP 4128482A JP 4128482 A JP4128482 A JP 4128482A JP S58157214 A JPS58157214 A JP S58157214A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- meter
- receiving
- analog
- reception
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J1/00—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general
- H03J1/02—Indicating arrangements
- H03J1/04—Indicating arrangements with optical indicating means
- H03J1/045—Indication of the tuning band, the bandwidth, tone control, the channel number, the frequency, or the like
- H03J1/047—Indication of the tuning band, the bandwidth, tone control, the channel number, the frequency, or the like using electronic means, e.g. LED's
Landscapes
- Circuits Of Receivers In General (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は複数の受信周波数帯域の選局動作をティンタル
的に行ない、かつその受信周波数をアナログメータでア
ナログ的に表示するようにしだティ/タル受信機に関し
、各受信周波数帯域の最高周波数を受信したとき、アナ
ログメータが同一の値を指示するように設定することに
よって、正確なアナログ表示が行なえるようにしたもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tit/tal receiver that performs tuning operations for a plurality of receiving frequency bands in a tint-like manner, and displays the received frequencies in an analog manner with an analog meter. By setting the analog meter so that it indicates the same value when the highest frequency in the frequency band is received, accurate analog display can be performed.
近年、PLLを用いたシンセサイザ方式によって選局動
作をティンタル的に行なう受信機が数多く使用されてお
り、それらのうちには、受信周波数をティンタル的に表
示するだけでなく、アナログメータを併用してアナログ
的にも表示するようにしだものがある。In recent years, many receivers have been used that perform tuning operations in a tintal manner using a synthesizer method using a PLL. There are also things that can be displayed in an analog way.
このようなアナログ表示を併用したディジタル受信機で
、かつ複数の受信周波数帯域(たとえばFMとムM)の
受信が可能な受信機においては、各帯域ごとにアナログ
メータの指示値が異なるという問題がある。すなわち、
PLL中に使用されるティ/タル信号は、受信帯域周波
数と、そのチャンネルスペース周波数(最も隣接する局
と局の間の周波数)とによってステップ数が異なり、こ
れをDム変換して得たアナログ信号にもレベル差が生じ
る。In a digital receiver that also uses analog display and is capable of receiving multiple reception frequency bands (for example, FM and FM), there is a problem that the indicated value of the analog meter differs for each band. be. That is,
The tit/tal signal used during PLL has a different number of steps depending on the receiving band frequency and its channel space frequency (the frequency between the most adjacent stations), and is an analog signal obtained by D/M conversion. A level difference also occurs in the signal.
第1図は地域別にみた受信周波数とDCレベルの関係を
示すものであり、受信帯域(11と受信帯域(II)、
!:では、DCレベルにV2−11の差がある。しだか
ってこのような2つの受信周波数帯域を受信し、各DC
レベルでアナログメータを駆動すると、受信帯域(1)
のときの振れ角度が、受信帯域(tl)のときのそれに
比べて小さくなるという欠点がある。Figure 1 shows the relationship between reception frequency and DC level by region, and shows the relationship between reception frequency (11), reception band (II),
! : There is a difference in DC level of V2-11. However, by receiving such two reception frequency bands, each DC
When the analog meter is driven by the level, the reception band (1)
There is a drawback that the deflection angle at the time of the reception band (tl) is smaller than that at the reception band (tl).
本発明はこのような従来の欠点を解決するテイシタル受
信機を提供するものである。The present invention provides a digital receiver that solves these conventional drawbacks.
以下、本発明の一実施例を第2図とともに説明5はFM
検波段、6は増幅段、7はスピーカであり、以上は通常
のFM受信系を構成している。8は電圧制御発振器で構
成された局部発振器、9は局部発振器8の出力周波数を
分周するプログラマブル分周器、1oは基準発振器、1
1はプログラマブル分周器9の出力と基準発振器1oの
出力の位相を比較する位相比較器、12は位相比較器1
1の出力を低域沖波するローパスフィルタであり。Hereinafter, one embodiment of the present invention will be explained with reference to FIG.
A detection stage, 6 an amplification stage, and 7 a speaker constitute a normal FM reception system. 8 is a local oscillator composed of a voltage controlled oscillator; 9 is a programmable frequency divider that divides the output frequency of the local oscillator 8; 1o is a reference oscillator;
1 is a phase comparator that compares the phases of the output of the programmable frequency divider 9 and the output of the reference oscillator 1o; 12 is the phase comparator 1;
This is a low-pass filter that filters the output of 1 into low-frequency waves.
ローパスフィルタ12の出力により局部発振器8の発振
周波数が可変される。これらは周知のPLL回路を構成
しており、分周比設定回路13から、手動または自動で
プログラマブル分周器9に分周比設定用のディジタル信
号をセットすることにより、それに応じて局部発振周波
数が変化し、選局動作が行なわれる。The oscillation frequency of the local oscillator 8 is varied by the output of the low-pass filter 12. These constitute a well-known PLL circuit, and by manually or automatically setting a digital signal for setting the division ratio from the division ratio setting circuit 13 to the programmable frequency divider 9, the local oscillation frequency can be adjusted accordingly. changes, and a channel selection operation is performed.
一方、14,15.16はAM受信系を構成するAMア
ンテナ、AM受信回路、スピーカである。On the other hand, 14, 15, and 16 are an AM antenna, an AM receiving circuit, and a speaker that constitute an AM receiving system.
ここでは説明の便宜上スピーカ16をスピーカ7とは別
に表わしているが、いずれか一方のスピーカをFMとA
Mに共用できることは言うまでもない。捷たムV受信回
路15・内の増幅段もFM側の増幅段6と共用できるこ
とは言うまでもない、丑だムM受信回路15内にはFM
の場合と同様にAM用のPLLが組込まれているが、こ
のPLLについても一部をFM用のPLLと共用するこ
とができる。Here, for convenience of explanation, the speaker 16 is shown separately from the speaker 7, but one of the speakers is shown as FM and A.
Needless to say, it can be shared with M. It goes without saying that the amplification stage in the FM receiver circuit 15 can also be used in common with the amplification stage 6 on the FM side.
As in the case of , an AM PLL is incorporated, but a part of this PLL can also be shared with the FM PLL.
17はFM側のプログラマブル分周器9およびAM側の
それにセットされるディジタル信号をアナログ信号に変
換するDム変換器、18はその出力を積分する積分回路
、19はスイッチSw′l、SW2の操作によpFMと
ムMを切換える帯域セレクタ回路、20はアナログメー
タ、21はアナログメータ20の振れを調整する調整回
路である。この調整回路21は、トランジスタQ+ 、
Q2と半固定抵抗VRと、チャンネルスペース周波数の
切換え時にオン、オフされるスイッチSw3と、抵抗R
1〜R5で構成されている。17 is the programmable frequency divider 9 on the FM side and a DM converter that converts the digital signal set thereon into an analog signal, 18 is an integration circuit that integrates the output, and 19 is the switch Sw'l, SW2. 20 is an analog meter; and 21 is an adjustment circuit that adjusts the deflection of the analog meter 20. This adjustment circuit 21 includes transistors Q+,
Q2, a semi-fixed resistor VR, a switch Sw3 that is turned on and off when switching the channel space frequency, and a resistor R.
It is composed of 1 to R5.
上記構成において、選局動作そのものはよく知られてい
るので説明を省略し、アナログメータ20の動作につい
て説明する。In the above configuration, since the channel selection operation itself is well known, the explanation will be omitted, and the operation of the analog meter 20 will be explained.
捷ずスイッチSwjを操作してFMを受信する状態に切
換えると、帯域セレクタ回路19の出力により、トラン
ジスJQ2がオフになる。ここでトランジスタQ1のV
at特性補正用のバイアス抵抗R2を適切に選んで、最
低受信周波数の零電位から、最高受信周波数のvaxま
での間でアナログメータ20の指針が適切に振れるよう
に設定しておき、かつ最高周波数受信時にメータ20の
指針が最大振れ角度になるように調整しておく。すなわ
ち、第1図の受信帯域(I)がFMであるとすると、最
高周波数F1のときのDCレベルv1を、ランジスタQ
+ 、半固定抵抗VRを介してメータ20に印加し、
半固定抵抗VRによってメータ2oの指針が最大振れ位
置を指示するように調節する。When the switch Swj is operated to switch to the state of receiving FM, the output of the band selector circuit 19 turns off the transistor JQ2. Here, V of transistor Q1
The bias resistor R2 for AT characteristic correction is appropriately selected and set so that the pointer of the analog meter 20 swings appropriately between the zero potential of the lowest reception frequency and the vax of the highest reception frequency. Adjust the pointer of the meter 20 so that it reaches the maximum deflection angle during reception. That is, assuming that the receiving band (I) in FIG. 1 is FM, the DC level v1 at the highest frequency F1 is determined by transistor Q.
+, applied to the meter 20 via the semi-fixed resistor VR,
The pointer of the meter 2o is adjusted by the semi-fixed resistor VR so that it indicates the maximum deflection position.
このようにすれば、FMの各周波数の受信時にプログラ
マブル分周器9にセラl−されるティ・ジタル信号がD
ム変換器17でDム変換され、その出力が抵抗R1,ト
ランジスタQ1.半固定抵抗VRを介してアナログメー
タ20に印加され、メータ2゜の指針が振れ角、零から
最大重で移動し、これによってFMの受信周波数がアナ
ログ的に表示される。In this way, when receiving each FM frequency, the digital signal sent to the programmable frequency divider 9 will be
The D/M converter 17 performs D/M conversion, and the output thereof is sent to a resistor R1, a transistor Q1 . The signal is applied to the analog meter 20 through the semi-fixed resistor VR, and the pointer of the meter 2° moves from the zero deflection angle to the maximum weight, thereby displaying the FM reception frequency in an analog manner.
次にスイッチSw2を操作してムMを受信する状態に切
換えると、帯域セレクタ回路19の出力によりトランジ
スタQ2がオンになり、積分回路18の出力は抵抗R1
,Rsで分圧されてメー、J20に印加される。そこで
最高周波数(第1図の例でいえばF2 )のときのDa
レベルv2が抵抗R+ 、R1で分圧されてvlになる
ように抵抗R5の値を選び、この電圧をメータ20に印
加するようにすれば指針が最高周波数で最大振れ位置を
指示することになる。Next, when the switch Sw2 is operated to switch to the state where the signal M is received, the transistor Q2 is turned on by the output of the band selector circuit 19, and the output of the integrating circuit 18 is changed to the state of receiving the signal M.
, Rs and applied to J20. Therefore, at the highest frequency (F2 in the example in Figure 1), Da
Select the value of resistor R5 so that level v2 is divided by resistors R+ and R1 to become vl, and if this voltage is applied to meter 20, the pointer will indicate the maximum deflection position at the highest frequency. .
なお、輸出向けの受信機には、チャンネルスペース周波
数をFMで200KH2、450KH2、AMで10
KHzと9 KHzに切換える機能をもったものがあり
、この場合にもチャンネルスペース周波数の切換えによ
って、たとえば第1図の受信帯域(1) 、 GV)で
示すようにDCレベルが異なってくる。In addition, for export receivers, the channel space frequency is 200KH2, 450KH2 for FM, and 10KH2 for AM.
Some devices have a function of switching between KHz and 9 KHz, and even in this case, the DC level changes depending on the switching of the channel space frequency, as shown in the receiving band (1), GV) in FIG. 1, for example.
そこで第2図に示すように抵抗R5と並列に抵抗R4と
スイッチSw3を接続し、チャンネルスペース周波数の
切換えに連動してスイッチSw3を閉じ、積分回路18
の出力を抵抗R1と抵抗R2,Rsの並列合成値R2/
R5とで分圧してメータ20に加えるようにすれば、帯
域切換時と同様にメータ2゜の振れを合わせることがで
きる。Therefore, as shown in FIG. 2, a resistor R4 and a switch Sw3 are connected in parallel with the resistor R5, and the switch Sw3 is closed in conjunction with the switching of the channel space frequency.
The output of is the parallel composite value R2/ of resistor R1 and resistor R2, Rs.
If the voltage is divided by R5 and applied to the meter 20, the 2° deviation of the meter can be adjusted in the same way as when changing the band.
このように本発明は異なる受信周波数帯域をディジタル
的に受信し、そのときのディジタル信号にもとづいてア
ナログ信号を発生し、このアナログ信号でメータを駆動
して受信周波数をアナログ的に表示するものにおいて、
各受信周波数帯域の最高周波数受信時にメータの振れ位
置を一致させるようにしたものであるから、受信周波数
を正確にアナログ表示することができる。In this way, the present invention digitally receives different reception frequency bands, generates an analog signal based on the digital signal at that time, drives a meter with this analog signal, and displays the reception frequency in an analog manner. ,
Since the meter deflection positions are made to match when receiving the highest frequency of each receiving frequency band, the receiving frequency can be accurately displayed in analog form.
第1図は受信周波数とD(3レベルの関係を示す図、第
2図は本発明の一実施例の回路図である。
1〜7・・・・・・FM受信系、8〜12・・・・・・
PLL、13・・・・・・分周比設定回路、14〜16
・・・・・・ムy受信系、17・・・・・・0人変換器
、18・・・・・・積分回路、19・・・・・・帯域セ
レクタ回路、2o・・・・・・アナログメータ、21・
・・・・・調整回路。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図
−4少俤用遺麩FIG. 1 is a diagram showing the relationship between reception frequency and D (3 levels), and FIG. 2 is a circuit diagram of an embodiment of the present invention. 1 to 7...FM reception system, 8 to 12.・・・・・・
PLL, 13... Division ratio setting circuit, 14 to 16
...Muy receiving system, 17...0 converter, 18...integrator circuit, 19...band selector circuit, 2o...・Analog meter, 21・
...adjustment circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 4: Small amount of leftover fu
Claims (1)
信号にしたがって受信する複数の受信手段と、上記各受
信手段中のディジタル信号をアナログ信号に変換するD
ム変換手段と、上記DA変換手段から出力されるアナロ
グ信号に応じて受信周波数をアナログ的に表示するアナ
ログメータと。 上記各受信周波数帯域の最高周波数受他時の上記アナロ
グメータの指示値を同一の値に一致させる手段とを備え
たディジタル受信機。[Scope of Claims] A plurality of receiving means for receiving a plurality of mutually different receiving frequency bands according to tintal signals, and D converting digital signals in each of the receiving means into analog signals.
and an analog meter that displays a reception frequency in an analog manner according to the analog signal output from the DA conversion means. A digital receiver comprising means for making the indicated values of the analog meter coincide with the same value when receiving the highest frequency of each of the receiving frequency bands.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4128482A JPS58157214A (en) | 1982-03-15 | 1982-03-15 | Digital receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4128482A JPS58157214A (en) | 1982-03-15 | 1982-03-15 | Digital receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58157214A true JPS58157214A (en) | 1983-09-19 |
Family
ID=12604139
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4128482A Pending JPS58157214A (en) | 1982-03-15 | 1982-03-15 | Digital receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58157214A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05177971A (en) * | 1991-12-26 | 1993-07-20 | Nitto Shiko Kk | Binding body and manufacture thereof |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS573414A (en) * | 1980-06-06 | 1982-01-08 | Fujitsu General Ltd | Meter driving circuit |
-
1982
- 1982-03-15 JP JP4128482A patent/JPS58157214A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS573414A (en) * | 1980-06-06 | 1982-01-08 | Fujitsu General Ltd | Meter driving circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05177971A (en) * | 1991-12-26 | 1993-07-20 | Nitto Shiko Kk | Binding body and manufacture thereof |
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