JPS6042657B2 - Reception frequency correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiving frequency correction circuit for a synthesizer type radio receiver.

Electronically tuned receivers use an analog method that uses a voltage memory element to generate a voltage that gradually increases and decreases depending on the command voltage and continues to output the current voltage when the command voltage disappears to change the voltage variable capacitance element of the tuning circuit. In addition to these, synthesizer-based systems have also appeared, especially for C-ray reception.

This synthesizer type receiver has the configuration shown in FIG.

In this figure, 1 is an antenna, 2 is a high frequency amplifier, 3 is a local oscillator, 4 is a mixer or frequency converter, 5 is an intermediate frequency amplifier, 6 is a detection circuit, and 7, 8, and 9 are voltage variable capacitance elements such as varicaps. This is a resonant circuit with a capacitor. These parts are the same as the tuner section of a normal superheterodyne electronically tuned radio receiver. In the case of a synthesizer type receiver, a key switch 10, a controller 11, a varicap control circuit and a channel selection circuit are used.
Prescaler 12, 1/N programmable frequency divider 13, reference frequency oscillator 14, frequency divider 1
5. A phase detector 16 and a low-pass filter 17 are provided, each of which includes a PLL (Phase Locked Loop) or the like. The channel selection operation in this receiver is performed at frequencies 71.0 to 9.
The following explanation will be given using 0.0 MHz FM broadcast in Japan as an example. The output frequency of the local oscillator 3 for the above FM broadcast frequency band is 65.3 to 79.3 MHz, but this is reduced to 1110 by the prescaler 12, which is a frequency divider, to 6.53 to 7.93 MHz.

This is further frequency-divided by a divider 13 by a value 1/N varying between 653 and 793. The channel separation of FM broadcasting is 100KH2, so the broadcasting frequencies are 76.0, 76.1, 76, 2, etc. In terms of local frequencies, they are 65.3, 65.4, 65. .5...
. . . and no other values, the output frequency of the divider 13 will always be 10 KHz when the N value is appropriately selected and tuned to the broadcast frequency. These N values 653, 654...793 are stored in the controller 11, and the key switch 10
(this will indicate the desired broadcasting station),
Preset to divider 13. On the other hand, the reference frequency oscillator 14 oscillates at a frequency of 5.76 MHz in this example, but since the frequency is set to 11576 by the divider 15, the output of the divider is 10 KHz. Therefore, the receiver is key switch 1
0 and controller 11, the output frequencies of dividers 13 and 15 are both 10 KHz, and after phase synchronization, there is no output from phase detector 16. The variable capacitance element of the tuning circuit is not adjusted, and the receiver enters the receiving state for now. However, if the receiver is not in the receiving state corresponding to the N value, the phase detector 16 outputs an output with a width and polarity corresponding to the deviation.
is generated, which is smoothed by the low-pass filter 17 and then applied to the variable capacitance elements of the resonant circuits 7 to 9. Therefore, the receiving frequency is adjusted, and the output frequency of the divider 13 becomes 1.
The adjustment ends when it converges to 0KHz and synchronizes,
Enters reception status at the broadcasting station (broadcasting frequency) specified by the N value. This synthesizer type receiver allows highly accurate reception.

That is, the N value used for channel selection does not change, of course, and therefore the reception accuracy depends on the accuracy of the reference frequency oscillator 14, which is extremely accurate because it is a crystal oscillator. By the way, with this conventional PLL synthesizer receiver.
has no means of fine tuning.

This is also due to the high accuracy mentioned above.The N value and the crystal oscillator allow you to specify the reception frequency with extremely high precision, and the local oscillation frequency converges to the specified frequency as precisely as possible, so the frequency deviation is This is because it is possible to reliably tune into the broadcast frequency and enter the receiving state, which is usually negligible. However, there is a shift in the tuning frequency of the intermediate frequency stage due to temperature fluctuations, and for indoor use, the temperature fluctuation is at most 0°C.
It is sufficient to consider a temperature of -30°C, but since it is exposed to the outside air for automotive use, it is necessary to plan for a temperature of -20°C to +80°C, and the shift in the resonance frequency of the intermediate frequency cannot be ignored.
Also, the frequency of radio waves broadcast from broadcasting stations (broadcast frequency)
This can be quite noticeable in some countries. This frequency shift can be corrected by changing the N value or adjusting the reference frequency Fr, but the N value is a numerical value stored in memory, and its correction is troublesome. Furthermore, the reference frequency is fixed at 10 KHz or the like, and it is difficult to change it because it is related to channel separation. In view of the above, the present invention attempts to provide a synthesizer receiver with a fine tuning function by making it possible to correct frequency deviations by means that can be implemented relatively easily. Next, this will be explained in detail with reference to the embodiment shown in FIG. In Fig. 2, the area within the scanning line frame is the radio receiver tuner section shown in Fig. 1.
0 is a PLL synthesizer, which consists of a 1/N programmable frequency divider 13, a reference frequency oscillator 14, and a phase detector 16 shown in FIG.

In the present invention, the prescaler 12A that reduces the local frequency to a frequency that can be counted by the PLL synthesizer is a variable hexadecimal counter with a maximum of hexadecimal, and is an ECL or Schottky TT counter.
It normally operates as a 1 pheasant counter, but when the load signal S2 is input, it becomes a 5 to 1 pheasant counter determined by the contents of the counter 23 only at that time. This prescaler 1
The counter 23, which sets the frequency division ratio to 2A, is an up/down counter, and operates as a w-adic counter when there is no load signal S1. Reference numerals 21 and 22 represent a controller and a switch matrix, which correspond to the microcomputer 11 and key switch 10 in FIG.

24, 25, 26 are NAND gates, 27, 28 are interlocking switches, the switch 27 can rotate in one direction or the opposite direction without limit, the mover 28a of the switch 28 closes to the contact 28b or 28c depending on the direction of rotation, This state is maintained while rotating in the same direction.

29 and 30 are resistors, and 31 is an amplifier.

Next, the operation of this circuit will be explained with reference to the pulse waveform diagram in FIG. When the receiver is selecting a channel, noise is generated from the speaker, so muting is applied to remove it. However, while the controller 21 is outputting the mute signal S1 having the waveform shown in FIG. counter 23
The preset signal AiBiCiDi becomes the load signal for the counter, and the preset signal AiBiCiDi is the power supply for the counter. The preset signal 1010 (decimal number 10) is set in the counter 23 because the preset signal 1010 is fixed to 1010 by the connection including the 01 resistor 29 and the ground.

On the other hand, as described above, the N value indicating the desired broadcasting station is set in the PLL synthesizer 20 via the path between the switch matrix 22 and the controller 21, and the prescaler 12
At A, the count value of the counter 23 (currently 10) is preset by the load signal S2 from the PLL synthesizer 20, and w
It is used as a forward counter. Therefore, the output frequency F5 of the local oscillator 3 shown in FIG. 3 is 1110 at the prescaler 12A.
The PLL synthesizer 20 further divides the frequency into 1/N and compares it with the reference frequency of 10 KHz. If the synchronization is achieved, the 1/N divided output is also 10 KHz, so P
There is no output of the LL synthesizer 20, so the high frequency stage,
The capacitance values of the variable capacitance elements of the frequency conversion stages 2 and 4 and the local oscillator 3 are not corrected and the reception state is entered as is. However, if tuning is not achieved, the PLL synthesizer 20 adjusts the width and width according to the frequency deviation. A polar pulse is output, which is smoothed by a low-pass filter 17 and then sent to an amplifier 3.
1 to the variable capacitance element, and changes its capacitance value to converge to a tuned state. In this way, it enters the receiving state,
At this time, the mute signal S1 is canceled. However, when the resonant frequency of the intermediate frequency stage 5 deviates from the design value (10.7 MHz for FM) by ΔFi due to a rise in temperature, the PLL synthesizer 20 uses the high precision obtained by the crystal oscillator 14 to convert the local oscillation frequency to the reference frequency x N ( This is designed to be the broadcasting frequency minus 10.7MHz), so the output frequency of the frequency conversion stage 4 is 10.7MHz with this accuracy.
Hz, and the resonant frequency of the intermediate frequency stage is the deviation ΔF.
j will be shifted.

In the present invention, in order to correct this deviation, the output frequencies of the local oscillator 3 and therefore the frequency conversion stage 4 are shifted in the same direction by ΔFi, so that the intended gain can be obtained over the intended frequency band by correctly tuning at the intermediate frequency. Make it. Specifically, in this case, the listener rotates the switches 27, 28 in one direction or in the opposite direction. When the switch 27 rotates, its movable element 27a separates from one of the plurality of commonly grounded fixed contacts 27b, contacts the adjacent fixed contact 27b, and separates again. L, H...
・A potential that changes to Lulu can be obtained. One input terminal of the NAND gate 26 is connected to the power supply DD via the resistor 30, so it is always at H level, and therefore the movable element 27b (7
) The NAND gate 26 changes H and L according to the H and L level changes.
, H, L... Produces an output that changes to the level. This is input to the clock terminal of the counter 23, and the counter 23
counts this. Further, when the switch 28 rotates in one direction together with the switch 27, its movable element 28a contacts a grounded fixed contact 28b, and when it rotates in the other direction, it contacts a fixed contact 28c connected to the power supply VDD via a resistor 29. . Therefore, when the movable element rotates in one direction, it becomes L level, and when it rotates in the other direction, it becomes H level.
3 is applied to uptown U/D, and the counter is set as an up counter or a down counter. Now switch 27
As shown in FIG. 3, generates three L level pulses and inputs them to the clock terminal Cr of the counter 23, and the switch 28 sets the counter 23 to be an up counter. Counting in the addition direction, the counted value becomes 13. DOCOBOAO in FIG. 3 shows the output of the counter 23, which is initially 10, that is, 1010, but becomes 1011, 1100, and 1101 when one, two, and three pulses are applied to the clock terminal Cr. The PLL synthesizer 20 includes a 1/N programmable frequency divider as described in FIG. 1, which is preset to a value N to count down the input pulses and output one pulse when the value becomes O. , N pulses are taken in from the controller 21 along with the load signal, the input pulses are counted again, and when the value becomes O, one pulse is output, and this is repeated to perform 1/N frequency division. This pulse also serves as the load signal S2 of the prescaler 12A,
The contents of the counter 23 are read into the prescaler A.
Therefore, the prescaler 12A becomes a 13-decimal counter when the load signal S2 is input, and outputs 1 pulse when it counts 13 pulses as shown in FIG. When the load signal S2 is input, the counter returns to the 13-decimal counter again, and this process is repeated thereafter. In other words, the prescaler 12A functions as a radical counter only once out of two times, and functions as a w-radius counter the remaining N-1 times. To further explain this point with a numerical example, for example, in 82.5MHz (7) FM reception, Δ
If a slippage of Fi=-30KHz occurs, the resonance (center) frequency of the intermediate frequency stage is 10.7-0.03=10.
67MHz, and the local oscillation frequency is 82MHz when normal.
．． 5-10.7=71.8r! It needs to be 71.83MHz, which is 30KHz higher than 4Hz.

The N value can be specified up to 718, and a value lower than that, 0.3 in this example, cannot be specified. On the other hand, when the switches 27 and 28 are turned to increment the counter 23 by 3 as described above, the prescaler 12A loses the frequency by 1 out of 1 out of N times, and 1 out of 1 out of 1 out of N times. Emission frequency Fe
The average value is F1 [Toju? ]±=10 KHz, which in this example becomes 10NN71.823 MHz, which becomes the desired 71.83 MHz.

In reality, the listener only needs to turn the switches 27 and 28 to hear the sound from the speaker SP, and then stop operating the switch when the distortion has disappeared. Since the switches 27 and 28 can be rotated in one direction or the other direction without limit, the contents of the counter 23 may be manipulated to 0 or the maximum value, but it is preferable not to make too many corrections and cause the contents to shift to adjacent channels. Since there is no upper limiter and lower limiter consisting of NAND gates 24 and 25 is provided.

In other words, all four input terminals of the NAND gate 24 are 1.
The NAND gate 25 produces an L level output when its four input terminals receive the 0101 input, and even if the NAND gate 26 is closed and the switches 27 and 28 are operated, no further output occurs. Above is counter 23
Make sure that no pulses are input to the Input 1111 above
and 0101 correspond to 15 and 5 in the w-adic number, so that the counter 23 has a count value in the range of 10±5. In this example, of the second and fourth digit terminals that serve as the O input of the NAND gate 25, the second digit is omitted as it is unnecessary, and an inverter is added to the fourth digit to input the fourth digit signal of the counter 23. ing. If the count value of the counter 23 is limited to ±5, this is approximately S゛±
It becomes 50KHz. Since FM channel separation is 100 KHz, it is possible to perform fine tuning without intruding into the area of adjacent channels. When the receiving state is established as described above, when the channel selection operation is started to change the broadcasting station, the mute signal S1 is generated, and the counter 23 receives the load signal and receives the fixed input Ai.
BiCiDi, that is, the number 10, is preset and returns to the 1 pane counter.

Therefore, the frequency fine adjustment has to be done again, but this is natural since it has to be done for each station. As explained in detail above, according to the present invention, it is possible to provide a PLL synthesizer receiver with a fine tuning function, and the tuning operation is extremely simple as it is only necessary to turn a switch while listening to the sound from the speaker. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an overview of a synthesizer receiver.
FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a pulse waveform diagram for explaining the operation.

Claims (1)

[Claims] 1 A prescaler that reduces the output frequency of the local oscillator and a numerical value N that determines the frequency division ratio are preset, and the output frequency of the prescaler is down counted and divided by 1/N, and the 1/N divided output is used as the reference. P calculates the deviation by comparing the frequency and phase, and generates a voltage to control the tuning voltage variable capacitance element of the receiver tuner section so that the deviation becomes zero.
In a reception frequency correction circuit of a synthesizer type radio receiver, which is equipped with a LL synthesizer and receives broadcasting of a station specified by the N value, the switch generates a pulse and a signal indicating the direction of rotation when rotated; A counter has a preset value that counts up or down when pulses and rotational direction signals are input, and is modified by the counted value.It is normally an M-ary counter, and when a load signal is input from the PLL synthesizer, the contents of the counter are taken in. and the prescaler, which is a variable base counter that temporarily becomes an X-base counter.