JPS58155787A - Manufacture of semiconductor light-emitting element - Google Patents

Manufacture of semiconductor light-emitting element

Info

Publication number
JPS58155787A
JPS58155787A JP57038553A JP3855382A JPS58155787A JP S58155787 A JPS58155787 A JP S58155787A JP 57038553 A JP57038553 A JP 57038553A JP 3855382 A JP3855382 A JP 3855382A JP S58155787 A JPS58155787 A JP S58155787A
Authority
JP
Japan
Prior art keywords
layer
type
current
active layer
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57038553A
Other languages
Japanese (ja)
Inventor
Tsunao Yuasa
湯浅 図南雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57038553A priority Critical patent/JPS58155787A/en
Publication of JPS58155787A publication Critical patent/JPS58155787A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure

Landscapes

  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To manufacture an optical semiconductor laser having excellent characteristics with superior yield by partially heating a high impurity-concentration semiconductor layer, selectively inverting a conduction type of a low-concentration semiconductor layer by a push-in effect and introducing a current constricting mechanism to the lower section of an active layer. CONSTITUTION:An undoped N<-> type InP layer 10, an N type InP layer 11 to which Te is added, the undoped InGaAsP active layer 12, a P type InP layer 14 to which Zn is added, and an N type InGaAsP layer 15 to which Te is added are laminated onto an N type InP substrate 9 in succession. When YAG laser lights 17 are irradiated while using a metallic film 16 as a mask, the lights 17 pass through the layer 15, and are absorbed selectively by the layer 14. Accordingly, an impurity Zn is pushed into a layer 13, the layer 12, the layer 11 and the layer 10 in succession. A conduction type of the layer 10 is inverted into a P<-> type from an N<-> type at that time. The mask 16 is removed through etching, and Zn is diffused selectively so as to reach the layer 14 while using an SiO2 film as a mask. The current constricting mechanism is formed to the lower section of the active layer.

Description

【発明の詳細な説明】 本発明は素子内部に電流の広がりを制限する構造を有す
る二重へテロ接合層から成る注入型半導体発光素子の製
造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an injection type semiconductor light emitting device comprising a double heterojunction layer having a structure that limits the spread of current inside the device.

ヘテロ接合構造を用いた半導体発光素子は波長0.84
m帯の(AjlGa )ム畠、波長l#m帯のInGa
ムSP/InP L E D 、レーザにおけるように
、特に光フアイバー通信用の光源として実用化されてい
る。
A semiconductor light emitting device using a heterojunction structure has a wavelength of 0.84
m-band (AjlGa) Muhata, wavelength l#m-band InGa
SP/InPLED has been put to practical use, especially as a light source for optical fiber communications, such as in lasers.

これらの半導体発光素子においては、LEDについては
発光効率の増加、レーザについてはしきい値電流密度の
減少1発振横モードの制御のために活性層での電流の広
がりを制限することが必要である。特に半導体レーザに
おいては高温での連続発振を可能にするためにも、消費
電力を小さくするためにもできるだけしきい値電流が小
さいことが望ましい。このため電流をできるだけ活性領
域のみに流すような方法が提案されている。最も良く知
られている方法は、最上層の導電型を不純物拡散によっ
て選択的に反転させる方法、あるいは8量08等の絶縁
物膜を表面につけて通常のフォトリソグラフィーの技術
によって電流注入領域用の室を設ける方法であるが、こ
のような方法によって表面より注入される電流の領域が
限定される効果はあるが、この場合でも表面より注入さ
れた電流は内部に向って次第に広がり、活性層において
は表面の電流注入領域用の数倍の範囲に広がってしまう
。これに対して発振領域はほぼ表面の電流注入領域層と
同程度であるため、実際に社使用されない無効電流成分
の全注入電流に対して占める割合がかなり大きい。この
ためしきい値電流密度は上昇し、発振の微分量子効率は
低くなってしまう。このような欠点を除去し、活性層に
おける電流の流れをさらに限定するために、基板側にも
さらに電流を制限する機構を設けることが提案されてい
る。この基板側に設けた電流制限のためOS造を作製す
る従来の方法をa11図に基づいて説明する。基板の導
電型がnilである場合を例にとると、第1図(&)の
ように基板1上にpm半導体層2を成長し、次に半導体
層2を通常の7オ) IJソダテフイー技術を用いて第
1図伽)のように選択的に除去する。次にその上に第1
図(c)のようにs m’li半導体層3、活性層4、
pHクラッド層Ssn臘キャップ層6を順次成長する。
In these semiconductor light emitting devices, it is necessary to limit the spread of current in the active layer in order to increase the luminous efficiency for LEDs, decrease the threshold current density for lasers, and control the 1-oscillation transverse mode. . Particularly in semiconductor lasers, it is desirable that the threshold current be as small as possible in order to enable continuous oscillation at high temperatures and to reduce power consumption. For this reason, methods have been proposed in which current is passed only through the active region as much as possible. The most well-known method is to selectively invert the conductivity type of the top layer by impurity diffusion, or to apply an insulating film such as 08 to the surface and form a current injection region using normal photolithography technology. Although this method has the effect of limiting the area of the current injected from the surface, even in this case, the current injected from the surface gradually spreads toward the inside, and in the active layer. will extend over an area several times larger than that for the current injection region on the surface. On the other hand, since the oscillation region is approximately the same as the surface current injection region layer, the proportion of the reactive current component that is not actually used in the total injection current is quite large. Therefore, the threshold current density increases and the differential quantum efficiency of oscillation decreases. In order to eliminate these drawbacks and further limit the current flow in the active layer, it has been proposed to provide a further current limiting mechanism on the substrate side. A conventional method for manufacturing an OS structure for current limiting provided on the substrate side will be explained based on FIG. a11. Taking the case where the conductivity type of the substrate is nil as an example, a PM semiconductor layer 2 is grown on the substrate 1 as shown in FIG. selectively remove it as shown in Figure 1). then the first one on top of that
As shown in figure (c), the s m'li semiconductor layer 3, the active layer 4,
A pH cladding layer Ssn and a capping layer 6 are sequentially grown.

次に第1図(ωのようにn[キャップ層6の表面よりp
mクラッド層5迄、不純物を選択拡散しp瑠領域7を設
けて電流注入領域とする。この構造においては注入され
た電流は基板側にも電流狭窄層があるため上下で限定さ
れて活性層での電流広がりが抑制される。
Next, as shown in FIG.
Impurities are selectively diffused up to the m cladding layer 5 to form a p-type region 7, which serves as a current injection region. In this structure, since there is a current confinement layer on the substrate side, the injected current is limited between the upper and lower sides, and the current spread in the active layer is suppressed.

しかしながら、上述した方法においてはp型電流狭窄層
を形成するために結晶成長を2回行なう必要がある上に
、電流通過領域を形成するために選択エツチングを行な
わなけれにならないので工程が複雑になるという欠点が
ある。上述した第1図(d)の2の蛸き電流狭窄層を形
成する他の方法として、基板1に選択的に不純物を拡散
して導電型を反転させる方法、あるいはプルトンを選択
的に打ち込んで局部的に高抵抗領域を設ける方法がある
が、いずれも基板表面が損傷するために基板に積層する
エピタキシャル層に多数の転位源が持ち込まれ、このた
め素子の動作寿命が短かくなるという欠点がある。さら
にまた電流狭窄の効果を上げるためには電流注入領域層
7と電流狭窄層2との相対的な位置を合わせる必要があ
る。具体的には電流注入領域7の中心線と電流狭窄層2
が除去された部分、即ち電流通過領域8の中心線とが一
致する必要がある。この位置合わせは前述した7オトリ
ソグラフイによる拡散マスク作製の工程においてガラス
マスクに印写されたマスクパターンと結晶内部に設けら
れた電流通過領域8の位置合わせとして行なわれるが、
この場合の位置合わせの精度は1μm以下であることが
要求されるため、実際には非常に困難である。
However, in the above method, it is necessary to perform crystal growth twice to form a p-type current confinement layer, and selective etching must be performed to form a current passing region, which complicates the process. There is a drawback. Other methods for forming the octopus current confinement layer 2 in FIG. 1(d) described above include selectively diffusing impurities into the substrate 1 to invert the conductivity type, or selectively implanting pluton. There are methods to create a locally high resistance region, but each method has the disadvantage that the substrate surface is damaged and a large number of dislocation sources are brought into the epitaxial layer stacked on the substrate, which shortens the device's operating life. be. Furthermore, in order to increase the effect of current confinement, it is necessary to match the relative positions of current injection region layer 7 and current confinement layer 2. Specifically, the center line of the current injection region 7 and the current confinement layer 2
It is necessary that the removed portion, that is, the center line of the current passing region 8, coincide with the center line of the current passing region 8. This alignment is performed as alignment between the mask pattern printed on the glass mask and the current passing region 8 provided inside the crystal in the step of manufacturing the diffusion mask using 7 otolithography described above.
In this case, the alignment accuracy is required to be 1 μm or less, which is actually very difficult.

本発明は上述した如き従来の電流狭窄層の製造方法にお
ける欠点を除去した新規有用な電流狭窄層の製造方法を
提供するものである。
The present invention provides a new and useful method for manufacturing a current confinement layer that eliminates the drawbacks of the conventional method for manufacturing a current confinement layer as described above.

本発明の要旨は、活性層の片方のIIK少なくとも第1
の導電型の低濃度半導体層を設け、反対側に第2の導電
型の高不純物濃度半導体層を設けて賦高不純物濃度半導
体層を選択的に加熱することによって、高不純物濃度半
導体層中の不純物を低濃度半導体層に局部的に押し込ん
で、低濃度半導体層の導電型を第2の導電型に変えて電
流狭窄層とするものである。
The gist of the present invention is to provide at least the first IIK of one side of the active layer.
By providing a low concentration semiconductor layer of a conductivity type, providing a high impurity concentration semiconductor layer of a second conductivity type on the opposite side, and selectively heating the high impurity concentration semiconductor layer, the high impurity concentration semiconductor layer is heated. Impurities are locally pushed into the lightly doped semiconductor layer to change the conductivity type of the lightly doped semiconductor layer to a second conductivity type, thereby forming a current confinement layer.

既に活性層上方部にある第1半導体層上に導電型が第1
半導体層とは反対の第2半導体層を設けた半導体結晶に
おいて該第2半導体層を選択的にかかる方法によっては
、活性層上部の電流通過領域ヲ狭くするプレーナストラ
イプ構造は実現できるが、活性層下方部には電流狭窄機
構を設けることができないため、しきい値電流密度を大
巾に下げることはできをい。本発明においては特に活性
層下方部に第1導電型の低不純物濃度半導体層を活性層
上C古都に第2導電型の高不純物濃度半導体層を設け、
該高不純物濃度半導体層を局部的に加熱してよ低濃度半
導体層の導電型をいわゆる押し込み効果によって選択的
に反転させて活性層下方部に電流狭窄機構を導入せんと
するものである。
The first conductivity type is already on the first semiconductor layer above the active layer.
In a semiconductor crystal in which a second semiconductor layer opposite to the semiconductor layer is provided, a planar stripe structure in which the current passing region above the active layer is narrowed can be realized by selectively forming the second semiconductor layer. Since a current confinement mechanism cannot be provided in the lower part, it is impossible to significantly lower the threshold current density. In particular, in the present invention, a low impurity concentration semiconductor layer of the first conductivity type is provided below the active layer, and a high impurity concentration semiconductor layer of the second conductivity type is provided above the active layer.
The purpose is to locally heat the high impurity concentration semiconductor layer and selectively invert the conductivity type of the low concentration semiconductor layer by a so-called push effect to introduce a current confinement mechanism in the lower part of the active layer.

本発明によれば結晶成長は1回で済み、かつ基板に加工
をせずに電流狭窄層を活性層下に有する半導体発光素子
の製造が可能である。また前述したような表面よりの電
流注入領域を形成する際の電流注入領域と電流狭窄層と
の位置合わせが不要になる利点もある。以下、本発明を
具体的に実施例をもって詳細に説明する。本実施例にお
いては半導体レーザの製造方法に本発明を適用する場合
を例に採り説明する。
According to the present invention, crystal growth can be performed only once, and a semiconductor light emitting device having a current confinement layer under an active layer can be manufactured without processing the substrate. There is also the advantage that alignment between the current injection region and the current confinement layer when forming the current injection region from the surface as described above is not necessary. Hereinafter, the present invention will be specifically explained in detail with reference to examples. In this embodiment, a case will be described in which the present invention is applied to a method of manufacturing a semiconductor laser.

第2図は本実施例の具体的な製造工程を示す説明図であ
る。
FIG. 2 is an explanatory diagram showing the specific manufacturing process of this example.

まず、第2図(&)の如く、液相あるいは気相成長によ
りnmInP基板9上に、アンドープまたは〒・添加キ
ャリア練炭2−5 X 10”aw−”0n−111n
P層(厚み2μm)10.T・添加キャリア濃度3×1
017cm+−3のn型InP層(厚み0.1−〇、5
711!1)11、アンドープInGaAaP活性層(
厚みQ、2jams禁制帯巾0.95eV)12.Zn
添加キャリア濃度2〜3 x l Q”am−’のp型
InP層(厚み2nm)13、Zn添加キャリア濃度1
〜2X10’−のp+型InGaAsP層(厚み174
mm禁制帯輻0.9S@V)14゜T・添加、キャリア
濃度3〜4X10  ex  C1n型I nGaAa
P層(厚みljms禁制帯輔19Z4eV)15を順次
積層する。
First, as shown in FIG. 2 (&), undoped or 〒-doped carrier briquettes 2-5 x 10"aw-"0n-111n are deposited on the nmInP substrate 9 by liquid phase or vapor phase growth.
P layer (thickness 2 μm)10. T・added carrier concentration 3×1
017cm+-3 n-type InP layer (thickness 0.1-〇, 5
711!1) 11, undoped InGaAaP active layer (
Thickness Q, 2jams forbidden band width 0.95eV)12. Zn
P-type InP layer (thickness 2 nm) with doped carrier concentration 2 to 3 x l Q"am-' (thickness 2 nm) 13, Zn doped carrier concentration 1
~2X10'- p+ type InGaAsP layer (thickness 174
mm Forbidden band 0.9S@V) 14°T・addition, carrier concentration 3~4X10 ex C1n type I nGaAa
P layers 15 (thickness: 1jms, forbidden band: 19Z4eV) are sequentially laminated.

次に第2図山)の如く、n WIImG畠ム畠P層15
0表面に、真空蒸着及び通常のフォトリングラフィ法に
よって、AuあるいはAj郷の金属膜16をストライプ
状に設け、該金属マスク16をマスクとしてYAGレー
ザ光(波長1.06μm)17をパルス的に(1−IQ
 Joule 、 1 m秒以下)照射する。
Next, as shown in Figure 2), the n WIImG Hatakem Hatake P layer 15
A metal film 16 of Au or Aj is provided in stripes on the 0 surface by vacuum evaporation and ordinary photolithography, and YAG laser light (wavelength 1.06 μm) 17 is pulsed using the metal mask 16 as a mask. (1-IQ
joule, 1 msec or less).

この際金属マスク16以外のInGaAaP層15の表
面は8i0,18で覆っておく。表面より侵入したYA
Gレーザ光17はn型InGaAaP層15は透過し、
p+型T31GaAsP層14において選択的に吸収さ
れるためp+型InGaAsP層14は瞬時に加熱され
る。このため拡散係数の大きい不純物Znはp型InP
層13に侵入し、このためにp型InP層13中の不純
物Znは活性層12、n型InPクラクド層11.さら
にn−型InP層10に次々に押し込まれることになる
。この際押し込まれるZn0m度は低いので、 Znが
押し込まれてもn型InPクラッド層11の導電型は変
化しないが、n−型InP層10の導電型はn−型から
p−型に反転する。この場合、金属マスク16の下では
YAGレーザ光17が侵入しないために、上述した押し
込み現象は生じない。従って@2図(c)の如くn−型
InP層10の導電型は選択的にp−型に変換されるこ
とになる。次に金属マスク16をエツチングによって、
除去して第2図(d)のように8i0.膜18をマスク
としてZnを先端がp1型InGaAmPjll 4に
達するような選択拡散を行なって電流注入領域20を設
ける。次にsioオ[I[18を除去してplilミオ
−。かくして形成された半導体レーザ素子においては活
性層の上下に電流狭窄機構があるために電流は限定され
た領域にのみ流れることになり、しきい値電流宿度は大
巾に減少することになる。
At this time, the surface of the InGaAaP layer 15 other than the metal mask 16 is covered with 8i0,18. YA invaded from the surface
The G laser beam 17 is transmitted through the n-type InGaAaP layer 15,
Since it is selectively absorbed in the p+ type T31GaAsP layer 14, the p+ type InGaAsP layer 14 is instantaneously heated. Therefore, the impurity Zn with a large diffusion coefficient is p-type InP.
The impurity Zn in the p-type InP layer 13 penetrates into the active layer 12, the n-type InP cracked layer 11. Furthermore, they are pushed into the n-type InP layer 10 one after another. Since the degree of Zn pushed in at this time is low, the conductivity type of the n-type InP cladding layer 11 does not change even if Zn is pushed in, but the conductivity type of the n-type InP layer 10 is reversed from n-type to p-type. . In this case, since the YAG laser beam 17 does not penetrate under the metal mask 16, the above-mentioned pushing phenomenon does not occur. Therefore, as shown in Figure 2 (c), the conductivity type of the n-type InP layer 10 is selectively converted to the p-type. Next, the metal mask 16 is etched,
8i0. as shown in FIG. 2(d). Using the film 18 as a mask, selective diffusion of Zn is performed so that the tip reaches the p1 type InGaAmPjll 4, thereby providing a current injection region 20. Next, remove sio[I[18 and create plil]. In the semiconductor laser device thus formed, since there is a current confinement mechanism above and below the active layer, current flows only in a limited region, and the threshold current density is greatly reduced.

上述した実施例においては金属マスク16のストライプ
巾はlO〜201mとした。この場合の活性層下の電流
狭窄層190間の電流通過領域の巾は5〜15#mとな
る。また上述した実施例の説明で明らかなように電流注
入領域20と活性層12の下の電流狭窄層19との位置
合わせを行なう必要がないため、製造が非常に容易にな
るという利点がある。上述した実施例においては結晶成
長中にn−型InP層lOがp型に反転するのを防ぐ目
的でn II InP層を設けたが成長条件によっては
h型InP層11上を積まずにn−型InP層1層上0
上接活性層12を積層した場合でも同様にして電流狭窄
構造を作製できることは言うまでもない。
In the embodiment described above, the stripe width of the metal mask 16 was 10 to 201 m. In this case, the width of the current passing region between the current confinement layers 190 under the active layer is 5 to 15 #m. Further, as is clear from the description of the embodiments described above, there is no need to align the current injection region 20 and the current confinement layer 19 under the active layer 12, so there is an advantage that manufacturing becomes very easy. In the above-mentioned embodiment, the n II InP layer was provided for the purpose of preventing the n-type InP layer lO from being inverted to the p-type during crystal growth, but depending on the growth conditions, the n - type InP layer 1 layer 0
It goes without saying that even when the upper active layer 12 is laminated, a current confinement structure can be produced in the same manner.

また、上記実施例では発振効率等を考慮して。Further, in the above embodiment, oscillation efficiency and the like are taken into consideration.

活性層と高一度のp+型InGaAsP層14との間に
p型InP層13を挾んだが、活性層上に直接p+型I
nGaAsP層14を形成してもよい。
Although the p-type InP layer 13 was sandwiched between the active layer and the p+-type InGaAsP layer 14 of high degree, the p+-type I
An nGaAsP layer 14 may also be formed.

以上説明したように、本発明によれば活性層中に流れる
電流の広がりを抑制するための電流狭窄層を、高不純物
濃度層のレーザ光照射による局部加熱によって活性層下
の結晶内部に設けることができるため基板の加工が不必
要であるばかりでなく、電流注入領域をも電流狭窄層と
の位置合わせの工程を必要とせずに作製できる。
As explained above, according to the present invention, a current confinement layer for suppressing the spread of current flowing in the active layer is provided inside the crystal under the active layer by locally heating the high impurity concentration layer by laser beam irradiation. Not only is it unnecessary to process the substrate, but also the current injection region can be fabricated without the need for alignment with the current confinement layer.

なお、以上の実施例においては半導体発光素子として半
導体レーザを例にしたが発光ダイオードの場合について
も全く同様にして適用できることは言うまでもない。ま
た( AA! Ga ) AI 二重ヘテ目構造のよう
なInGaAaP/InP系以外のへテ四構造材料やシ
ングルへテロ構造、ホモ接合構造にも適用できる。
In the above embodiments, a semiconductor laser was used as an example of the semiconductor light emitting element, but it goes without saying that the present invention can be applied to a light emitting diode in exactly the same manner. It can also be applied to heterotetrastructure materials other than the InGaAaP/InP system, such as (AA!Ga)AI double heterostructure, single heterostructure, and homojunction structure.

かくして本発明の製造方法によれば、従来困難であった
。低しきい値電流、高効率畔の優れた特性を有する半導
体レーザ等の光半導体素子を歩留り良く容易に製作でき
ることになりその効果は大である。
Thus, according to the manufacturing method of the present invention, this has been difficult in the past. Optical semiconductor devices such as semiconductor lasers having excellent characteristics such as low threshold current and high efficiency can be easily manufactured with high yield, and the effect is great.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来例の製造工程を示す部分断面図、第2図
は本発明の一実施例の製造工程を示す部分断面図である
。 図において、l・・・n型半導体基板、2・・・pH半
導体層、3・・・n型クラッド層、4・・・活性層%5
・・・p型クラッド層、6・・・n型キャップ層、7・
・・不純物選択拡散層、8・・・電流通過領域、9・・
・n型IIF基板、10− n−型InP層、11”n
型1mPクテッド層、12− InGaAsP活性層、
13 =−p型ImPクラッド層、14− p+型In
GaAsP M s 15 ・= n型InGaAsP
キャップ鳩、16・・・金属マスク、17・・・YAG
レーザ光、18・・・810.膜、19・・・p″′型
InP電流狭窄層、20・・・電流注入領域、21・・
・p型電極522・・・n型電極、23・・・電流通過
領域。 ry (0) (1> (C) (d)
FIG. 1 is a partial sectional view showing the manufacturing process of a conventional example, and FIG. 2 is a partial sectional view showing the manufacturing process of an embodiment of the present invention. In the figure, l...n-type semiconductor substrate, 2...pH semiconductor layer, 3...n-type cladding layer, 4...active layer%5
... p-type cladding layer, 6... n-type cap layer, 7.
... Impurity selective diffusion layer, 8... Current passing region, 9...
・N-type IIF substrate, 10-n-type InP layer, 11”n
Type 1mP cutted layer, 12-InGaAsP active layer,
13 =-p type InP cladding layer, 14- p+ type In
GaAsP M s 15 ・= n-type InGaAsP
Cap pigeon, 16...metal mask, 17...YAG
Laser light, 18...810. Film, 19... p'' type InP current confinement layer, 20... current injection region, 21...
- P-type electrode 522...n-type electrode, 23... current passing region. ry (0) (1> (C) (d)

Claims (1)

【特許請求の範囲】[Claims] 活性層の片方の側に少なくともgi導電型の低湊度半導
体層を備え、反対の側に少なくとも第2導電型の高不純
物濃度半導体層を備えている層構造を形成する工程と、
前記高不純物濃度半導体層を局部的に加熱して、前記低
換度半導体層の導電型を選択的に反転させる工程とを有
することを特徴とする半導体発光素子の製造方法。
forming a layered structure comprising at least a gi conductivity type low-density semiconductor layer on one side of the active layer and at least a second conductivity type high impurity concentration semiconductor layer on the opposite side;
A method for manufacturing a semiconductor light emitting device, comprising the step of selectively inverting the conductivity type of the low conversion semiconductor layer by locally heating the high impurity concentration semiconductor layer.
JP57038553A 1982-03-11 1982-03-11 Manufacture of semiconductor light-emitting element Pending JPS58155787A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57038553A JPS58155787A (en) 1982-03-11 1982-03-11 Manufacture of semiconductor light-emitting element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57038553A JPS58155787A (en) 1982-03-11 1982-03-11 Manufacture of semiconductor light-emitting element

Publications (1)

Publication Number Publication Date
JPS58155787A true JPS58155787A (en) 1983-09-16

Family

ID=12528477

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57038553A Pending JPS58155787A (en) 1982-03-11 1982-03-11 Manufacture of semiconductor light-emitting element

Country Status (1)

Country Link
JP (1) JPS58155787A (en)

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