JPS58155747A - Ic substrate and manufacture thereof - Google Patents
Ic substrate and manufacture thereofInfo
- Publication number
- JPS58155747A JPS58155747A JP57038081A JP3808182A JPS58155747A JP S58155747 A JPS58155747 A JP S58155747A JP 57038081 A JP57038081 A JP 57038081A JP 3808182 A JP3808182 A JP 3808182A JP S58155747 A JPS58155747 A JP S58155747A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- electrodes
- electrode
- periphery
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000007772 electroless plating Methods 0.000 claims abstract description 5
- 230000002093 peripheral effect Effects 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims 2
- 229910052742 iron Inorganic materials 0.000 claims 1
- 239000013043 chemical agent Substances 0.000 abstract 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 15
- 239000011889 copper foil Substances 0.000 description 14
- 239000010410 layer Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000003599 detergent Substances 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 229940079593 drug Drugs 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Credit Cards Or The Like (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は識別カードなどに用いられるＩＣ基板に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an IC board used for identification cards and the like.
識別カードにおいて、ＩＣ基板をカード表面の凹部に埋
め込む形式のものは、第１図に示す如く、基板１の裏面
に設けた裏面電極２ＫＩＣ３が接続され、プラスチック
の保護層４で保護されており、裏面電極２は、外部端子
となる表面電極５とスルーホール６によシミ気的に接続
されている。このように形成されたＩＣ基板を、カード
７に予め設けられた凹部８に、プラスチックの接着剤に
よる充填層９によ＃）！１着されている。In the case of an identification card in which an IC board is embedded in a recess on the surface of the card, as shown in FIG. The back electrode 2 is airtightly connected to the front electrode 5, which serves as an external terminal, through a through hole 6. The IC board formed in this manner is placed in a recess 8 previously provided in the card 7 and filled with a filling layer 9 made of plastic adhesive. He came in first place.
しかしながら、このスルーホール６１１ｔ、 カードデ
ザイン上見映えが悪く、またＩＣ用電源（＋５Ｖ。However, this through hole 611t does not look good on the card design, and the IC power supply (+5V).
＋２５Ｖ 、 ＧＮＤ等）Ｋ対するスルーホール６の電
流容量のマージンが少な過ぎる欠点があった。さらに職
別カードを誤って衣服と共に洗濯する、などの際に、洗
剤などがスルーホール６の隙間より内部に浸入し、ＩＣ
１でも損傷するおそれがあり、さらに１識別カードに改
変を加えようとする者に、電極の位置を知らせるという
情報を与える、などの欠点を有するものであっ、た。There was a drawback that the margin of current capacity of the through hole 6 with respect to K (+25V, GND, etc.) was too small. Furthermore, if the job card is washed with clothes by mistake, detergent or the like may seep into the IC through the gap in the through hole 6.
However, even a single identification card may be damaged, and it also has disadvantages in that it provides information about the location of the electrodes to a person who attempts to alter the identification card.
本発明は、これらの欠点を除き、体裁がよく、電極の電
流容量が大であシ、薬剤が浸入するような隙間はなく、
を九、電極の位置の目印にならないように表裏の電極の
接続を行なったＩＣ基板及びその製法を提供することを
目的とするものである。The present invention eliminates these drawbacks, has a good appearance, has a large electrode current capacity, and has no gaps where drugs can enter.
(9) It is an object of the present invention to provide an IC substrate in which front and back electrodes are connected so as not to serve as a mark of the electrode position, and a method for manufacturing the same.
本発ＢＡＦｉ、基板の、表面側の電極と、裏面側の電極
とが、前記基板の周縁の外周面をわ友って電気的に接続
されていることを特徴とするＩＣ基板である。The present BAFi is an IC substrate characterized in that an electrode on the front side and an electrode on the back side of the substrate are electrically connected across the outer peripheral surface of the periphery of the substrate.
本発明の実施例を図面を用いて説明する。Embodiments of the present invention will be described using the drawings.
第２図、第３図、第４図において、基板素材であるキャ
リアフィルム１１の円形の周縁１２の内部が最終的な基
板１３の領域である。即ち、基板１３の周囲に穴１４を
環状に設け、保持部１５によって基板１３が、外側のキ
ャリアフィルム１１から支えられている。基板１３の表
面及び裏面には豪数個の表面電極１６及び裏面電極１７
が設けられている。表面電極１６及び裏面電極１７は、
銅などの金属膜の貼付、転写、金属の蒸着、メッキなど
で連続的に設けられた後、エツチング、機械的除去など
によシ溝状に隙間を設けて複数個の電極を形成する。表
面電極１６．裏面電極１７ともその外側は、基板１３０
周縁に達し、各々の穴１４に、表面電極１６及び裏面電
極】７が一つづつ臨んでいる。裏面中央の電極部１８は
ＩＣを載置する部分である。In FIGS. 2, 3, and 4, the area inside the circular periphery 12 of the carrier film 11, which is the substrate material, is the area of the final substrate 13. That is, a hole 14 is provided in an annular shape around the substrate 13, and the substrate 13 is supported from the outer carrier film 11 by a holding portion 15. Several front electrodes 16 and back electrodes 17 are provided on the front and back surfaces of the substrate 13.
is provided. The front electrode 16 and the back electrode 17 are
After being continuously provided by pasting, transferring, metal vapor deposition, plating, etc. with a metal film such as copper, a plurality of electrodes are formed by creating groove-like gaps by etching, mechanical removal, etc. Surface electrode 16. The outside of the back electrode 17 is connected to the substrate 130.
One front electrode 16 and one rear electrode 7 face each hole 14 at the periphery. The electrode section 18 at the center of the back surface is a section on which an IC is placed.
表面電極１６又は裏面電極１７の形成は穴１４を設ける
前でも後でもよい。The front electrode 16 or the back electrode 17 may be formed before or after the hole 14 is formed.
この状態で、基板】３の周縁１２の外周面１９は、絶縁
されている。In this state, the outer peripheral surface 19 of the peripheral edge 12 of the substrate 3 is insulated.
次に、第５図に示す如く、表面電極１６と裏面電４に１
７とを、無電解メッキなどによシ形成した接続部加によ
シ、基板１３の周縁１２（第２，３図）の外周面１９（
第４図）をわたって電気的に接続する。Next, as shown in FIG.
7 is formed by electroless plating or the like, and the outer circumferential surface 19 (
(Fig. 4).
その後、電解メッキによシ厚盛シを行ない、さらに金メ
ッキにて保−する。Thereafter, it is plated thickly by electrolytic plating, and then protected by gold plating.
次に１保持部１５より基板１３を切り離し、第６図に示
す如く、電極部１８ Ｋ ＩＣ３を装着し、金線２１に
よりワイヤポンディングを行なう。その後プラスチック
により保護層４を形成し、これを第１図に示す如くカー
ド７の凹部８に装填する。Next, the substrate 13 is separated from the holding part 15, and the electrode part 18K IC3 is attached as shown in FIG. Thereafter, a protective layer 4 is formed of plastic, and this is loaded into the recess 8 of the card 7 as shown in FIG.
本実施例は、以上の如く構成されているので、外部端子
となる表面電極１６には、スルーホールの如き穴はなく
、平坦であり、外見がよく、また、接続部加の断面積は
、幅及び厚さの選択によシ十分なる電流容量を確保する
ことができ、薬剤浸入を招く穴がなく、また、目印がな
いので外部端子であるかどうか区別が容易でないので、
カードの改変を予防することができる。Since the present embodiment is constructed as described above, the surface electrode 16 serving as an external terminal has no hole such as a through hole, is flat, has a good appearance, and has a cross-sectional area of the connecting portion. By selecting the width and thickness, a sufficient current capacity can be secured, there are no holes that allow chemicals to enter, and since there are no markings, it is not easy to distinguish whether it is an external terminal or not.
Modification of the card can be prevented.
第７図〜第１３図は、別の実施例の製法の過程を示す。7 to 13 show the manufacturing process of another embodiment.
基板素材１００表面と裏［Ｋ銅箔用の接着剤層２２を設
け、第８図の如く、ＩＣの基板１３となるべき部分の周
囲に電極の数と同じ数の穴１４を環状に設け（第２．３
図の穴１４と同様）、次に第９図の如く電極素材として
の導電体膜である銅箔２３ 、２４を表、裏に、穴１４
をおおって貼り着けて被覆する。この状態では、基板１
３の周縁１２の外周面１９は絶縁状態にある。An adhesive layer 22 for the K copper foil is provided on the front and back sides of the board material 100, and as shown in FIG. Section 2.3
(same as the hole 14 in the figure), then as shown in FIG.
cover and paste to cover. In this state, the board 1
The outer peripheral surface 19 of the peripheral edge 12 of No. 3 is in an insulated state.
次に、第１０図の如く、基板１３の周縁１２より少し離
れた位置にある刃２５と、段部％と、穴１４の外側付近
を切る刃２７を備えたカッター四を下降せしめて、穴１
４の部分の銅箔２３．ｕを、基板１３の周縁１２より少
しはみ出させた状態で切断し、さらにカッター詔を下降
せしめ段部銘により、はみ出した銅箔２３と為を台四に
押し付け、超音波振動を与えて銅箔２３と２４とを超音
波溶接によシミ気的に接続、或いは極めて近接せしめる
。Next, as shown in FIG. 10, the cutter 4, which is equipped with a blade 25 located a little away from the periphery 12 of the substrate 13, a blade 27 that cuts the stepped portion, and the vicinity of the outside of the hole 14, is lowered to make the hole. 1
Copper foil in section 4 23. Cut the copper foil 23 slightly protruding from the periphery 12 of the board 13, then lower the cutter blade and press the protruding copper foil 23 against the base plate 4 by applying ultrasonic vibration to cut the copper foil. 23 and 24 are airtightly connected by ultrasonic welding or brought very close to each other.
次に第１１図の如く、銅箔２３と冴の接続部或いは近接
部を、無電解メッキにより接続して電気的接続を行ない
、さらに電解メッキで厚盛りを行ない、さらに金メッキ
を施し、このようにして形成した接続部２０によシ、基
板１３の周縁１２の外周面１９をわたって表裏にまたが
って表の銅箔２３と裏の銅箔ムとが電気的Ｋｍ続される
。Next, as shown in FIG. 11, the connection part or the adjacent part of the copper foil 23 and the copper foil is connected by electroless plating to establish an electrical connection, and then a thick layer is applied by electrolytic plating, and then gold plating is applied. Through the connecting portion 20 formed in this manner, the copper foil 23 on the front side and the copper foil layer on the back side are electrically connected across the outer peripheral surface 19 of the peripheral edge 12 of the substrate 13 on the front and back sides.
次に第１２図に示す如くレジスト材３０を電極の形状に
応じて配備し、エツチングを行なって、銅箔を分離し第
１３図の如く銅箔パターンにより表面電極１６及び裏面
電極１７を形成する。Next, as shown in FIG. 12, a resist material 30 is placed according to the shape of the electrode, and etching is performed to separate the copper foil, forming a front electrode 16 and a back electrode 17 with a copper foil pattern as shown in FIG. .
このようにして形成された表面電極１６及び裏面電極１
７Ｆｉ、基板１３０周縁１２の外周面１９をわたって、
接続部２０により電気的に接続されている。The front electrode 16 and the back electrode 1 formed in this way
7Fi, across the outer peripheral surface 19 of the peripheral edge 12 of the substrate 130,
They are electrically connected by a connecting part 20.
エツチングの代りに機械的に銅箔の一部を除去して電極
を分離するようにしてもよい。この電極分離のプロセス
は、鋼箔ｎ、２４にて被覆を行なった（第９図）直後の
プロセスから、接続部２０を形成し九（第１１図）後の
プロセスまでの間の、何れの段階のプロセスにおいて行
なってもよい。Instead of etching, a portion of the copper foil may be mechanically removed to separate the electrodes. This electrode separation process can be carried out at any time from the process immediately after coating with the steel foil 24 (FIG. 9) to the process after forming the connection part 20 (FIG. 11). It may be done in a step process.
本発明によシ、必要な電流容量に対するマージンが十分
とれ、薬剤などが浸入するおそれがなく、また、外部電
極の位置が不明となり改変を防ぐことができるＩＣ基板
及びその製法を提供することができ、実用的に極めて大
なる効果を奏することができる。更に、識別カードなど
においてはカードのデザイン、印刷に与える障害がなく
なり体裁がよい。また、カードの発行会社や使用会社等
を表示する文字や図形を表面電極を用いて表示する場合
（即ち、表面電極自体の形を文字や図形の形とする場合
）に極めて好適である。According to the present invention, it is possible to provide an IC substrate that has a sufficient margin for the necessary current capacity, has no risk of infiltration of chemicals, and can prevent alterations since the positions of external electrodes are unknown. It is possible to achieve extremely great practical effects. Furthermore, in the case of identification cards, etc., there is no problem with the design and printing of the cards, and the appearance is good. Further, it is extremely suitable for displaying characters or figures indicating the issuing company or the company using the card using the surface electrode (that is, when the shape of the surface electrode itself is in the shape of characters or figures).
第１図は従来例の断面図、第２図〜第１３図は本発明の
実施例に関するもので、第２図は平面図、第３図は裏面
図、第４図は第２図の１−１線断面図、＃！５図、第６
図は製作過程を示す断面図、第７図ないし第１３図は別
の実施例における製作過程を示す断面図である。
１・・・基板、２・・・裏面電極、３・・・ＩＣ，４・
・・保護層、５・・・表面電極、６・・・スルーホール
、７・・・カード、８・・・凹部、９・・・充填層、１
１・・・キャリアフィルム、１２・・・周縁、１３・・
・基板、１４・・・穴、１５・・・保持部、１６・・・
表面電極、１７・・・裏面電極、１８・・・電極部、１
９・・・外周面、加・・・接続部、２１・・・金線、２
２・・・接着剤層、２３・・・銅箔、２４・・・銅箔、
２５・・・刃、が・・・段部、２７・・・刃、２８・・
・カッター、２９・・・台、３０・・・レジスト材。
特許出願人 共同印刷株式会社
代理人弁理士 端 山 五 −FIG. 1 is a cross-sectional view of a conventional example, FIGS. 2 to 13 are related to an embodiment of the present invention, FIG. 2 is a plan view, FIG. 3 is a back view, and FIG. -1 line sectional view, #! Figure 5, 6th
The figure is a sectional view showing the manufacturing process, and FIGS. 7 to 13 are sectional views showing the manufacturing process in another embodiment. 1... Substrate, 2... Back electrode, 3... IC, 4...
...Protective layer, 5...Surface electrode, 6...Through hole, 7...Card, 8...Recess, 9...Filling layer, 1
DESCRIPTION OF SYMBOLS 1...Carrier film, 12...Periphery, 13...
・Substrate, 14...hole, 15...holding part, 16...
Surface electrode, 17... Back electrode, 18... Electrode part, 1
9...Outer peripheral surface, processing...connection part, 21...gold wire, 2
2...Adhesive layer, 23...Copper foil, 24...Copper foil,
25...Blade, Ga...Step, 27...Blade, 28...
・Cutter, 29...stand, 30...resist material. Patent applicant Kyodo Printing Co., Ltd. Representative Patent Attorney Go Hatayama −
Claims (1)
記基板の周縁の外周面をわたって電気的、に＠続されて
いることを特徴とするＩＣ基板。 ２、基板の表面及び裏面に、同数の複数の電極を、それ
ぞれの電極が前記基板の側縁辺に達するように配備して
設け、対応する表側電極と裏側電極とを、前記基板の周
縁の外周面をわたって電気的接続を行なうことを特徴と
するＩＣ基板の製法。 五 前記電気的接続が無電解メッキ法にて行なわれる特
許請求の範囲第３項記載の製法。 ４、基板素材の、ＩＣ基板となるべき部分の周囲に電極
の数と同じ数の穴を環状に設け、次に鉄基板素材の表裏
を、前記穴をおおって導電体膜にて被覆し、次に前記穴
において、基板の周縁よシはみ出させて前記表側及び裏
側の導電体膜を切り取ると共に前記基板の周縁よりはみ
出た前記表側及び裏側の電極のはみ出し部を互に圧着し
て電気的接続を行なわしめ、前記基板素材に前記導電体
膜を被覆した直後のプロセスから、前記電気的接触を行
なわしめた後のプロセスまでのプロセスのうち、何れか
のプロセスにおいて、前記導電体膜を複数個の電極に分
離し、前記基板の周縁の外周面をわたって表裏にまたが
った複数個の電極を形成することを特徴とするＩＣ基板
の製法。[Claims] 1. An IC board characterized in that an electrode on the front side and an electrode on the back side of the substrate are electrically connected across the outer peripheral surface of the periphery of the substrate. . 2. The same number of electrodes are arranged on the front and back surfaces of the substrate so that each electrode reaches the side edge of the substrate, and the corresponding front and back electrodes are arranged around the outer periphery of the substrate. A method for manufacturing an IC board characterized by making electrical connections across its surface. 5. The manufacturing method according to claim 3, wherein the electrical connection is performed by electroless plating. 4. Provide the same number of holes as the number of electrodes in a ring around the part of the substrate material that will become the IC substrate, then cover the front and back sides of the iron substrate material with a conductive film covering the holes, Next, in the hole, the conductor films on the front and back sides are cut out so as to protrude beyond the periphery of the substrate, and the protruding portions of the electrodes on the front and back sides that protrude beyond the periphery of the substrate are crimped together for electrical connection. A plurality of the conductor films are applied in any one of the processes from immediately after coating the substrate material with the conductor film to after making the electrical contact. 1. A method for manufacturing an IC substrate, comprising forming a plurality of electrodes that are separated into electrodes and extend across the outer circumferential surface of the periphery of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57038081A JPS58155747A (en) | 1982-03-12 | 1982-03-12 | Ic substrate and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57038081A JPS58155747A (en) | 1982-03-12 | 1982-03-12 | Ic substrate and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58155747A true JPS58155747A (en) | 1983-09-16 |
| JPH0219977B2 JPH0219977B2 (en) | 1990-05-07 |
Family
ID=12515526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57038081A Granted JPS58155747A (en) | 1982-03-12 | 1982-03-12 | Ic substrate and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58155747A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62185072U (en) * | 1986-05-15 | 1987-11-25 | ||
| JPH01108798A (en) * | 1987-10-21 | 1989-04-26 | Nec Corp | Manufacture of printed wiring board |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5010564A (en) * | 1973-05-25 | 1975-02-03 |
-
1982
- 1982-03-12 JP JP57038081A patent/JPS58155747A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5010564A (en) * | 1973-05-25 | 1975-02-03 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62185072U (en) * | 1986-05-15 | 1987-11-25 | ||
| JPH0517269Y2 (en) * | 1986-05-15 | 1993-05-10 | ||
| JPH01108798A (en) * | 1987-10-21 | 1989-04-26 | Nec Corp | Manufacture of printed wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0219977B2 (en) | 1990-05-07 |
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